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Final review for Archimajor V4 release #2
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V0.4 Fixes design errors from V0.3
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@allspice-wayne I'm going to run DRCY here before we kick off our next design review meeting.
DRCY has reviewed this Design Review, and there should be a review posted below.
DRCY Connections Checker Review
DRCY reviewed the 7 pages that changed in this design review. It selected 449 components to review and found 57 potential issues in 173 components. DRCY posted a comment on the schematic for each issue. Component Details below lists every component DRCY reviewed.
Component Details
DRCY reviewed all connections of the following components:
Missing Datasheets
DRCY could not find datasheets for the parts below. Upload them to the repository and DRCY will use them in future reviews.
DRCY uses AI. Please verify the outputs.
[💡 Recommendation] Component
J10, pin3; ComponentC206, pin2: J10 pin 3 puts the 3.3VCC MCU rail on the cable with no current limit or ESD clamp.Observed: J10 pin 3, a contact on an external cable header, connects straight to the shared 3.3VCC rail. Nothing sits in series with it: no resistor, PTC or fuse. The only things on that pin are the 0201 6.3 V decoupling capacitor C206 and the rail itself. Of the two TVS paths, D33 clamps only the signal pin (NetD33_C, pin 1). Pin 3 has no clamp at all.
Requirement: C206 (CL03A104KQ3NNNC): any surge or ESD voltage across the part must stay below its 6.3 V rating. D33 protects only the line its cathode is connected to. No datasheet requires a current limit on an off-board supply pin, so treat that part as robustness practice.
Consequence: If the end-stop cable shorts pin 3 to GND, the shared 3.3VCC rail is pulled down with no current limit. That can brown out the MCU. ESD or surge energy coupled into pin 3 goes onto the rail and C206 without any clamp. How serious this is depends on the cabling and how exposed it is to ESD, which the schematic does not show.
Evidence:
Suggested repair: Add a small series resistor or PTC between 3.3VCC and J10 pin 3, and/or a TVS on that pin, so a cable fault or ESD cannot reach the MCU rail directly.
2 affected locations (one repeated pattern)
J10, pin `3`; ComponentC206, pin `2` (G004-F001)J7, pin `3`; ComponentC207, pin `2` (G005-F002)Component
J7, pin `3`; ComponentC207, pin `2`: J7 pin 3 puts unprotected 3.3VCC on the off-board cable; consider current limiting and ESD protection. (G005-F002)Observed: J7 pin 3 carries 3.3VCC straight to the off-board end-stop cable. It has no series current limit and no TVS. Only the signal pin (J7.1) gets D34 and the 1k series resistor R76. The only local part on pin 3 is C207, a 6.3 V-rated 0201 MLCC. 3.3VCC is the main logic rail: U8 VOUT feeds it, and it reaches 3.3VIO on the Microcontroller page through FB28.
Requirement: The CL03A104KQ3NNNC datasheet says surge and ESD voltages applied to the capacitor must not exceed its 6.3 V rating. The ESD9X datasheet describes clamping ESD on exposed lines to protect voltage-sensitive parts. No requirement mandates protecting an off-board supply pin, so this is a robustness item.
Consequence: ESD or a cable fault on the exposed J7.3 pin goes straight onto the shared logic rail. A cable short from pin 3 to GND would pull 3.3VCC into U8's current limit and collapse the MCU supply, resetting the board. Whether ESD damages anything depends on the total rail capacitance, which this page does not establish.
Evidence:
Suggested repair: Consider a series PTC or small resistor and/or a TVS on the 3.3VCC pin of each end-stop header.
Datasheets: C206, J10
Replace a datasheet: C206, C207, J10, J7
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[💡 Recommendation] Component
D13, pinsC, A: D13 EE_SPEC says 15 pF, but the ESD9X3.3ST5G datasheet gives 80 pF typical; correct the attribute.Observed: D13's EE_SPEC attribute is "3.3Vso 15pF", which says 15 pF. The datasheet for the part listed in D13's MPN (ESD9X3.3ST5G) gives a typical junction capacitance of 80 pF at VR = 0 V, 1 MHz.
Requirement: The component attributes should match the ordered part so that BOM, sourcing and signal-loading assumptions agree with what gets fitted.
Consequence: The metadata doesn't agree with itself. Someone substituting by EE_SPEC could pick a different, lower-capacitance TVS, or a later review could trust 15 pF of line loading. On this slow end-stop line, which already has 10 nF (C86), the extra capacitance does nothing functionally. The problem is documentation and procurement clarity.
Evidence:
Suggested repair: Change the EE_SPEC to match the ESD9X3.3ST5G datasheet (3.3 V VRWM, about 80 pF typ). If a 15 pF part was intended, change the MPN instead.
2 affected locations (one repeated pattern)
D13, pins `C, A` (G002-F001)D59, pins `C, A` (G008-F001)Component
D59, pins `C, A`: D59 EE_SPEC says 15 pF, but the ESD9X3.3ST5G datasheet gives 80 pF typical; fix the attribute. (G008-F001)Observed: D59's EE_SPEC attribute says "3.3Vso 15pF", so it records 15 pF of line capacitance for the ESD9X3.3ST5G.
Requirement: Component attributes should match the resolved part's datasheet. The ESD9X3.3ST5G datasheet gives a typical capacitance of 80 pF at VR = 0 V and 1 MHz.
Consequence: The library entry understates the diode capacitance by more than 5x. On this end-stop line the effect is negligible, because the 1 kΩ / 10 nF filter dominates. But anyone who reuses the library entry, or picks a substitute based on EE_SPEC, will get the wrong capacitance on faster lines.
Evidence:
Suggested repair: Change the EE_SPEC attribute to the datasheet value (80 pF typ), or check whether a different low-capacitance part was intended.
Datasheet: D13
Replace a datasheet: D13, D59
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[⚠️ Warning] Component
D34, pinsC, A; ComponentR75, pins1, 2: D34 VRWM (3.3 V max) is below the worst-case 3.3VCC idle level; pick a higher-VRWM TVS.Observed: D34 (ESD9X3.3ST5G) sits on NetD34_C. That net is pulled up to 3.3VCC through R76 (1k) and R75 (100K), so when the input is idle the cathode rests at the 3.3VCC level. 3.3VCC comes from U8, an MIC5353-3.3YMT-TR whose output accuracy is ±2% at 25 °C and ±3% from −40 to 125 °C. That puts the rail as high as about 3.37 V to 3.40 V before load and line regulation are added. D34's VRWM is 3.3 V max.
Requirement: The ESD9X3.3ST5G datasheet says the protected line's normal operating voltage should not exceed VRWM (3.3 V max). The 2.5 µA maximum leakage is only guaranteed at VR = 3.3 V.
Consequence: At the top of the regulator tolerance, D34 is biased above its rated working voltage. Its leakage is then no longer guaranteed to stay at or below 2.5 µA. That leakage flows through the ~101 kΩ pull-up, so the idle-high level at MIN_ES3 (U11A PA7) drops. At exactly 2.5 µA the level is already about 0.25 V low. Leakage above the rating cuts the logic-high margin further and gets worse with temperature. Because VBR is at least 5 V, a hard logic failure is unlikely, but the margin is not guaranteed by the datasheet.
Evidence:
Suggested repair: Use a TVS whose VRWM is above the worst-case 3.3VCC maximum, for example a 5 V-VRWM part in the same ESD9X family, and check the clamp voltage against PA7 with R76 in series. The alternative is to confirm the ESD9X3.3 leakage at 3.4 V and high temperature.
2 affected locations (one repeated pattern)
D34, pins `C, A`; ComponentR75, pins `1, 2` (G005-F001)D35, pins `C, A`; ComponentR78, pin `2` (G006-F001)Component
D35, pins `C, A`; ComponentR78, pin `2`: D35 TVS VRWM of 3.3 V is below the worst-case 3.3VCC idle level on the Z MAX endstop line. (G006-F001)Observed: D35 (ESD9X3.3ST5G, VRWM 3.3 V max) clamps NetD35_C to GND. R78 (100k) and R79 (1k) pull NetD35_C up to 3.3VCC, so the line sits at about the rail voltage whenever the endstop is open. 3.3VCC comes from U8, a MIC5353-3.3YMT-TR whose output is specified at ±2% at 25 °C and ±3% over temperature. That puts the rail as high as about 3.37–3.40 V, before line and load regulation are added. This exceeds D35's 3.3 V working peak reverse voltage.
Requirement: The ESD9X3.3ST5G datasheet says the protected line's normal operating voltage should not exceed VRWM (3.3 V max). The guaranteed leakage (2.5 µA max) applies only at VRWM.
Consequence: Whenever the rail sits above nominal, D35 runs above its rated working voltage. Its leakage is then not guaranteed. That leakage flows through the 101k pull-up path and lowers the idle-high level at the MCU input U11A PD9. Typical leakage is small and VBR is at least 5 V, so a functional failure is unlikely. Still, the operating point is outside the part's rated working range on all eight identical channels.
Evidence:
Suggested repair: Use a TVS with VRWM above the worst-case 3.3VCC, for example a 5 V VRWM ESD9X-series or equivalent part with a suitable clamp. Alternatively, confirm D35's leakage at 3.4 V and accept it with documented margin.
Datasheets: R75, D34
Replace a datasheet: D34, D35, R75, R78
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[💡 Recommendation] Component
J33, pins1, 2, 3: Connector Layout table omits the A-axis headers; add J32 (MIN) and J33 (MAX).Observed: The 'Connector Layout' text table on the page maps only X/Y/Z MIN/MAX to J5, J9, J6, J10, J7 and J11. The A-axis connectors J32 (MIN_ES4) and J33 (MAX_ES4) are not listed, although an 'A' label sits next to the ES4 channels.
Requirement: An assembly or connector-assignment table should cover every connector it describes, so that users wire end-stops to the correct header.
Consequence: The documentation leaves the A-axis MAX end-stop header unmapped, so it is easy to swap MIN and MAX wiring on that axis.
Evidence:
Suggested repair: Add an 'A' column (J32 = MIN, J33 = MAX) to the Connector Layout table.
Datasheet: J33
Replace a datasheet: J33
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[💡 Recommendation] Component
R19, pins1, 2: R19's library name is a KOA part but its MPN fields are Yageo; align the part metadata.Observed: R19's component name and description field is the KOA part RK73H1ETTP1001F. Its MANUFACTURER, MANUFACTURER #, PART and DISTRIBUTOR # attributes all call out Yageo RC0402FR-071KL (311-1.00KLRTR-ND). The same split appears on the other 1k series resistors on this page (R23, R72, R74, R76, R79, R191, R193).
Requirement: A component's identifying fields should name one orderable part, so a BOM built from any field buys the same part.
Consequence: The two candidate parts appear to be the same 0402 1 kΩ 1% value, so the circuit still works either way. But a BOM or assembly flow that reads the library name would order a different manufacturer's part than the one specified, which leaves sourcing ambiguous.
Evidence:
Suggested repair: Rename the library component, or point it at a Yageo RC0402FR-071KL symbol, so the name agrees with the manufacturer attributes.
5 affected locations (one repeated pattern)
R19, pins `1, 2` (G001-F001)R23, pins `1, 2` (G002-F002)R74, pins `1, 2` (G004-F002)R79, pins `1, 2` (G006-F002)R193, pins `1, 2` (G008-F002)Component
R23, pins `1, 2`: R23's library name (KOA RK73H1ETTP1001F) conflicts with its Yageo MPN; make the part fields consistent. (G002-F002)Observed: R23's symbol name is RK73H1ETTP1001F, which is a KOA part number. Its MANUFACTURER is Yageo and its MANUFACTURER # / PART is RC0402FR-071KL.
Requirement: A component's name, manufacturer and MPN fields should identify one orderable part so the BOM isn't ambiguous.
Consequence: BOM exports that read the library name instead of the MPN field could call out a different manufacturer's part. Both part numbers describe a 1 kΩ 1% 0402 1/16 W resistor, so the electrical impact is nil. The risk is purchasing and traceability confusion.
Evidence:
Suggested repair: Rename the library symbol to match the Yageo MPN, or list the KOA part as an approved alternate.
Component
R74, pins `1, 2`: R74's library name gives a KOA part but its MPN fields give Yageo; pick one or list both. (G004-F002)Observed: R74's library name and description point to a KOA part (RK73H1ETTP1001F). Its MANUFACTURER, MANUFACTURER # and PART fields point to Yageo RC0402FR-071KL. The DISTRIBUTOR # 311-1.00KLRTR-ND is a Yageo number.
Requirement: A component's part-number fields should name one orderable part, so the BOM and procurement are unambiguous.
Consequence: The two candidates are both 0402, 1 kΩ, 1%, 1/16 W, so this is not an electrical problem. It is a procurement and documentation ambiguity: different BOM tools could order different manufacturers.
Evidence:
Suggested repair: Align the library name and description with the MPN fields, or list the KOA part explicitly as an approved alternate.
Component
R79, pins `1, 2`: R79 symbol name (KOA RK73H) conflicts with its Yageo RC0402FR-071KL MPN; align the part identity. (G006-F002)Observed: R79's library name and description are KOA RK73H1ETTP1001F ('RES 0402 1k 63mW 1%'). Its MANUFACTURER, MANUFACTURER #, PART and DISTRIBUTOR # attributes name Yageo RC0402FR-071KL (Digi-Key 311-1.00KLRTR-ND).
Requirement: A component's identity fields should name a single manufacturer part, so the BOM and procurement are unambiguous.
Consequence: Both part numbers are 1k 1% 0402, so the circuit works either way. However, a BOM generated from the symbol name and one generated from the MPN field would order different manufacturers' parts.
Evidence:
Suggested repair: Rename the library symbol, or align its name and description with the Yageo MPN that is actually ordered. The same symbol is used by R76, R19, R23, R72, R74, R191 and R193.
Component
R193, pins `1, 2`: R193 library name (KOA RK73H) conflicts with its Yageo RC0402FR-071KL MPN; make the part identity consistent. (G008-F002)Observed: R193's library name and description refer to KOA RK73H1ETTP1001F, but MANUFACTURER #, PART and DISTRIBUTOR # all give Yageo RC0402FR-071KL.
Requirement: A component should carry one consistent manufacturer part identity so that BOM generation and procurement are unambiguous.
Consequence: A BOM built from the component name would order a different manufacturer's part than one built from the MPN attribute. Both are 1 kΩ 1% 0402, so this is a documentation and procurement inconsistency, not an electrical one.
Evidence:
Suggested repair: Align the library component name with the RC0402FR-071KL attribute set, or list the KOA part as an approved alternate.
Datasheet: R19
Replace a datasheet: R19, R193, R23, R74, R79
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[🚨 Error] Component
D53, pinA: D53 anode floats on single-pin net NetD53_A, so TACH_2's ground clamp is open; tie D53.A to GND.Observed: D53 (BAT54WX) is wired with K on NetD51_A, the node between R177 and R176 on the TACH_2 line. Its A pin is on NetD53_A, and nothing else connects to that net anywhere in the design, so the anode is left floating. The other three tach channels on this page have their low-side clamp anodes on GND: D52.A, D56.A and D57.A.
Requirement: A clamp diode only works if both terminals connect to their reference nodes. This channel's ground clamp needs D53's anode on GND, the same way it is done in the TACH_1, TACH_3 and TACH_4 channels.
Consequence: The external fan connector line (J22.3) has no clamp to ground. A negative transient or miswiring on the fan cable passes through R177 (1k) and R176 (1k) to the microcontroller's PD8 input with only C156 for filtering. Any negative excursion then has to be absorbed by the MCU's internal ESD structures. This channel ends up with less protection than the other three, and D53 is placed on the board but does nothing.
Evidence:
Suggested repair: Connect D53 pin A to GND, matching D52, D56 and D57.
2 affected locations (one shared root cause)
D53, pin `A` (G007-F001)J22, pin `3`; ComponentD53, pin `A` (G004-F003)Component
J22, pin `3`; ComponentD53, pin `A`: The D53 anode on the J22 tach clamp is unconnected; tie it to GND as in the other channels. (G004-F003)Observed: The Fan2 tach input J22.3 (NetJ22_3) passes through R177 to NetD51_A, which has the D51 clamp to 3.3VCC and the cathode of D53. The D53 anode is on NetD53_A, which has no other connection: a GND port sits near D53 but does not reach it. On the matching Fan1 channel, D52.A is tied to GND.
Requirement: The external tach input needs a working clamp toward GND to limit negative excursions, the same as the matching channels (D52, D56, D57 anodes to GND).
Consequence: Negative transients or ESD on the Fan2 tach pin are not clamped by D53. They reach TACH_2 and the MCU input through R177/R176, so the MCU's internal ESD structures have to absorb them, unlike the other three fan channels.
Evidence:
Suggested repair: Connect the D53 anode to GND, as done for D52.
Datasheets: J22, D53
Replace a datasheet: D53, J22
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[⚠️ Warning] Component
R187, pins1, 2; ComponentD54, pinsA, K; ComponentJ31, pins2, 3: R187 is underrated for 24 V VFAN reaching the J31.3 tach pin; size it for VFAN.Observed: R187 (1 kΩ, RC0402FR-071KL, 1/16 W) is the only series element between connector pin J31.3 (NetJ31_3) and the D54 Schottky clamp to 3.3VCC. The pin next to it, J31.2, carries VFAN. VFAN connects to VPWR through the 0 Ω R103, and VPWR is guarded by an SMAJ24A TVS (24 V stand-off). If J31.3 sits at VFAN, for example from a tach output that the fan pulls up to its own supply, a miswired fan, or a short between pins 2 and 3, R187 has about 24 − 3.3 − 0.4 ≈ 20 V across it. That is about 20 mA and about 0.41 W.
Requirement: For an RC0402 standard-power part the rated power is 0.0625 W at 70 °C. The rated continuous working voltage is V = sqrt(P×R), or 50 V if that is lower. For 1 kΩ this works out to about 7.9 V.
Consequence: If 24 V reaches the tach pin, R187 dissipates about 6.5 times its rating. The resistor can overheat or fail open, which removes the series limiting for the clamp or the tach path for this channel. About 20 mA is also pushed into 3.3VCC through D54.
Evidence:
Suggested repair: Use a higher-value or higher-power series resistor at R187, for example 10 kΩ or above, or a 0603/0805 part sized for VFAN minus 3.3 V continuous. Recheck the RC filter corner and the tach thresholds after the change.
2 affected locations (one repeated pattern)
R187, pins `1, 2`; ComponentD54, pins `A, K`; ComponentJ31, pins `2, 3` (G008-F001)R184, pins `1, 2`; ComponentJ31, pins `2, 3` (G008-F002)Component
R184, pins `1, 2`; ComponentJ31, pins `2, 3`: R184 pull-up is underrated if 24 V VFAN reaches J31.3; resize it for VFAN. (G008-F002)Observed: R184 (1.8 kΩ, RC0402FR-071K8L, 1/16 W) pulls J31.3 up directly to 3.3VCC, with no other element in the path. VFAN, a 24 V class rail through R103 from VPWR, is on the next pin, J31.2. With J31.3 at about 24 V, R184 has about 20.7 V across it. That is about 11.5 mA and about 0.24 W.
Requirement: For an RC0402 standard-power part the rated power is 0.0625 W at 70 °C. Rated working voltage is sqrt(P×R), about 10.6 V for 1.8 kΩ.
Consequence: If 24 V reaches the tach pin, R184 dissipates about 3.8 times its rating and pushes about 11.5 mA into 3.3VCC. The pull-up can be damaged, which would stop tach reading on this channel.
Evidence:
Suggested repair: Size the pull-up for VFAN to 3.3 V continuous, using higher resistance or a larger package, or add a series or blocking element that can take the fault voltage.
Datasheets: J31, R187, D54, R184
Replace a datasheet: D54, J31, R184, R187
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[⚠️ Warning] Component
R172, pin1; ComponentR175, pin2; ComponentQ12A, pin7; ComponentJ29, pins1, 3: TACH_1 tach is referenced to the low-side switched fan return; readings fail during Q12A PWM-off.Observed: The TACH_1 sense input is pulled up to 3.3VCC by R172 and is referenced to board GND (D52, C155). J29 pin 1, the fan's return/ground pin, does not go to GND. It goes to NetC154_2, the drain of the low-side switch Q12A, which U2D drives from the MCU signal Fan1. J29 pin 2 is VFAN, which comes from VPWR through the 0R jumper R103. VPWR carries an SMAJ24A TVS, which points to a supply of up to 24 V. So when Q12A is off, including the off part of each PWM cycle, the fan's ground floats up toward VFAN.
Requirement: A 3-wire fan's open-collector tach output switches against the fan's own ground pin. A ground-referenced tach input therefore only gives a valid count while that ground pin sits at board GND. When the fan's ground floats toward VFAN, the tach transistor can no longer pull NetJ29_3 low, and its internal junctions can push current from the fan supply into the pull-up node.
Consequence: If Fan1 is used as PWM, or the fan is switched off, TACH_1 cannot be pulled low during Q12A off-time. Pulses go missing or get distorted, so RPM readings and stall detection are wrong. While the fan's ground floats toward VFAN, current from the fan can also flow through J29.3 into R172 and R175/D50 and back into 3.3VCC. How much flows depends on the fan's internal circuit.
Evidence:
Suggested repair: Either drive Fan1 only fully on or off (and read tach only while it is on), or move the fan switch to the high side so the fan ground stays at GND. Another option is to add an isolated or high-voltage-tolerant tach front end, such as a small NPN/optocoupler stage referenced to the switched return.
Datasheets: J29, R175, R172, Q12A
Replace a datasheet: J29, Q12A, R172, R175
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[🚨 Error] Component
J30, pins1, 2; ComponentLED4, pinC; ComponentQ13B, pin5: The Fan 4 drain net is merged into VFAN, so J30, LED4 and the Q13B drain need their own switched return net.Observed: Every Fan 4 node that should sit on its own switched return is on VFAN. J30 pin 1 (fan return) and J30 pin 2 (fan supply) are both on VFAN. The LED4 cathode is on VFAN. The Q13B channel-2 drain (pin 5) is on VFAN, and so are TP17 and both pins of DNI C209. The Fan 3 copy of this circuit uses a separate drain net, NetC211_2, which joins Q13A.7, J31.1, the LED3 cathode, TP18 and C211.2. Fan 4 has no matching net.
Requirement: In a low-side fan switch, the drain of the NCV8402 channel goes to the load, and the load sits between the supply and the drain. So the fan return pin, the indicator cathode and the test point must share a dedicated drain net that is separate from VFAN.
Consequence: Fan 4 sees 0 V across J30 pins 1 and 2, so it can never run. LED4 has VFAN on both ends and can never light. When firmware asserts Fan4, U2A drives Q13B on and puts the VFAN/VPWR rail straight to GND. Q13B then sits in current limit at roughly 3.7 to 5 A and cycles in and out of thermal shutdown. That fault current also flows through the R103 0603 jumper and the supply, which can sag VPWR or damage the jumper or Q13B.
Evidence:
Suggested repair: Create a dedicated Fan 4 drain net (for example NetC209_2). Connect Q13B pin 5 (and pin 6), J30 pin 1, the LED4 cathode, TP17 and C209 pin 2 to it. Keep J30 pin 2 and C209 pin 1 on VFAN, matching the Fan 3 copy of the circuit.
2 affected locations (one shared root cause)
J30, pins `1, 2`; ComponentLED4, pin `C`; ComponentQ13B, pin `5` (G005-F001)Q13B, pins `5, 3`; ComponentJ30, pins `1, 2` (G003-F001)Component
Q13B, pins `5, 3`; ComponentJ30, pins `1, 2`: Q13B drain and J30 pin 1 are on VFAN, so turning on Fan4 shorts VFAN to GND; give it its own return net. (G003-F001)Observed: Q13B drain pin 5 (D) is on VFAN and its source pin 3 is on GND. The Fan4 return node never exists as its own net: J30 pin 1 and pin 2 are both on VFAN, LED4 cathode is on VFAN with R14 also going to VFAN, and DNI C209 has both pins on VFAN. The other three channels connect the switch drain to a separate return net: Q13A.7 to NetC211_2/J31.1, Q12A.7 to NetC154_2/J29.1 and Q12B.5 to NetC153_2/J22.1.
Requirement: A low-side switch drain has to connect to the load's return terminal, not to the load supply. The NCV8402 datasheet describes the drain as the pin that 'connects to the load', and its test circuits put the load between VDD and the drain with the source at ground.
Consequence: Whenever firmware drives Fan4 high, U2A turns Q13B on and VFAN/VPWR is shorted straight to GND through the switch. The current is limited only by the NCV8402's internal limit (about 3.7–5 A), so the device cycles in and out of thermal shutdown and the VPWR rail sags and is stressed. The fan on J30 has VFAN on both pins, so Fan 4 can never run, and LED4 never lights because its anode resistor and cathode are on the same net.
Evidence:
Suggested repair: Create a separate Fan4 return net and connect Q13B pin 5 (and pin 6), J30 pin 1, LED4 cathode, TP17 and C209 pin 2 to it, matching the Q12B/J22 channel. J30 pin 2 and C209 pin 1 stay on VFAN.
Datasheets: LED4, J30, Q13B
Replace a datasheet: J30, LED4, Q13B
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[⚠️ Warning] Component
Q12A, pin7; ComponentQ12B, pin5: Q12 symbol leaves drain pins 8 and 6 unconnected; add them to the drain nets.Observed: The Q12 symbol parts bring out only one drain pin per channel. Q12A has pins 1 (S), 2 (G) and 7 (D), and Drain 1 pin 8 has no symbol pin or net. Q12B has pins 3 (S), 4 (G) and 5 (D), and Drain 2 pin 6 has no symbol pin or net. The whole-design component lookup shows the same three pins for each part, so pins 6 and 8 have no net anywhere in the netlist.
Requirement: In the NCV8402ADDR2G SOIC-8 pinout, pins 7 and 8 are both Drain 1 and pins 5 and 6 are both Drain 2. Each drain pin is described as the pin that connects to the load. The datasheet also says the drain pins should connect to a large copper area, because RθJA is 157 °C/W on minimum pad and 77 °C/W on 625 mm² of 2 oz copper.
Consequence: The netlist leaves PCB pads 8 and 6 without a net. They stay electrically at drain potential through the package, but nothing requires them to be routed. Each channel's load current and drain heat sinking can end up going through a single pin and its copper, which cuts thermal and current margin compared with the datasheet mounting assumptions. Whether this matters depends on fan current, which this page does not show.
Evidence:
Suggested repair: Add the second drain pin to each Q12 symbol part (pin 8 on part A, pin 6 on part B) and tie it to the same drain net. Pour copper over both drain pins.
Datasheet: Q12A
Replace a datasheet: Q12A, Q12B
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[⚠️ Warning] Component
R96, pins1, 2; ComponentR12, pins1, 2: R96/R12 metadata conflicts between 4.7k and 10k; make PART and description match one value.Observed: R96 and R12 have VALUE = 4.7K, MANUFACTURER # = RC0402FR-074K7L and DISTRIBUTOR # = 311-4.7KLRTR-ND. The same parts also have component name '10k 1% 0402', PART = RC0402FR-0710KP and PART DESCRIPTION '10k Ohm ±1% ...'. Each part carries two different resistances.
Requirement: Every BOM field for a placed part has to name one orderable part, so assembly loads the intended resistance.
Consequence: A BOM or pick-and-place flow that reads PART or the description can fit 10k instead of 4.7k. That roughly halves the LED1/LED2 drive current and dims the indicators. It also changes the resistor dissipation and voltage stress, so the board as built would not match the reviewed design.
Evidence:
Suggested repair: Make the name, PART and PART DESCRIPTION match the chosen part (RC0402FR-074K7L, 4.7k), or pick 10k in every field. R14 and R15 carry the same conflict and should get the same fix.
2 affected locations (one repeated pattern)
R96, pins `1, 2`; ComponentR12, pins `1, 2` (G004-F001)R15, pins `1, 2`; ComponentR14, pins `1, 2` (G005-F002)Component
R15, pins `1, 2`; ComponentR14, pins `1, 2`: R15 and R14 list both 4.7K and 10K part numbers; settle on a single value and MPN. (G005-F002)Observed: R15 and R14 carry conflicting part data. VALUE = 4.7K and MANUFACTURER # = RC0402FR-074K7L, while the component name is '10k 1% 0402', PART = RC0402FR-0710KP and PART DESCRIPTION reads '10k Ohm'. Two different resistances and two different MPNs are on the same symbol.
Requirement: The BOM fields of each part must name a single resistance and orderable part number so that assembly installs the intended value.
Consequence: Depending on which field the BOM or assembler reads, either 4.7 kΩ or 10 kΩ gets fitted. That changes LED3/LED4 current by about 2x and changes resistor dissipation, which is near or over the rating on a 24 V fan rail (see the separate finding).
Evidence:
Suggested repair: Choose one value and update the name, VALUE, PART, MANUFACTURER #, DISTRIBUTOR # and description to match. The same fix applies to R96 and R12.
Datasheet: R96
Replace a datasheet: R12, R14, R15, R96
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[⚠️ Warning] Component
R96, pins1, 2; ComponentR12, pins1, 2: R96/R12 are overstressed when VFAN is 24 V; use a larger package or a higher resistance.Observed: The R96/R12 + LED1/LED2 chains connect VFAN to the fan low-side switch drain. VFAN ties straight to VPWR through the 0R jumper R103, and VPWR is protected by an SMAJ24A TVS (24 V standoff). With the switch on and VFAN = 24 V, each 4.7k resistor sees about 24 − 2.1 = 21.9 V. That gives about 4.7 mA and 21.9²/4700 ≈ 0.10 W.
Requirement: RC0402 standard-power resistors are rated 0.0625 W at 70 °C. Their continuous working voltage is limited to sqrt(P×R), which is about 17.1 V for 4.7k.
Consequence: With a 24 V supply and the fan running continuously, each resistor dissipates about 160% of its rated power and runs above its rated continuous working voltage. This risks overheating, resistance drift or early failure. At 12 V the dissipation is about 0.02 W, which is within rating.
Evidence:
Suggested repair: Use a larger package or higher-power resistor (0603 at 0.1 W or 0805 at 0.125 W), or raise the resistance (for example 10k gives about 0.048 W at 24 V, though at 10k the voltage is close to the sqrt(P×R) limit). Apply the same fix to R14/R15.
2 affected locations (one repeated pattern)
R96, pins `1, 2`; ComponentR12, pins `1, 2` (G004-F002)R15, pins `1, 2`; ComponentR14, pins `1, 2` (G005-F003)Component
R15, pins `1, 2`; ComponentR14, pins `1, 2`: The 4.7 kΩ 0402 LED resistors R15/R14 exceed 1/16 W on a 24 V VFAN; use 10 kΩ or a larger package. (G005-F003)Observed: R15 feeds LED3 from VFAN, and R14 is meant to feed LED4 the same way. The VALUE/MPN fields specify a 4.7 kΩ RC0402 (1/16 W) part. VFAN is jumpered to VPWR, which is protected by an SMAJ24A (24 V standoff), so the rail can be 24 V. At 24 V with a 2.1 V LED, the 4.7 kΩ resistor dissipates (21.9 V)²/4.7 kΩ ≈ 0.10 W. With the 10 kΩ variant it would be about 0.048 W. As drawn, R14 currently has no voltage across it because the LED4 cathode is on VFAN, so the overstress applies to R14 only once the Fan 4 net is fixed.
Requirement: RC0402 standard-power rated dissipation is 0.0625 W at 70 °C, derated linearly to 0 at 155 °C.
Consequence: With a 24 V supply, the fitted 4.7 kΩ 0402 runs at about 160% of its rated power whenever the fan is on. That leads to overheating and resistance drift or failure over time.
Evidence:
Suggested repair: Use 10 kΩ (about 0.048 W at 24 V and about 2.2 mA LED current, which is still visible). Alternatively, keep 4.7 kΩ in a 0603 or double-power package rated at least 0.125 W.
Datasheet: R96
Replace a datasheet: R12, R14, R15, R96
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[⚠️ Warning] Component
C55, pin2; ComponentU11C, pin56: VDDOUT bulk capacitor C55 is a low-ESR MLCC, below the regulator's 0.5–10 Ω ESR window.Observed: The only bulk capacitor on the regulator output (U11C pin 56 VDDOUT, which also feeds VDDCORE pins 10/45/61/104/124) is C55, a TDK C1608JB0J106K080AB 10 µF ceramic. Five 100 nF X7R MLCCs (C44, C52, C65, C68, C80) sit in parallel with it. No tantalum capacitor and no series resistor is fitted to put the output ESR inside the 0.5–10 Ω range.
Requirement: For regulator stability, the SAM3X datasheet requires a 4.7 µF output capacitor with ESR between 0.5 Ω and 10 Ω, placed between VDDOUT and the closest GND pin.
Consequence: MLCC ESR in this size is normally in the milliohm range, so the output ESR probably sits below the specified 0.5 Ω minimum. That can reduce phase margin on the internal 1.8 V regulator, which powers the core and, through FB26, the PLL. The possible result is ringing or oscillation on VDDCORE/VDDPLL under load steps, which could cause brown-out resets or clock instability. The actual effect depends on the capacitor's real ESR and the board parasitics, so this is a conditional risk, not a confirmed failure.
Evidence:
Suggested repair: Either fit a 4.7 µF tantalum (or polymer) capacitor whose specified ESR is within 0.5–10 Ω in place of C55, or add a series resistor of about 0.5–1 Ω in line with the 4.7–10 µF MLCC. Keep the 100 nF bypass capacitors. Alternatively, get Microchip confirmation that an all-MLCC output is stable on this part.
2 affected locations (one shared root cause)
C37, pin `2`; ComponentFB26, pins `1, 2`; ComponentC55, pin `2`; ComponentU11C, pin `56` (G003-F001)C55, pin `2`; ComponentU11C, pin `56` (G002-F001)Component
C37, pin `2`; ComponentFB26, pins `1, 2`; ComponentC55, pin `2`; ComponentU11C, pin `56`: VDDOUT, including C37 behind FB26, has only low-ESR MLCCs; add a 0.5–10 Ω ESR output capacitor. (G003-F001)Observed: The VDDOUT regulator output is loaded only by ceramic capacitors: C55, a 10 µF TDK C1608JB0J106K080AB MLCC, and five 100 nF X7R parts (C44, C52, C65, C68, C80). The output also sees C37, another 10 µF C1608JB0J106K080AB MLCC on VDDPLL, through FB26. FB26 is a CIS10P121AC bead with 0.03 Ω max DCR, so at regulator-loop frequencies C37 sits almost directly on VDDOUT. That puts about 20 µF of low-ESR ceramic on VDDOUT. No part in the network provides the 0.5–10 Ω ESR the regulator needs.
Requirement: For stability, the SAM3X datasheet requires a 4.7 µF output capacitor with ESR of 0.5–10 Ω (tantalum or MLCC) between VDDOUT and the closest GND pin.
Consequence: With about 20 µF of very low-ESR ceramic, the regulator runs outside its specified stability conditions. The result can be ringing or marginal stability on the 1.8 V core/PLL rail, with possible brownout resets or PLL jitter under load transients. The bead and the 10 µF also form a lightly damped LC that can resonate on VDDPLL.
Evidence:
Suggested repair: Add an output capacitor that meets the 0.5–10 Ω ESR window, such as a 4.7 µF tantalum or an MLCC with a series resistor of about 1 Ω. Alternatively, reduce the low-ESR bulk on VDDOUT. Consider dropping C37 to a smaller value or damping it so the FB26/C37 network does not add undamped bulk to the regulator output.
Datasheets: FB26, C37, U11C
Replace a datasheet: C37, C55, FB26, U11C
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[💡 Recommendation] Component
C40, pins1, 2: C40 returns NRSTB to 3.3VIO rather than VDDBU; tie C40 pin 2 to 3.3VCC.Observed: C40 (10 nF) sits between net RESET, which goes to U11B pin 47 (NRSTB), and 3.3VIO. 3.3VIO is the VDDIO rail and is fed from 3.3VCC through ferrite bead FB28. VDDBU (U11C pin 52) is on 3.3VCC, not on 3.3VIO.
Requirement: The SAM3X datasheet recommends an external 10 nF capacitor between NRSTB and VDDBU in harsh environments.
Consequence: The cap's reference is VDDIO behind a ferrite bead rather than the backup supply that powers NRSTB. Noise between the two rails can couple into the NRSTB glitch filter. This departs from the recommended connection, but the DC level is the same, so the effect is small.
Evidence:
Suggested repair: Connect C40 pin 2 to 3.3VCC (the VDDBU net) instead of 3.3VIO.
Datasheet: C40
Replace a datasheet: C40
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[⚠️ Warning] Component
C57, pins1, 2; ComponentU11C, pin57: C57 VDDIN capacitor is exactly 10 µF nominal with -10% tolerance; upsize to guarantee at least 10 µF.Observed: C57 (TDK C1608JB0J106K080AB, 10 µF ±10%, 6.3 V, 0603, JB dielectric) is the only 10 µF ceramic capacitor drawn in the VDDIN/VDDBU decoupling group on 3.3VCC. Its pin 2 is on 3.3VCC and pin 1 is on GND. The part is specified at exactly the required 10 µF nominal with a -10% tolerance, so it can measure as low as 9 µF before any DC-bias loss at 3.3 V on a 6.3 V-rated 0603 part. The supplier catalog does not define the JB dielectric, so nothing in the documents shows the capacitance it keeps under bias or across temperature.
Requirement: The SAM3X datasheet says a ceramic decoupling capacitor of 10 µF or more between VDDIN and the closest GND pin is mandatory.
Consequence: Under worst-case tolerance alone, the mandatory VDDIN input capacitance is not met (9 µF < 10 µF). DC-bias derating of a 6.3 V 0603 MLCC at 3.3 V would most likely reduce it further, though the catalog does not give that figure. The datasheet says this capacitor limits regulator startup current and sets transient response and noise rejection, so all of those margins shrink. How much depends on placement and on how much other 3.3VCC capacitance sits near pin 57.
Evidence:
Suggested repair: Raise the VDDIN capacitor so its effective value at 3.3 V stays at or above 10 µF. For example, use a 22 µF ceramic, or a 10 µF part with a higher voltage rating, X5R/X7R dielectric and a larger case, and confirm it with the manufacturer's DC-bias curve. Place it at VDDIN pin 57.
Datasheets: C57, U11C
Replace a datasheet: C57, U11C
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[⚠️ Warning] Component
U11A, pin110; ComponentC64, pin2: C64 on the U11A SPI0 SPCK node is installed with a TBD value and part; specify it or mark it DNI.Observed: U11A pin 110 (PA27/SPI0_SPCK) drives net NetC64_2 through R82 (24R). That net feeds U14 input A, the 1:4 clock fanout to the TC, M1 (SPI flash) and M2 buses. C64 is an installed (not DNI) 0402 capacitor from this node to GND. Its value, manufacturer, MPN and part description are all TBD.
Requirement: An installed BOM part needs a defined value and part number. Any capacitance on the SPI clock source node has to leave edges fast enough for every device clocked through U14.
Consequence: C64 cannot be bought or assembled as specified. Whatever value is fitted sets the RC edge at the source of every SPI clock in the system, including the SPI flash path.
Evidence:
Suggested repair: Either mark C64 DNI or assign it a specific value and MPN chosen against the SPI clock rate and the U14/U12 edge-rate requirements.
7 affected locations (one repeated pattern)
U11A, pin `110`; ComponentC64, pin `2` (G001-F003)C64, pins `1, 2`; ComponentU14, pin `2` (G018-F001)C74, pins `1, 2`; ComponentC75, pins `1, 2`; ComponentC87, pins `1, 2` (G022-F001)C83, pins `1, 2`; ComponentC88, pins `1, 2`; ComponentC89, pins `1, 2`; ComponentC90, pins `1, 2` (G021-F001)R84, pin `1`; ComponentR59, pin `1`; ComponentR89, pin `1`; ComponentR93, pin `1`; ComponentC83, pin `1`; ComponentC88, pin `1`; ComponentC89, pin `1`; ComponentC90, pin `1` (G020-F001)C101, pin `2`; ComponentC102, pin `2`; ComponentC104, pin `2`; ComponentC85, pin `2` (G019-F001)R3, pin `1`; ComponentR4, pin `1`; ComponentC101, pin `2`; ComponentC102, pin `2` (G018-F002)Component
C64, pins `1, 2`; ComponentU14, pin `2`: C64 on the U14 clock input is fitted but has TBD value and part number; define it or mark DNI. (G018-F001)Observed: C64 sits between NetC64_2 (U14 pin 2, input A, which R82 24R feeds from the MCU PA27/SPI0_SPCK pin) and GND. It is fitted (no DNI mark), but its VALUE, MANUFACTURER, MANUFACTURER #, PART, DISTRIBUTOR #, PART DESCRIPTION and EE_SPEC are all 'TBD'.
Requirement: A fitted BOM line needs a defined value and orderable part number before it can be bought and placed. Here the value also sets the edge rate of the only SPI clock source that feeds every SCLK bus.
Consequence: The board cannot be procured or assembled as drawn. A placeholder value picked at build time could slow the SPCK edge at U14 or attenuate it. All four buffered clock buses (TC, M1 with the SPI flash, M2, and the external PA27_SCLK) would then be affected at once.
Evidence:
Suggested repair: Choose a value for C64 (for example a small pF-range filter cap sized against the 24R plus MCU ODT source and the target SPI clock rate) and give it a real MPN, or mark it DNI if it is only a footprint option.
Component
C74, pins `1, 2`; ComponentC75, pins `1, 2`; ComponentC87, pins `1, 2`: C74, C75 and C87 on the U16 MISO inputs are installed with TBD value and MPN; define or DNI them. (G022-F001)Observed: C74 (MISO_TCBUS), C75 (MISO_M1BUS) and C87 (MISO_M2BUS) are installed. They are not marked DNI and sit from each U16 A input (pins 2, 5 and 9) to GND. Every procurement field on all three reads TBD: VALUE, MANUFACTURER, MANUFACTURER #, PART, PART DESCRIPTION, EE_SPEC and DISTRIBUTOR #.
Requirement: Every installed part needs a defined value and orderable part number before the BOM can be bought and assembled. Any value chosen here also has to keep the edge at each U16 A input faster than the SN74LVC125A input transition limit of 8 ns/V (125 V/µs minimum slew). Unused or slow inputs must not sit at undefined levels.
Consequence: The BOM cannot be bought or assembled as released, because three installed positions have no part defined. If someone later picks a value without checking the U16 slew limit and the SPI clock rate, a large capacitor could slow MISO edges past the U16 input transition limit. That would corrupt or delay readback from the TMC5160 drivers, the MAX31856 thermocouple converters and the SPI flash.
Evidence:
Suggested repair: Either mark C74, C75 and C87 DNI, or give each a defined value and MPN. Pick a value small enough that the RC with the 47R source resistors keeps the input transitions inside the U16 8 ns/V limit at the intended SPI clock.
Component
C83, pins `1, 2`; ComponentC88, pins `1, 2`; ComponentC89, pins `1, 2`; ComponentC90, pins `1, 2`: MOSI filter capacitors C83, C88, C89 and C90 are installed with TBD value and part number; specify them or mark them DNI. (G021-F001)Observed: C83 (MOSI_TCBUS), C88 (MOSI_M1BUS), C89 (MOSI_M2BUS) and C90 (PA26_MOSI) all go to GND and are marked installed, with no DNI flag. Their VALUE, MANUFACTURER, MANUFACTURER #, PART, PART DESCRIPTION, EE_SPEC and DISTRIBUTOR # fields all read 'TBD'.
Requirement: An installed BOM line needs a defined value and an orderable part number before it can be bought and placed. Each of these capacitors forms an RC low-pass with its 47R series resistor (R84, R59, R89, R93) on a live SPI MOSI line, so its value sets the edge rate the downstream SPI receivers see.
Consequence: The BOM cannot be procured or assembled as drawn. Assembly will either stop or proceed with an arbitrary value or an empty pad. If an arbitrary value is too large, MOSI edges at the MAX31856, TMC5160 drivers, SPI flash and external headers slow down and SPI transfers can fail. Whether it is too large also depends on the clock-line caps and SPI rate, which are not set.
Evidence:
Suggested repair: Choose a value for each capacitor from the SPI clock rate and receiver timing, and fill in the MPN and voltage rating. Alternatively, mark the capacitors DNI if they are only optional placeholders.
Component
R84, pin `1`; ComponentR59, pin `1`; ComponentR89, pin `1`; ComponentR93, pin `1`; ComponentC83, pin `1`; ComponentC88, pin `1`; ComponentC89, pin `1`; ComponentC90, pin `1`: MOSI RC capacitors C83/C88/C89/C90 after R84/R59/R89/R93 are installed with TBD value; define or DNI them. (G020-F001)Observed: Each U17 MOSI fan-out output goes through a 47R series resistor: R84 to MOSI_TCBUS, R59 to MOSI_M1BUS, R89 to MOSI_M2BUS and R93 to PA26_MOSI. Each of those nets then has a shunt capacitor to GND: C83, C88, C89 and C90. All four capacitors are installed (none is marked DNI), and their VALUE, MANUFACTURER #, PART and EE_SPEC fields are all 'TBD'.
Requirement: An installed BOM part needs a defined value and part number before it can be bought and assembled. On a SPI data line, a shunt capacitor after a 47R source resistor sets the edge rate, so its value has to be chosen to suit the SPI clock rate.
Consequence: With no defined part, the BOM for these four capacitors can't be bought or assembled. If the value is guessed too large, the 47R·C time constant slows MOSI edges at the stepper-driver and thermocouple inputs and can corrupt SPI data at the intended clock rate.
Evidence:
Suggested repair: Pick a value for each capacitor so that 47R·C stays well below the SPI bit period (small-pF parts are typical; check the result against the SPI clock rate), or mark them DNI if they are only optional edge-rate placeholders.
Component
C101, pin `2`; ComponentC102, pin `2`; ComponentC104, pin `2`; ComponentC85, pin `2`: Clock filter caps C101, C102, C104 and C85 are installed with TBD value and part; specify them or mark DNI. (G019-F001)Observed: C101 (SCLK_TCBUS), C102 (PA27_SCLK), C104 (SCLK_M1BUS) and C85 (SCLK_M2BUS) each sit from a buffered SPI clock branch to GND and are marked installed. Their VALUE, MANUFACTURER, MANUFACTURER #, PART, PART DESCRIPTION and EE_SPEC fields are all 'TBD', and none carries a DNI attribute.
Requirement: A part marked installed needs a defined value and orderable part number so it can be bought and assembled. For a capacitor that loads a clock line, the value sets the RC edge rate together with the 47R series resistors R3/R4/R13/R32.
Consequence: The BOM cannot be bought or assembled as drawn. The parts will either be placed with an arbitrary value or left off without a DNI record. A value that is too large would slow the SCLK edges to the TMC5160 drivers, the SPI flash and the MAX31856 and limit the usable SPI clock rate.
Evidence:
Suggested repair: Choose a value for each capacitor (typically a few pF to tens of pF as an edge-rate filter after the 47R terminations) and fill in the MPN. If they are only optional footprints, mark them DNI.
Component
R3, pin `1`; ComponentR4, pin `1`; ComponentC101, pin `2`; ComponentC102, pin `2`: C101/C102 at the R3/R4 clock outputs are fitted with TBD values; define them or mark DNI. (G018-F002)Observed: R3 (47R) feeds SCLK_TCBUS from U14 Y1, and C101 shunts that net to GND. R4 (47R) feeds PA27_SCLK from U14 Y2, and C102 shunts that net to GND. C101 and C102 are both fitted, and their value and part fields are all 'TBD'.
Requirement: The series-R/shunt-C networks on the buffered clock outputs need defined, orderable capacitor values. Without them the clock edge filtering set by R3/R4 is undefined, and the BOM is incomplete.
Consequence: The thermocouple SPI clock and the external SPI header clock (J20.2, and J13.9 through R139) have no defined edge shaping, and the build cannot be procured. Too large a value placed later would round SCLK edges on these buses and add delay.
Evidence:
Suggested repair: Set C101 and C102 to defined values with MPNs, picked together with R3/R4 for the intended SPI clock rate, or mark them DNI.
Datasheets: U14, U11A, R84
Replace a datasheet: R3, R4, R59, R84, R89, R93, U11A, U14
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[⚠️ Warning] Component
D64, pinC; ComponentD65, pinC; ComponentD66, pinC; ComponentD67, pinC; ComponentD68, pinC; ComponentD69, pinC: SD-line ESD diodes D64–D69 are about 80 pF each, not the 15 pF in their metadata; use low-capacitance parts.Observed: Six ESD9X3.3ST5G diodes sit on the microSD lines: D67 on MCCK, D66 on MCCDA, and D65, D64, D69 and D68 on MCDA0 to MCDA3. Each part's EE_SPEC attribute says "3.3Vso 15pF". The datasheet for this exact part gives a typical capacitance of 80 pF at VR = 0 V, 1 MHz. Each SD line connects straight from U11A to J18, so it carries the full diode capacitance in parallel with the card and the trace.
Requirement: The capacitance recorded in the part metadata, and used to accept these diodes for HSMCI, must match the selected part. The datasheet says this capacitance loads the protected line and should be checked against signal speed.
Consequence: Each SD clock, command and data line carries about 5× the capacitance the design records (80 pF typical vs 15 pF). This slows MCCK and data edges and cuts timing margin at higher HSMCI clock rates, and the card may fail to work or work unreliably at full-speed clocks. The mismatch also means anyone who checks the 15 pF attribute will wrongly conclude the loading is acceptable.
Evidence:
Suggested repair: Swap D64–D69 for a low-capacitance ESD part rated for SD/high-speed data (a few pF or less), or limit the HSMCI clock to a rate that has been checked against the full 80 pF load. Then correct the EE_SPEC attribute to match the part you use.
Datasheet: D64
Replace a datasheet: D64, D65, D66, D67, D68, D69
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[⚠️ Warning] Component
R100, pin2; ComponentD70, pinA; ComponentD74, pinA; ComponentD75, pinA; ComponentD76, pinA; ComponentU16, pin4: CS_M1BUS rises slowly through R100 10k into U16 nOE2, breaking the LVC125A edge-rate limit; buffer nOE2 with a gate.Observed: Nothing drives CS_M1BUS (U16 nOE2) high except the 10 kΩ pull-up R100. The net also carries five reverse-biased BAT54 anodes (D70, D74, D75, D76, D77) plus the nOE2 input. The datasheets put that load at up to about 55 pF: 5 × 10 pF max junction capacitance plus 5 pF typical input capacitance. When all motor and flash CS lines go high, the RC time constant is up to about 0.55 µs. Near the switching threshold the edge rises at only a few V/µs. Even the input capacitance alone (about 5 pF, τ ≈ 50 ns) gives roughly 36 V/µs. The falling edge is fine because the MCU pulls it down hard through a diode.
Requirement: For the SN74LVC125A, the input transition rise/fall rate must be no slower than 8 ns/V, i.e. at least 125 V/µs.
Consequence: The nOE2 input of U16 sits in its linear region for hundreds of ns on every deassert edge. This breaks the datasheet input-edge requirement. It can cause extra supply current, or the enable can chatter, glitching MISO onto the shared NetR94_2/PA25_MISO node. Buffer 2 also stays enabled for about 0.5 µs after the motor or flash CS is released. If firmware selects a thermocouple or M2 device within that window, U16 Y2 and the other buffer outputs drive NetR94_2 at the same time.
Evidence:
Suggested repair: Drive nOE2 from a real logic gate instead of the diode-AND plus pull-up. For example, use a multi-input AND gate of M_nCSA–D and SPIFLASH_CS, or a Schmitt-trigger buffer (e.g. 74LVC1G17) between CS_M1BUS and U16 pin 4. If you keep the resistor approach, also allow a deassert delay in firmware before switching buses.
2 affected locations (one repeated pattern)
R100, pin `2`; ComponentD70, pin `A`; ComponentD74, pin `A`; ComponentD75, pin `A`; ComponentD76, pin `A`; ComponentU16, pin `4` (G023-F001)R97, pin `2`; ComponentU16, pin `10` (G024-F001)Component
R97, pin `2`; ComponentU16, pin `10`: R97's 10k pull-up gives U16 nOE3 a rising edge far slower than the LVC125A's 8 ns/V limit. (G024-F001)Observed: When the M_nCSE–H chip selects are released, the 10 kΩ pull-up R97 alone pulls CS_M2BUS back high. The diodes and the MCU only drive this net low. On the rising edge, R97 has to charge U16 nOE3 (Ci ≈ 5 pF typical) plus the junction capacitance of the four BAT54 anodes (up to 10 pF each) and the trace. That gives an RC time constant of about 50 ns at best and up to roughly 450 ns. The starting slew rate is therefore about 3 V/50 ns ≈ 60 V/µs at best, and about 7 V/µs with the diode capacitance included.
Requirement: The SN74LVC125A input transition rate (Δt/ΔV) must be no slower than 8 ns/V, which is a minimum slew of 125 V/µs. U16 is the SN74LVC125ARGYR; its datasheet does not distinguish packages for this limit.
Consequence: Each time an M2-bus chip select is released, U16 nOE3 spends tens to hundreds of nanoseconds in the threshold region. This input has no Schmitt trigger and is outside its rated transition rate, so buffer 3 can chatter on and off. It can glitch MISO_M2BUS onto the shared NetR94_2 → R94 → PA25_MISO node. It also releases that shared node later than the firmware would expect, which raises the risk of contention with U16 Y1/Y2 if the TC or M1 bus chip select is asserted right afterwards.
Evidence:
Suggested repair: Drive nOE3 from an actively driven logic gate, for example a 74LVC1G08/'21-style AND of the four chip selects, or put a Schmitt-trigger buffer (74LVC1G17) between CS_M2BUS and nOE3. As a lesser fix, lower R97 to about 1 kΩ: the MCU sinks about 3.3 mA, within the 9 mA IOL rating, and the edge gets about 10× faster. The same topology is used on CS_TCBUS (R95) and CS_M1BUS (R100) and should be checked the same way.
Datasheets: D70, R100, U16
Replace a datasheet: D70, D74, D75, D76, R100, R97, U16
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[⚠️ Warning] Component
R142, pins1, 2; ComponentR140, pins1, 2; ComponentR144, pins1, 2; ComponentR141, pins1, 2; ComponentR139, pins1, 2; ComponentR143, pins1, 2; ComponentJ13, pins1, 4, 5, 6, 7, 8, 9: J13 SC2 lines reach MCU pins through 100R only, with no ESD or 5 V clamping, while the header supplies +5VCC.Observed: J13 (SC2) is an off-board 2x5 header, and its pin 1 carries +5VCC. Its signal pins pass through 100R resistors only:
None of these lines has a TVS or clamp. The PA3_AD2, PB25_TIOA0, PB27_TIOB0 and PA29_CS nets have only the MCU pin and the series resistor. By contrast, J28's off-board UART and NRST lines on the same page do have ESD9X3.3ST5G diodes (D71/D72/D73).
Requirement: The ATSAM3X8EA allows at most -0.3 V to 4.0 V on any input pin (absolute maximum), and VDDIO runs at no more than 3.6 V. An off-board connector should stop accessory logic levels and ESD from pushing the MCU pins past this limit.
Consequence: An accessory powered from J13's +5VCC pin may use 5 V logic. If it drives PA3, PB25 or PB27 high, the U11A pin sees about 5 V, above the 4.0 V absolute maximum. Only 100R plus the roughly 36 ohm on-die termination limits the injection current, to around 10 mA. Cable ESD on these unprotected off-board lines also goes straight into the MCU pins (or into the U14/U17 buffer outputs for SCLK/MOSI). Either case risks latch-up or pin damage. How severe this is depends on the accessory's logic level, which the schematic does not show.
Evidence:
Suggested repair: If SC2 accessories may be 5 V logic, add level translation or clamping (for example a series resistor plus clamp to 3.3 V, or a 5 V-tolerant buffer) on the MCU-direct inputs. Either way, add low-capacitance TVS diodes (such as the ESD9X3.3ST5G already used for J28) on J13 pins 4 through 10 next to the connector. Alternatively, document that SC2 accessories must use 3.3 V logic.
6 affected locations (one repeated pattern)
J28, pins `2, 4, 6, 7, 3, 8`; ComponentD73, pin `C`; ComponentD72, pin `C` (G007-F001)J12, pins `1, 3, 4, 5, 6, 7, 8, 9, 10`; ComponentR109, pins `1, 2`; ComponentR120, pins `1, 2` (G014-F001)R136, pins `1, 2`; ComponentR133, pins `1, 2`; ComponentR135, pins `1, 2`; ComponentR137, pins `1, 2`; ComponentR134, pins `1, 2`; ComponentR114, pins `1, 2`; ComponentJ12, pins `1, 3, 4, 5, 6, 7, 9` (G015-F001)R138, pins `1, 2`; ComponentJ13, pins `1, 10` (G012-F001)J13, pins `4, 5, 6, 7, 8, 9, 10`; ComponentR138, pin `2` (G012-F002)R142, pins `1, 2`; ComponentR140, pins `1, 2`; ComponentR144, pins `1, 2`; ComponentR141, pins `1, 2`; ComponentR139, pins `1, 2`; ComponentR143, pins `1, 2`; ComponentJ13, pins `1, 4, 5, 6, 7, 8, 9` (G013-F001)Component
J28, pins `2, 4, 6, 7, 3, 8`; ComponentD73, pin `C`; ComponentD72, pin `C`: J28 supplies 5V beside unbuffered 3.3V MCU UART/ERASE pins; add series resistance or level translation. (G007-F001)Observed: J28 puts +5VCC on pins 3 and 8 next to MCU signals with no series resistance and no level translation. PA9_UTXD (pin 2) and PA8_URXD (pin 4) go straight to U11A pins 2 and 27; ERASE (pin 7) goes straight to U11A pin 130. The only parts on those nets are the ESD9X3.3ST5G diodes D72, D73 and D1. NRST (pin 6) reaches the MCU only through a 100R resistor (R149) on the USB page. The page labels the header 'SERIAL + 5V', which means it powers an external serial device from 5 V. By comparison, the J12 and J13 signals on this page each have a 100R series resistor.
Requirement: No SAM3X input pin may go above 4.0 V with respect to ground (absolute maximum). The ESD9X3.3ST5G is not a clamp at 5 V: its minimum breakdown is 5.0 V, so it gives no protection against a 5 V logic driver.
Consequence: Suppose a device powered from the header's 5 V uses 5 V logic, as many 5 V serial adapters and modules do. It would push PA8_URXD (and ERASE or NRST, if it drives them) above the 4.0 V absolute maximum. Current would flow through the MCU's internal protection into VDDIO, limited only by the driver's impedance. This can latch up or damage the MCU, and it can back-feed the 3.3VIO rail. A 5 V level held on ERASE for more than 220 ms also erases the Flash.
Evidence:
Suggested repair: Add series resistors (for example 100R–1k, matching J12/J13) on J28 pins 2, 4 and 7. For 5 V-logic accessories, add a level translator or 5 V-tolerant buffer on the MCU input lines. Otherwise, document and key the header as 3.3 V-logic only.
Component
J12, pins `1, 3, 4, 5, 6, 7, 8, 9, 10`; ComponentR109, pins `1, 2`; ComponentR120, pins `1, 2`: J12 supplies 5 V to a module, but its signals reach 3.3 V MCU pins through only 100 Ω with no protection. (G014-F001)Observed: J12 pin 1 supplies +5VCC to whatever plugs into the SC1 header. Signal pins 3 to 10 go to U11A port pins through 100 Ω series resistors and nothing else: PC2 (pin 59), PA1 (pin 24), PA16 (pin 78), PA0 (pin 23), PA12 (pin 5), PA15/CTS1 (pin 8, via R120), PA13 (pin 6) and PA14/RTS1 (pin 7, via R109). None of these lines has a level translator, buffer, or clamp/TVS. The serial header J28, by comparison, has ESD9X3.3 clamps D72/D73 on its UART lines.
Requirement: The ATSAM3X8EA inputs must stay between -0.3 V and 4.0 V relative to ground (absolute maximum), and VIH max is VDDIO + 0.3 V.
Consequence: A module powered from J12's +5VCC that drives 5 V logic levels would push these MCU pins above the 4.0 V absolute maximum. Only about 136 Ω (100 Ω plus the ~36 Ω on-die termination) would limit the injected current, which would be several mA per pin through the I/O protection structures into 3.3VIO. That risks latch-up or damage to U11, and the unclamped lines are also open to ESD at the connector. Whether this happens depends on the logic level of the module that is fitted.
Evidence:
Suggested repair: Either restrict SC1 to 3.3 V-logic modules and document that on the silkscreen, or add 5 V-tolerant buffering or level translation (for example LVC-family parts on the inputs). Alternatively, raise the series resistance and add ESD9X3.3-type clamps on the J12 signal lines, as J28 already has.
Component
R136, pins `1, 2`; ComponentR133, pins `1, 2`; ComponentR135, pins `1, 2`; ComponentR137, pins `1, 2`; ComponentR134, pins `1, 2`; ComponentR114, pins `1, 2`; ComponentJ12, pins `1, 3, 4, 5, 6, 7, 9`: J12 SC1 signal lines have no ESD/overvoltage protection beside a +5V pin; add TVS clamps. (G015-F001)Observed: Six J12 signal pins reach SAM3X pins through only a 100 Ω series resistor: pin 3 via R137 to PC2, pin 4 via R136 to PA1/CANRX0, pin 5 via R135 to PA16, pin 6 via R134 to PA0/CANTX0, pin 7 via R133 to PA12/RXD1 and pin 9 via R114 to PA13/TXD1. No TVS or clamp sits on any of these nets. J12 pin 1 carries +5VCC to the off-board device, so a powered peripheral sits on this header, and pin 1 is next to pin 3 in the odd-numbered row. The other connectors on this page are protected: the J28 UART lines have ESD9X3.3 parts (D72, D73), the microSD lines have D64–D69, and the J20 lines have varistors RV1–RV4.
Requirement: SAM3X absolute maximum for voltage on input pins is −0.3 V to 4.0 V. Signals leaving the board on a connector need ESD protection to match that limit, and so does any path where a 5 V peripheral or a fault can drive these pins.
Consequence: An ESD hit on the J12 header is applied to the MCU pins through only about 100 Ω plus the ~36 Ω on-die termination. If a 5 V-logic peripheral powered from J12 pin 1 drives PA1/CANRX0 or PA12/RXD1, or pin 3 is shorted to pin 1, the inputs go above the 4.0 V absolute maximum. The only current limit is then the series resistor feeding the internal clamp, which risks latch-up or damage. Whether this happens depends on the module that is attached.
Evidence:
Suggested repair: Add low-capacitance 3.3 V TVS diodes, such as the ESD9X3.3ST5G already used on J28, on the J12 side of each series resistor. If 5 V-logic modules may be attached, add level translation or clamping on the MCU input lines.
Component
R138, pins `1, 2`; ComponentJ13, pins `1, 10`: SC2 MISO via R138 reaches the 3.3 V MCU unbuffered while J13 supplies 5 V; add level translation. (G012-F001)Observed: J13 (SC2) pin 1 supplies +5VCC to the off-board peripheral. J13 pin 10 is that peripheral's MISO input to the board. It passes through R138 (100R) to PA25_MISO, then through R83 (24R) to U11A pin 108 (PA25/SPI0_MISO). There is no level translator or clamp in this path. The onboard MISO buses do pass through U16, a 5V-tolerant SN74LVC125A, but the SC2 MISO line skips U16 and lands directly on the MCU pin.
Requirement: ATSAM3X8EA input pins have an absolute maximum of -0.3 V to 4.0 V relative to ground, and VIH max is VDDIO + 0.3 V.
Consequence: An SC2 peripheral powered from the 5 V that J13 provides may drive MISO with 5 V CMOS levels. That puts PA25 above its 4.0 V absolute maximum. The only current limit is about 124 ohm (R138 + R83), which allows on the order of 10 mA of clamp injection, so the MCU pin can be stressed or damaged. The same 5 V would also back-drive U16's outputs. Whether this happens depends on the peripheral's logic level, which the page does not define.
Evidence:
Suggested repair: Route the SC2 MISO line through a 5V-tolerant buffer or level shifter powered at 3.3 V, like the U16 channels. Alternatively, document and enforce that SC2 peripherals must use 3.3 V I/O even though the header supplies 5 V.
Component
J13, pins `4, 5, 6, 7, 8, 9, 10`; ComponentR138, pin `2`: J13 SC2 signal pins other than NRST lack ESD clamps; consider adding them as on J28 and J20. (G012-F002)Observed: Of the J13 off-board signal pins, only pin 3 (NRST, through R145) has an ESD clamp (D71). Pins 4 through 10, including MISO through R138, have only 100R series resistors to the MCU. The other off-board headers on this page do have protection: J28 serial lines (D72, D73) and the J20 Ethernet-pin lines (RV1-RV4).
Requirement: Design consistency and robustness. Other user-accessible headers on this page clamp their signal lines to GND. No datasheet requirement mandates it.
Consequence: ESD on the shrouded off-board SC2 header reaches the SAM3X I/O through only 100R, which lowers ESD robustness compared with the other headers.
Evidence:
Suggested repair: Consider adding low-capacitance 3.3 V ESD clamps (such as ESD9X3.3ST5G, already used here) on the J13 signal lines.
Datasheets: J28, R109, D73
Replace a datasheet: D72, D73, J12, J13, J28, R109, R114, R120, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144
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[💡 Recommendation] Component
U12, pin1; ComponentD77, pinsA, K: U12 CS# has no dedicated pull-up; add 10k from SPIFLASH_CS to 3.3VCC.Observed: U12 CS# (pin 1, SPIFLASH_CS) has no pull-up resistor of its own to 3.3VCC. On this page the net connects only to U11A PB21 (pin 92), TP74 and the cathode of D77. The only pull-up path is R100 (10k to 3.3VCC on CS_M1BUS), which reaches CS# forward through D77. That path is lost whenever another CS_M1BUS member is low, because M_nCSA–D pull the D70/D74/D75/D76 anodes low.
Requirement: The U12 datasheet recommends a 10 kΩ pull-up from CS to VCC so CS rises with VCC at power-up, for correct power-up sequencing.
Consequence: CS# idles high only through the R100+D77 path and the MCU's weak internal pull-up. While the MCU is in reset, or if a motor-driver CS on M1 is held low, CS# has no well-defined high level. That makes unintended selection or a missed power-up sequencing state more likely. This is a robustness gap, not a demonstrated failure.
Evidence:
Suggested repair: Add a dedicated 10k pull-up from SPIFLASH_CS (U12 pin 1) to 3.3VCC, close to U12.
Datasheets: D77, U12
Replace a datasheet: D77, U12
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[🚨 Error] Component
U11A, pins29, 30; ComponentJ4, pins6, 8: U11A PB29/TDI and PB30/TDO are crossed to J4, breaking JTAG and SWO; swap the nets.Observed: U11A pin 29 (PB29/TDI, the JTAG data input) is on net TDO/SWO, which goes to J4 pin 6. U11A pin 30 (PB30/TDO/TRACESWO, the JTAG data output and SWO trace output) is on net TDI, which goes to J4 pin 8 and the R37 pull-up. TMS/SWDIO (pin 31) and TCK/SWCLK (pin 28) are wired correctly.
Requirement: The debugger's TDI line has to drive the MCU's TDI input (PB29). The MCU's TDO/TRACESWO output (PB30) has to reach the header's TDO/SWO contact. Otherwise JTAG scan and SWO trace cannot work.
Consequence: JTAG mode through J4 cannot work: the debugger's TDI drive lands on the MCU's TDO output, and the debugger reads TDO from the MCU's TDI input. SWO trace output never reaches J4 pin 6. SWD programming over SWDIO/SWCLK still works.
Evidence:
Suggested repair: Swap the two nets at U11A. Put PB29/TDI (pin 29) on the J4 pin 8 TDI net and PB30/TDO/TRACESWO (pin 30) on the J4 pin 6 TDO/SWO net. Check that the R37 pull-up and test points TP50/TP53 end up on the intended signals.
2 affected locations (one shared root cause)
U11A, pins `29, 30`; ComponentJ4, pins `6, 8` (G001-F001)J4, pins `6, 8`; ComponentU11A, pins `29, 30` (G006-F001)Component
J4, pins `6, 8`; ComponentU11A, pins `29, 30`: J4 TDO/SWO and TDI are swapped onto U11A PB29/PB30; swap them so pin 6 gets PB30. (G006-F001)Observed: J4 pin 6 (TDO/SWO) is wired through net TDO/SWO to U11A pin 29, which the symbol names PB29/TDI. J4 pin 8 (TDI) is wired through net TDI to U11A pin 30, which the symbol names PB30/TDO/TRACESWO. So the probe's TDO/SWO input lands on the MCU's TDI input, and the probe's TDI output lands on the MCU's TDO/TRACESWO output.
Requirement: On a Cortex 10-pin debug header, pin 6 must carry the target's TDO/SWO output and pin 8 must carry the target's TDI input. On this MCU the symbol puts TDI on PB29 and TDO/TRACESWO on PB30. JTAGSEL is tied low, which selects the SWJ-DP port, so the JTAG pins are live after reset.
Consequence: JTAG through J4 cannot work: the probe drives the MCU's TDO output and listens on the MCU's TDI input, so the scan chain is broken. SWO trace also fails, because TRACESWO (PB30) reaches pin 8, not pin 6. Only 2-wire SWD (pins 2 and 4) works.
Evidence:
Suggested repair: Swap the connections: J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI). Rename the nets and move test points TP50/TP53 and pull-up R37 to match.
Datasheet: U11A
Upload/replace a datasheet: J4, U11A
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[⚠️ Warning] Component
J18, pins7, 8; ComponentU11A, pins107, 81: J18 pins 7/8 are named DAT1/DAT0 but carry MCDA0/MCDA1; check against the Molex drawing.Observed: J18's symbol labels pin 7 as DAT1 and pin 8 as DAT0. Pin 7 is on net MCDA0, which goes to U11A pin 107 (PA21/MCDA0). Pin 8 is on net MCDA1, which goes to U11A pin 81 (PA22/MCDA1). Read by pin name, the host's data-line 0 lands on the card's DAT1 and data-line 1 lands on DAT0. The Molex specification for this part gives no contact-by-contact signal assignment, so the documentation cannot settle whether the pin names or the pin numbers are the wrong half of the symbol.
Requirement: The host's data-line 0 (MCDA0) must reach the card's DAT0 contact, because SD 1-bit mode and card start-up use DAT0 only. Data-line 1 (MCDA1) must reach DAT1. The connector symbol's pin names and pin numbers must both match the manufacturer's contact map, so the netlist and footprint can be checked against it.
Consequence: If the physical contacts follow the symbol names, MCDA0 drives the card's DAT1. The card would then fail in 1-bit mode and at start-up (no data or busy signalling on the line the host reads), and 4-bit transfers would scramble bits. If the physical contacts follow the pin numbers, the board works, but the schematic labels are wrong and will mislead anyone bringing up or debugging the board.
Evidence:
Suggested repair: Check J18's symbol and footprint against the Molex SD-47571 sales drawing. Fix whichever is wrong (pin names or pin numbers) so that MCDA0 goes to the card's DAT0 contact and MCDA1 to DAT1.
2 affected locations (one shared root cause)
U11A, pins `107, 81`; ComponentJ18, pins `7, 8` (G001-F002)J18, pins `7, 8`; ComponentU11A, pins `107, 81` (G009-F001)Component
U11A, pins `107, 81`; ComponentJ18, pins `7, 8`: U11A MCDA0/MCDA1 go to J18 pins named DAT1/DAT0; confirm the connector pinout and fix the symbol or wiring. (G001-F002)Observed: U11A pin 107 (PA21/MCDA0) is on net MCDA0, which goes to J18 pin 7. The J18 symbol names pin 7 DAT1. U11A pin 81 (PA22/MCDA1) is on net MCDA1, which goes to J18 pin 8, named DAT0. MCDA2 goes to DAT2 and MCDA3 to CD/DAT3.
Requirement: HSMCI MCDAn has to reach card DATn. In 1-bit SD mode the card returns data only on DAT0, and the host samples it on MCDA0.
Consequence: There are two possibilities. If the J18 pin names are right, MCDA0 and MCDA1 are swapped at the card: 1-bit SD transfers fail and 4-bit data is scrambled. If the pin numbers are right and only the names are wrong, the wiring works but the schematic misdocuments the interface. As drawn, the schematic cannot settle which is the case.
Evidence:
Suggested repair: Check J18 pin numbering against the Molex SD-47571 drawing. Then either fix the symbol's pin names or swap the MCDA0/MCDA1 connections so that MCDA0 lands on the physical DAT0 contact.
Datasheets: J18, U11A
Replace a datasheet: J18, U11A
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[💡 Recommendation] Component
J20, pins5, 6, 7, 9, 10, 12: Six J20 pins are left open without no-connect markers; connect them or mark them NC.Observed: J20 pins 5, 6, 7, 9, 10 and 12 each sit alone on their own net (NetJ20_5/6/7/9/10/12) with no other connection and no no-connect marker. On the same header, pins 11, 13, 14 and 17 do carry explicit no-connect markers.
Requirement: Every connector pin should either be connected to its intended signal or be explicitly marked as an intentional no-connect, so that the netlist and ERC show the design intent.
Consequence: Because some open pins are marked and others are not, it is unclear whether those six pins are meant to be open or are connections that were forgotten for the mating expansion board. Unmarked open pins also produce ERC warnings, which can hide real ones.
Evidence:
Suggested repair: Confirm the J20 expansion pinout. Then either connect pins 5, 6, 7, 9, 10 and 12 to their intended signals or add no-connect markers.
Upload a datasheet: J20
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[⚠️ Warning] Component
R40, pins1, 2; ComponentR71, pins1, 2; ComponentJ20, pins21, 22: R40/R71 1k TWI pull-ups exceed the 3 mA I2C sink budget at J20; use 2.2k–4.7k.Observed: R40 (1k) pulls PA17_SDA up to 3.3VIO and R71 (1k) pulls PA18_SCL up to 3.3VIO. These are the only pull-ups on the two TWI0 lines, which also run straight to expansion header J20 pins 22 and 21 with no isolation. When a device pulls a line to VOL = 0.4 V, it has to sink (3.3 − 0.4)/1k ≈ 2.9 mA at nominal 3.3 V. With VDDIO at its 3.6 V maximum that becomes ≈ 3.2 mA. Any pull-up on the plugged-in module adds to this current.
Requirement: The I2C bus pull-up has to be weak enough that every device on the bus can hold VOL ≤ 0.4 V at its rated sink current. Standard-mode and Fast-mode I2C devices are only required to sink 3 mA, so Rp(min) = (VDD − 0.4 V)/3 mA ≈ 0.97 kΩ at 3.3 V and ≈ 1.07 kΩ at 3.6 V. The SAM3X itself sinks 6–9 mA at VOL 0.4 V, so the MCU is not the limit.
Consequence: An off-board I2C device on J20 that is only rated for 3 mA sink sits at or just over its limit with 1k pull-ups. This is worse at the high end of the 3.3 V tolerance or if the module brings its own pull-ups. Its VOL can then rise above 0.4 V, which eats into the low-level noise margin and can cause intermittent bus errors. The 1k values only stay within spec if every connected device is Fast-mode Plus (20 mA) capable.
Evidence:
Suggested repair: Raise R40/R71 to about 2.2k–4.7k, which still gives adequate rise time for 100/400 kHz on a short header bus. Alternatively, document that only Fast-mode Plus devices may be attached and that modules must not add their own pull-ups.
Datasheet: R40
Upload/replace a datasheet: J20, R40, R71
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[💡 Recommendation] Component
U11A, pin84: U11A PA3 net is named PA3_AD2 but PA3 is ADC channel AD1; rename the net.Observed: U11A pin 84, whose symbol name is PA3/TIOB1/PWMFI1/AD1/WKUP1, is on a net named PA3_AD2. That net goes to J13 pin 6 through R142.
Requirement: Net names that state an ADC channel should match the pin's actual alternate function, so that firmware picks the right channel.
Consequence: Firmware or users of the J13 header may set up ADC channel 2 for this signal, which would actually read PA4 (M_nCSA) instead of PA3.
Evidence:
Suggested repair: Rename the net PA3_AD1.
Datasheet: U11A
Replace a datasheet: U11A
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[⚠️ Warning] Component
D14, pinC; ComponentD10, pinC; ComponentD11, pinC; ComponentQ1, pinTAB; ComponentQ2, pinTAB; ComponentQ3, pinTAB: D14/D10/D11 RSB39V clamp at 35–43 V, above the 40 V VDS of Q1–Q3, so the drains are not protected.Observed: D14, D10 and D11 (RSB39VTE-17) are the only devices from the drain nodes HTR1, HTR2 and HTR3 straight to GND. They are meant to protect the Q1–Q3 CSD18503Q5A drains. The RSB39V zener voltage is 35.1 V min to 42.9 V max, and that range is measured at only 1 mA. At real transient currents the clamp voltage will be higher still.
Requirement: A drain-to-GND clamp has to hold the node below the MOSFET's absolute-maximum VDS of 40 V at the transient current it is expected to absorb.
Consequence: Even at 1 mA, a high-tolerance part can let the drain go past the 40 V VDS rating before it conducts. At surge-level current, the 200 mW ESD diode would either clamp higher or fail. So D14, D10 and D11 do not make sure Q1–Q3 stay inside VDS(max), and the protection the rationale counts on is not delivered.
Evidence:
Suggested repair: Rely on the D6–D8 freewheel diodes to VPWR, together with the VPWR rail TVS. Alternatively, swap in a power-rated TVS whose maximum clamp voltage at the expected peak current is below 40 V and whose breakdown is above the VPWR surge clamp.
3 affected locations (one repeated pattern)
D4, pins `C, A`; ComponentQ4, pin `TAB` (G010-F001)D14, pin `C`; ComponentD10, pin `C`; ComponentD11, pin `C`; ComponentQ1, pin `TAB`; ComponentQ2, pin `TAB`; ComponentQ3, pin `TAB` (G008-F001)Q1, pin `TAB`; ComponentD14, pins `C, A` (G003-F002)Component
D4, pins `C, A`; ComponentQ4, pin `TAB`: D4 breakdown (up to 42.9 V) exceeds Q4's 40 V VDS rating; use a lower-clamp power TVS. (G010-F001)Observed: D4 (RSB39VTE-17) is the only device on this page that clamps HTBD-OUT, the Q4 drain, to GND. Its Zener voltage at 1 mA can be anywhere from 35.1 V to 42.9 V. Q4 (CSD18503Q5A) is rated for VDS 40 V max, with BVDSS 40 V min. D4 is also a 200 mW ESD-protection part, not a power-surge TVS. The schematic attributes describe it as 'TVS DIODE 30VWM' with a VALUE of 30V.
Requirement: A clamp that protects a MOSFET drain has to break down below the MOSFET's VDS absolute maximum, with margin, at the surge current it will actually carry. Q4 VDS is 40 V max. D4 VZ can reach 42.9 V at only 1 mA, and its rated dissipation is only 200 mW.
Consequence: An overvoltage on HTBD-OUT, such as a transient coupled in through the off-board heated-bed wiring at J3 or a VBED surge passed through D15, can take Q4 past its 40 V rating before D4 conducts. Even when D4 does conduct, its 200 mW rating means it cannot absorb any significant energy. As a result, D4 adds capacitance but gives Q4 no dependable protection against overvoltage.
Evidence:
Suggested repair: Replace D4 with a power TVS whose clamping voltage at the expected surge current is below 40 V. One example is a unidirectional SMAJ-class part with about 26–28 V standoff, which also clears the 24 V VBED rail. Alternatively, choose Q4 with a higher VDS rating, for example 60 V.
Component
Q1, pin `TAB`; ComponentD14, pins `C, A`: D14 can clamp Q1's drain as high as 42.9 V, above Q1's 40 V VDS rating; use a lower-clamping TVS. (G003-F002)Observed: Drain net HTR1 of Q1 goes out to heater connector J1.1. The only clamp from HTR1 to GND is D14 (RSB39VTE-17), a bidirectional zener with VZ 35.1–42.9 V at 1 mA. Q1's absolute-maximum VDS is 40 V.
Requirement: Drain-source voltage must stay at or below Q1's 40 V absolute maximum. A shunt clamp meant to protect Q1 should clamp below that rating across its tolerance and pulse current.
Consequence: A transient on the external heater lead (for example ESD at J1) can push Q1's drain above 40 V before D14 conducts, and D14's clamp rises further at pulse current. Q1 then has to absorb the energy in avalanche. Q1 has an avalanche rating (EAS 157 mJ), so whether it is damaged depends on the transient's energy.
Evidence:
Suggested repair: Pick an HTR1-to-GND clamp whose maximum clamp voltage at the expected pulse current is below 40 V while its standoff stays above the VPWR rail, or use a higher-VDS MOSFET.
Datasheets: D4, Q4
Replace a datasheet: D10, D11, D14, D4, Q1, Q2, Q3, Q4
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[⚠️ Warning] Component
D14, pinsC, A; ComponentD10, pinsC, A; ComponentD11, pinsC, A: D14/D10/D11 breakdown (35.1 V min) is below D22's 38.9 V VPWR clamp, so a surge can overstress them through the heater.Observed: VPWR is clamped by D22 (SMAJ24A, attribute '24Vrs 38.9Vc') on Power.SchDoc. When Q1–Q3 are off, HTR1–HTR3 sit at VPWR through the heater load. D14, D10 and D11 begin to conduct as low as 35.1 V, which is inside the range VPWR can reach during a surge before D22 clamps it at 38.9 V. In that range each 200 mW RSB39V is wired across VPWR through the heater, and only the heater resistance limits its current.
Requirement: A local clamp's breakdown voltage has to stay above the highest voltage the upstream rail clamp lets through. Otherwise its steady-state or surge power must stay within its rating, and the datasheet says not to exceed rated power under steady-state loading.
Consequence: If VPWR goes above about 35 V (an overvoltage or surge that D22 has not clamped yet), the ESD diodes can draw heater-limited current far beyond what 200 mW allows. They could then fail short and leave a heater switched on regardless of what the MOSFET is doing.
Evidence:
Suggested repair: Remove D14/D10/D11, or replace them with parts whose minimum breakdown is above the VPWR clamp level of D22 and whose maximum clamp is still under 40 V. If that window cannot be met, tighten the VPWR rail clamp instead.
Datasheet: D14
Replace a datasheet: D10, D11, D14
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[⚠️ Warning] Component
Q1, pin4; ComponentR53, pin2; ComponentR52, pin2: Q1 gate has no pulldown to GND; add a gate-source resistor so the heater stays off when U3 is unbiased.Observed: Gate net NetQ1_4 connects only to Q1.4 (G), R52.2, R53.2 and test point TP58. There is no resistor from gate to source/GND, so the only path that holds the gate low is through R53 (100R) into U3 SINK. That path works only while U3 and its input are biased. NetQ1_4 is page-local.
Requirement: The ZXGD3009E6 typical low-side application circuit includes an external gate-to-source resistor R2 from the MOSFET gate to ground/VEE.
Consequence: If +5VCC is missing or late while VPWR is present, or if U3 is open or damaged, Q1's gate has no defined DC path to ground. Leakage or Cgd coupling from the drain can then bias Q1 partly or fully on (VGS(th) min 1.5 V) and run the HTR1 heater with no control. In a heater channel that is a thermal-runaway hazard.
Evidence:
Suggested repair: Add a gate-to-source resistor (for example 10k–100k) from NetQ1_4 to GND next to Q1, as in the datasheet's R2.
4 affected locations (one repeated pattern)
Q1, pin `4`; ComponentR53, pin `2`; ComponentR52, pin `2` (G003-F001)Q2, pin `4`; ComponentU4, pins `4, 6` (G004-F001)Q3, pin `4`; ComponentU5, pins `4, 6` (G005-F001)Q4, pin `4`; ComponentR25, pin `2`; ComponentR27, pin `2` (G006-F001)Component
Q2, pin `4`; ComponentU4, pins `4, 6`: Q2 gate has no gate-to-source pull-down; add a resistor from NetQ2_4 to GND. (G004-F001)Observed: Q2's gate net (NetQ2_4) connects only to Q2.4, R55.2 (10R to U4 SOURCE), R20.2 (100R to U4 SINK) and test point TP62. Nothing on the page ties the gate to GND or to Q2's source. NetQ2_4 is page-local, so no other page adds a pull-down. The only pull-down in the channel is R39 (10k), and it sits on Heat2 at the U10D input, upstream of both the buffer and the driver.
Requirement: In the ZXGD3009E6 typical low-side application circuit, an external gate-to-source resistor R2 runs from the MOSFET gate to ground/VEE. U4's output is a pair of emitter followers (NPN from VCC to SOURCE, PNP from SINK to VEE, bases driven from IN), so it only holds the gate low while U4 is powered and IN is held low.
Consequence: Whenever +5VCC is absent or ramping while VPWR is live (power-up, brown-out, or the 5 V rail failing), neither U4 nor U10D actively holds Q2's gate. The gate is then set only by leakage and by drain-to-gate coupling. Q2 can partly or fully enhance and switch on the heater on HTR2 with no command, which is a thermal-safety risk for a heater output.
Evidence:
Suggested repair: Add a resistor of roughly 10k–100k from NetQ2_4 (Q2 gate) to GND, placed close to Q2. Apply the same change to the other heater channels.
Component
Q3, pin `4`; ComponentU5, pins `4, 6`: Q3's gate has no pull-down to GND; add a gate-source resistor so HTR3 stays off when U5 is unpowered. (G005-F001)Observed: Q3's gate net NetQ3_4 connects only to Q3.4, R21.2 (100R to U5 SINK), R24.2 (10R to U5 SOURCE) and test point TP64. Nothing pulls the gate to GND or to Q3's source. Q3 is the low-side switch for heater HTR3, with its drain on HTR3 and its sources on GND.
Requirement: The ZXGD3009E6 typical low-side application circuit puts a gate-to-ground resistor R2 from the MOSFET gate to VEE/ground. The driver is a bipolar emitter follower and only holds the gate low while it is powered, and even then only to VOL (VEE + 0.5 V max).
Consequence: While +5VCC is absent, ramping, or faulted, U5 cannot hold Q3's gate low, so the gate's state is undefined while VPWR is present. Leakage or coupling could then partly turn on the heater switch. That would give uncontrolled heating or linear-mode dissipation in Q3, which is a safety concern for a heater output.
Evidence:
Suggested repair: Add a gate-to-source resistor (for example 10k–100k) from NetQ3_4 to GND, as close to Q3 as possible, matching R2 in the datasheet application circuit.
Component
Q4, pin `4`; ComponentR25, pin `2`; ComponentR27, pin `2`: Q4 gate has no gate-to-source pull-down; add a resistor from NetQ4_4 to GND. (G006-F001)Observed: The Q4 gate net (NetQ4_4) connects only to Q4 pin 4, R25 pin 2, R27 pin 2 and test point TP66. Nothing ties the gate to source/GND. NetQ4_4 does not appear on any other page. The only thing that can pull the gate down is U7's SINK output through R25 (100 Ω). Q4 switches HTBD-OUT, which goes to J3 pin 10, the heated-bed terminal. The bed's other side is VBED, which comes from its own input (VBED_IN through fuse block F1).
Requirement: The ZXGD3009E6 typical low-side drive circuit puts a gate-to-source resistor R2 from the MOSFET gate to ground/VEE. That way the gate has a defined off state that does not depend on the driver's bias.
Consequence: The gate can be left undefined when +5VCC is missing, ramping or browning out while VBED is live, or when U7 is unpowered or damaged. Whether U7's emitter follower clamps the gate then depends on the state of an unpowered U10C output, which nothing guarantees. Drain-gate coupling or leakage could then partly turn Q4 on and heat the bed with no command. A runaway heated bed is a safety hazard. The schematic does not show power sequencing, so this is a conditional risk.
Evidence:
Suggested repair: Add a gate-to-source resistor (for example 10 kΩ to 100 kΩ) from NetQ4_4 to GND close to Q4, as in the datasheet's R2.
Datasheets: R53, U4, Q1
Replace a datasheet: Q1, Q2, Q3, Q4, R25, R27, R52, R53, U4, U5
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[⚠️ Warning] Component
Q4, pins4, TAB; ComponentU7, pins1, 6: Q4 heated-bed MOSFET gets only about 4.2–4.6 V gate drive from U7 on 5 V, below its RDS(on) spec point.Observed: U7 runs from +5VCC and drives Q4's gate through R27 (10 Ω) from its SOURCE output. The U7 datasheet gives the high output as VCC−0.8 V min (VCC−0.4 V typ) even with VIN = VCC. Here IN comes from an AHCT125 output, which can only be at or below VCC. So Q4's gate settles at about 4.2–4.6 V. Q4 carries the heated-bed current, and the bed supply has a 30 A fuse block (F1) and a 24 V-class TVS (D78).
Requirement: The CSD18503Q5A's lowest guaranteed on-resistance point is VGS = 4.5 V (6.2 mΩ max at 22 A). Its 19 A ambient rating assumes about 40 °C/W on 1 in² of 2 oz copper. Below 4.5 V, RDS(on) is not guaranteed.
Consequence: At the worst-case drive level, Q4 runs below the gate voltage where its on-resistance is guaranteed. At heated-bed currents of about 15–20 A, even the 4.5 V maximum of 6.2 mΩ means 1.4–2.5 W. That would heat the junction by roughly 55–125 °C on copper like the datasheet's, and more if RDS(on) is higher at about 4.2 V. Q4 could overheat or need much more copper than planned. The size of the risk depends on the bed current and the PCB copper, which the schematic does not show.
Evidence:
Suggested repair: Supply U7 VCC from a higher rail (for example 10–12 V, within the 40 V VCC rating). Otherwise, confirm the bed current and Q4's thermal design against RDS(on) at about 4.2 V VGS.
Datasheets: U7, Q4
Replace a datasheet: Q4, U7
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[💡 Recommendation] Component
R6, pins1, 2; ComponentR7, pins1, 2; ComponentR8, pins1, 2: R6/R7/R8 dissipate about 77 % of their 1/16 W rating at 24 V; use a larger package or higher value.Observed: Each 10 kΩ 0402 resistor (RC0402FR-0710KP) sits between VPWR and an LED anode, with the LED cathode on the heater MOSFET drain. With the FET on, the resistor drops about VPWR − 2.1 V. VPWR has an SMAJ24A TVS (24 V standoff), which points to a 24 V rail. At 24 V that is about 2.19 mA and about 48 mW in each resistor, roughly 77 % of the 62.5 mW rating. At a supply set 10 % high (26.4 V) it is about 59 mW, roughly 94 % of the rating.
Requirement: RC0402 standard power is 0.0625 W at 70 °C ambient, derating linearly to 0 W at 155 °C. Good practice is to keep steady-state dissipation well below rating; this is not a mandated limit.
Consequence: The resistors run with little thermal margin in steady state whenever a heater is on. Board ambient above about 70 °C (possible near heater wiring) or a supply set at the top of its range pushes dissipation toward or past the derated limit. That speeds up resistor drift or ageing. It does not cause an immediate circuit failure.
Evidence:
Suggested repair: Use 0603 (1/10 W) resistors or the 1/8 W double-power RC0402 version, or raise the value to about 20 kΩ. At 24 V that still gives about 1.1 mA of LED current for indication.
Datasheet: R6
Replace a datasheet: R6, R7, R8
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[🚨 Error] Component
U15, pins4, 33: TVS D21 is reversed on VMOTE and shorts the M5–M8 driver supply; rotate D21.Observed: In channels M5–M8, U15 VSA (pin 4) and VS (pin 33) take power from design net VMOTE (fed from VMOT2). On Power.SchDoc, the SMAJ24A TVS D21 on that rail has its anode on VMOTE and its cathode on GND. The matching TVS on the other rail, D43, has its cathode on VMOTA and its anode on GND.
Requirement: U15 VS must be tied to the positive bridge supply, and the supply needs overvoltage protection. A unidirectional TVS clamp needs its cathode on the positive rail and its anode on GND.
Consequence: When VMOT2 is applied, D21 conducts forward and clamps VMOTE to about one diode drop above GND. This shorts the VMOT2 supply. Either the supply or fuse trips, or D21 overheats and fails. The four TMC5160 drivers on VMOTE (M5–M8) never see a valid VS/VSA (minimum 10 V recommended), so those motor channels cannot run. If D21 fails open, VMOTE is left with no transient clamp.
Evidence:
Suggested repair: Rotate D21 so pin K connects to VMOTE and pin A to GND, matching D43.
2 affected locations (one shared root cause)
C152, pin `1` (G002-F001)U15, pins `4, 33` (G001-F001)Component
C152, pin `1`: The VMOTE input TVS D21 is reversed, which shorts the M5–M8 bulk-capacitor rail; flip it to match D43. (G002-F001)Observed: In channels M5–M8, C152 pin 1 (plus C61, C121 and C122) sits on VMOTE. On Power.SchDoc the input TVS for that rail, D21 (SMAJ24A), has its anode (pin A) on VMOTE and its cathode (pin K) on GND. The matching TVS on the other motor rail, D43 (also SMAJ24A), is the other way round: cathode on VMOTA, anode on GND.
Requirement: A unidirectional TVS clamping a positive supply rail needs its cathode on the rail and its anode on GND. The design's own VMOTA clamp D43 follows this.
Consequence: As drawn, D21 forward-conducts from VMOTE to GND. That clamps the rail feeding the C152/C61/C121/C122 bank and the bridges for motors M5–M8 to about 1 V, or blows D21 or the upstream fuse/supply. Motors M5–M8 cannot get power.
Evidence:
Suggested repair: Flip D21 so pin K goes to VMOTE and pin A to GND, the same way as D43. Then check the footprint polarity mark.
Datasheets: U15, C152
Replace a datasheet: C152, U15
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[⚠️ Warning] Component
D19, pinsA, K; ComponentU15, pin23: ENCB through D19 has no pull-up because R17 is DNI, so U15 encoder channel B never reads high.Observed: ENCB (P2.6) reaches U15 pin 23 (ENCB_DCEN_CFG4) only through Schottky D19, with the cathode on ENCB and the anode on NetD19_A. The only pull-up on NetD19_A is R17, and R17 is marked DNI. When the encoder drives ENCB high, D19 is reverse-biased, so nothing drives pin 23 and its internal pull-down holds it low. The ENCA and ENCN channels get the same diode arrangement, but their pull-ups R18 and R16 (4.7k to 3.3VCC) are installed.
Requirement: A diode-OR level shifter only passes a high level when a pull-up on the anode side lifts the IC pin while the diode is reverse-biased. U15 pin 23 has an integrated pull-down, and its encoder B-channel function applies when SD_MODE=0. The page note says encoders only work with the TMC motion planner.
Consequence: With SD_MODE=0 and an encoder connected, U15 always reads encoder channel B as low. Quadrature decoding fails, so the encoder feature this header offers does not work on any of the eight channels as built.
Evidence:
Suggested repair: Fit R17 (4.7k to 3.3VCC, matching R16/R18) on builds that use the encoder. If the pull-up was left out on purpose so DCEN stays low (DcStep off) in STEP/DIR mode, document that trade-off, or route the pull-up through the mode selection.
Datasheets: U15, D19
Replace a datasheet: D19, U15
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[⚠️ Warning] Component
D46, pinsK, A; ComponentD47, pinsK, A; ComponentD48, pinsK, A; ComponentD49, pinsK, A; ComponentQ7, pins5, 7, 1, 3; ComponentQ10, pins5, 7, 1, 3: Phase TVS D46–D49 have a 24 V standoff, below the phase peak of VMOT plus the body-diode drop.Observed: Each motor phase (OAA, OAB, OBA, OBB) has an SMAJ24A from the phase to GND (K on the phase, A on GND). The high-side MOSFET drains of Q7 and Q10 sit on VMOT and their sources drive the phases, so the high-side body diode pulls each phase up to VMOT + VSD whenever current recirculates. The VMOT rail (VMOTA/VMOTE) is itself protected on Power.SchDoc by an SMAJ24A of the same type, with a 24 V standoff. That points to a 24 V-class rail, so the phase TVS standoff is set to the rail voltage, not to the higher voltage the phase actually reaches.
Requirement: For SMAJ24A: VRWM = 24 V, VBR = 26.7 V min at 1 mA, and IR ≤ 1 µA is guaranteed only at VRWM. For NVMFD5C478N: body-diode VSD is up to 1.2 V at 7.5 A. A TVS on a switching node should have a standoff at or above the node's highest normal voltage, VMOT(max) + VSD.
Consequence: At a 24 V nominal VMOT, every recirculation interval pushes the phases to about 25 V. That is above the 24 V VRWM, so leakage is no longer guaranteed. If VMOT reaches about 25.5 V (26.7 V VBR min minus 1.2 V VSD), within a normal tolerance band for a 24 V supply, the phase TVS can start conducting on every chopper cycle. Each TVS then dissipates repeatedly and heats up, and part of the phase current is diverted, which distorts the chopper current regulation. In all four phases of all eight channels, these TVS clamp before the rail TVS does.
Evidence:
Suggested repair: Choose a phase TVS whose VRWM is at or above VMOT(max) + about 1.2 V, for example an SMAJ28A/SMAJ30A class part. Keep its clamp voltage below the 40 V MOSFET VDSS at the expected surge current, or rely on the body diodes into a properly clamped VMOT and drop the phase-to-GND TVS.
Datasheets: D46, Q7
Replace a datasheet: D46, D47, D48, D49, Q10, Q7
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[💡 Recommendation] Component
J2, pins1, 2, 3, 4: Stray OBB/OBA/OAB/OAA ports near J2 are on unconnected duplicate nets; remove or connect them.Observed: Next to J2 the page has four ports named OBB, OBA, OAB and OAA, but they sit on separate nets OBB_DUPLICATE1, OBA_DUPLICATE1, OAB_DUPLICATE1 and OAA_DUPLICATE1. Each of those nets contains only its port. The real phase nets that reach J2 are page-local and have no sheet entries.
Requirement: A port should connect to the net it is named for and either continue to a sheet entry or be removed. A floating port that shares a name with a live net hides whether an off-sheet connection was intended.
Consequence: The motor outputs still reach J2 directly, so the drive works. The stray ports leave unconnected net stubs that trigger ERC warnings. They also make it unclear whether the phases were meant to leave the sheet, for example to a test or monitoring page.
Evidence:
Suggested repair: Remove the four stray ports, or wire them onto the OBB/OBA/OAB/OAA nets if an off-sheet connection was intended.
Datasheet: J2
Replace a datasheet: J2
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[⚠️ Warning] Component
RV5, pin1; ComponentRV6, pin1; ComponentRV7, pin1; ComponentP2, pins1, 4, 6, 8: Encoder varistors RV5–RV7 are rated 3.5V continuous but sit on lines from a 5V-powered encoder.Observed: RV5, RV6 and RV7 (AVRM0603C6R8NT101N) clamp ENCA, ENCB and ENCN to GND on the header side of the BAT54 isolation diodes. The same header supplies the encoder from +5VCC (P2.1). The D12/D19/D20 diodes with 3.3V pull-ups form a level shifter, which shows the design expects encoder high levels above 3.3V. A 5V push-pull or 5V-pulled-up encoder would hold these nets at about 5V.
Requirement: The AVRM0603C6R8NT101N maximum allowable circuit voltage is 3.5V DC (leakage 50uA max). Its varistor voltage at 1mA can be as low as 4.76V. The datasheet says not to apply a circuit voltage above the maximum allowable circuit voltage.
Consequence: A 5V encoder high level runs the varistors above their rated continuous voltage and near their minimum breakdown. They can draw milliamp-level current, which loads the encoder outputs, lowers the high level, and stresses or degrades the varistors over time.
Evidence:
Suggested repair: Use a protection device rated for at least 5.5V continuous operation on ENCA/ENCB/ENCN, or confirm and document that only 3.3V-output encoders are supported.
Datasheet: RV5
Replace a datasheet: RV5, RV6, RV7
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[⚠️ Warning] Component
Q11, pins1, 2, 3, 4, 5, 7; ComponentQ10, pins1, 2, 3, 4, 5, 7: Q10/Q11 symbol's MOSFET pin grouping conflicts with the datasheet pinout; check before release to rule out bridge shoot-through.Observed: The NVMFD5C478NT1G symbol used for Q10 and Q11 names pin 1 S2, pin 2 G2, pin 3 S1, pin 4 G1, pin 5 D1 and pin 7 D2. That puts the source on pin 1 in the same MOSFET as the drain on pin 7, and the source on pin 3 with the drain on pin 5. In Q11 (low side), pin 5 goes to OAB and is gated from LA2 through R167. Pin 7 goes to OAA and is gated from LA1 through R166. Both sources go to the R169 shunt. In Q10 (high side), HA1 drives pin 2 with the source on pin 1 = OAA, and HA2 drives pin 4 with the source on pin 3 = OAB.
Requirement: Each source/gate/drain pin group in the symbol must belong to one physical MOSFET in the package. The datasheet puts S1 on the corner marked pin 1, puts D1 (MOSFET 1) on pins 5 and 6 with drain flag 1, and puts D2 on pins 7 and 8 with drain flag 2. The two MOSFETs are electrically isolated from each other.
Consequence: The supplied datasheet pairs the pin-1 source with the drain on pins 5/6, but the symbol pairs it with the drain on pin 7. If the datasheet mapping is right, Q11's gate pins would switch the low-side MOSFET of the opposite half-bridge. LA1 would then turn on the OAB low side while HA1 or HA2 has the matching high side on, which shorts VMOT through the bridge (shoot-through) as soon as the motor runs. On Q10 the high-side source and gate pairs could also be swapped. The supplied datasheet text alone cannot settle which mapping is correct.
Evidence:
Suggested repair: Check the symbol and footprint pad numbering against the package drawing and pin connection diagram on page 1 of the onsemi NVMFD5C478N datasheet. Make sure each S/G pin pair sits in the same MOSFET as its own D pins and drain flag, then correct the symbol if needed.
Datasheet: Q11
Replace a datasheet: Q10, Q11
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[⚠️ Warning] Component
R108, pins1, 2; ComponentU15, pins26, 27: DIAG line through R108 has no external pull-up for TMC5160 open-drain DIAG outputs; add one of 47k or less to 3.3VCC.Observed: R108 (1k) joins U15 DIAG0_SWN (pin 26, net NetR108_1) to DIAG1_SWP (pin 27). Pin 27 then goes to the DIAG port, which becomes DIAGn in each channel. Across the whole design, DIAG1 and DIAG5 connect only to R108, U15 pin 27 and one microcontroller GPIO (U11A pin 63 for M1, pin 131 for M5), plus ports and sheet entries. No pull-up resistor sits on either DIAG net or on NetR108_1. The only defined bias on the DIAG node comes from U15's internal ~166k pull-down on DIAG1 and its internal pull-up/pull-down on DIAG0.
Requirement: The TMC5160 datasheet says that in open-drain mode, DIAG0_SWN and DIAG1_SWP need an external pull-up of 47k or less.
Consequence: If either DIAG output is left in open-drain mode, nothing pulls the combined DIAG line high except possibly an MCU internal pull-up. The internal pull-down on DIAG1 then tends to hold the line low, so the MCU may see diagnostics as permanently asserted, or see a slow, noise-prone edge. Stall and error reporting for all eight axes would then be unreliable. Push-pull firmware configuration avoids the problem, but nothing in hardware enforces that.
Evidence:
Suggested repair: Add a pull-up of 47k or less (for example 10k) from the DIAG net to 3.3VCC (VCC_IO) on this sheet. Otherwise, document that firmware must set both DIAG outputs to push-pull and that the MCU pull-up is not relied on.
2 affected locations (one shared root cause)
U15, pins `26, 27`; ComponentR108, pins `1, 2` (G001-F002)R108, pins `1, 2`; ComponentU15, pins `26, 27` (G007-F001)Component
U15, pins `26, 27`; ComponentR108, pins `1, 2`: U15 DIAG0/DIAG1 open-drain outputs have no external pull-up of 47k or less; add one to 3.3VCC. (G001-F002)Observed: DIAG1_SWP (pin 27) connects straight to the DIAG port. DIAG0_SWN (pin 26) joins the same net through R108 (1k). Design net DIAG1 contains only the SAM3X pin U11A.63, R108 and U15.27. No external pull-up resistor to VCC_IO exists anywhere in the design.
Requirement: In open-drain mode, DIAG0 and DIAG1 need an external pull-up of 47k or less.
Consequence: If the DIAG outputs stay in open-drain mode, the MCU input has no defined high level unless an internal MCU pull-up is enabled. With no pull-up the line floats, and diagnostic, stall or interrupt signalling is unreliable. A weak internal pull-up may also be above the 47k limit.
Evidence:
Suggested repair: Add a pull-up of 47k or less from DIAG to 3.3VCC in each channel. Alternatively, document that firmware sets the DIAG outputs to push-pull in GCONF before using them.
Datasheets: U15, R108
Replace a datasheet: R108, U15
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[⚠️ Warning] Component
R162, pins1, 2: R162's name says 0.1R 1206 but its value and MPN are 0.05R 2512; fix the name.Observed: R162's component name is '0.1R 1% 1206'. Its VALUE (0.05R), EE_SPEC (0.05R 1% 2512), MPN (CSRN2512FK50L0) and part description (50 mOhm 2W 2512) all say 0.05 Ω in a 2512 package. The matching phase-A shunt R169 is named '0.05R 1% 2512', so its name agrees with its other fields.
Requirement: The part identity fields must agree on resistance and package. The TMC5160 sets coil current from the sense resistor value, both phases should use matched shunts, and sense resistors should be low-inductance 1210/2512 parts. CSRN2512FK50L0 is a 0.050 Ω, 2 W, 2512 part.
Consequence: If the 0.1 Ω / 1206 name is used, at procurement or when the footprint is chosen, phase B gets a different shunt value than phase A (R169). Phase B current would then be about half of phase A, giving an asymmetric, distorted microstep current. A 1206 footprint would also not fit the specified 2512 part, or would force a lower-power part.
Evidence:
Suggested repair: Rename R162 to '0.05R 1% 2512' to match its MPN and R169, and confirm the assigned footprint is 2512.
Datasheet: R162
Replace a datasheet: R162
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[⚠️ Warning] Component
C93, pins1, 2: C93 manufacturer part number field holds a Digi-Key number and the tolerance fields conflict; correct the BOM data.Observed: C93's MANUFACTURER # and PART fields both contain '490-10756-2-ND', which is a Digi-Key distributor number, not a Murata manufacturer part number. MANUFACTURER2# is also a distributor number ('587-3248-2-ND'). The tolerance fields disagree: TOLERANCE and the description say 10%, but PART DESCRIPTION says ±20%.
Requirement: BOM metadata should give one clear manufacturer part number and consistent ratings, so the part bought matches the intended specification.
Consequence: With no actual MPN, the procured part and its tolerance are ambiguous, and an alternate source or CM substitution cannot be checked against a defined voltage or dielectric spec. The electrical impact on a bulk cap is small, but the BOM entry has no defined part behind it.
Evidence:
Suggested repair: Put the real Murata MPN in MANUFACTURER #, and the Taiyo Yuden MPN in the alternate field if it is a second source. Make TOLERANCE and the description match that MPN.
3 affected locations (one repeated pattern)
C14, pins `1, 2` (G011-F003)C16, pins `1, 2` (G012-F004)C93, pins `1, 2` (G010-F002)Component
C14, pins `1, 2`: C14 MPN field holds a Digi-Key number and its tolerance attributes conflict; fix the BOM metadata. (G011-F003)Observed: C14's MANUFACTURER # and PART fields both hold '490-10756-2-ND', which is a Digi-Key distributor number, not a manufacturer part number. MANUFACTURER2# also holds a distributor number, '587-3248-2-ND'. The TOLERANCE attribute and the description say 10%, but PART DESCRIPTION says ±20%. The supplied datasheet is a general Murata MLCC catalog, with no resolved part number.
Requirement: BOM metadata should name one manufacturer part, with tolerance and description attributes that agree, so that procurement and assembly fit the intended part.
Consequence: With no manufacturer part number and a tolerance conflict, the purchased part depends on how the distributor number is resolved. Substitutions are uncontrolled. For a bulk input capacitor the electrical impact is small, so this is a documentation and procurement issue.
Evidence:
Suggested repair: Enter the actual Murata MPN in the MANUFACTURER # and PART fields, and make the tolerance attribute and descriptions consistent.
Component
C16, pins `1, 2`: C16 MPN field holds a Digi-Key number and its tolerance fields conflict; enter the real Murata MPN. (G012-F004)Observed: C16's MANUFACTURER # and PART fields hold '490-10756-2-ND', which is a Digi-Key distributor number, not a Murata manufacturer part number. MANUFACTURER2# also holds a distributor number ('587-3248-2-ND'). The TOLERANCE field and component description say 10 %, while PART DESCRIPTION says ±20 %.
Requirement: BOM metadata should name one unambiguous manufacturer part, and its tolerance should agree across all fields.
Consequence: Purchasing or the contract manufacturer cannot tell which Murata part (and which tolerance grade) is intended. This can lead to substitution errors or BOM rejection. The electrical impact on this bulk capacitor is minor.
Evidence:
Suggested repair: Put the real Murata MPN in MANUFACTURER # and PART, keep distributor numbers in the DISTRIBUTOR # fields, and make the tolerance fields match.
Datasheet: C14
Replace a datasheet: C14, C16, C93
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[🚨 Error] Component
C71, pin2; ComponentU1, pin2: U1 VIN has only C71 10 nF plus small caps on VPWR; add a ≥10 µF 50 V ceramic at VIN.Observed: U1's VIN (pin 2) sits on VPWR, and the only ceramic from VPWR to GND near U1 is C71 (10 nF, X7R, 0402). Across the whole design, VPWR's only capacitors to GND are C71 (10 nF), C35 (1 nF) and C199/C202/C203 (100 nF each), about 0.31 µF in total. VPWR has no 10 µF-class ceramic and no bulk capacitor anywhere. The C8/C9/C10 capacitors on Mosfets.SchDoc connect VPWR to the HTR1/2/3 heater outputs, not to GND.
Requirement: The TPS54531 needs an input decoupling capacitor, typically a 10 µF X5R or X7R ceramic rated above the maximum input voltage, placed as close as possible to VIN and the catch-diode anode. The 0.01 µF part is only an extra high-frequency filter. Bulk capacitance (typically 100 µF electrolytic) is also recommended when the source is more than a few inches away.
Consequence: The buck's pulsed input current has no low-impedance local source. This gives volts of input ripple and ringing with the supply-cable inductance. At 24 V input that can push VIN/PH past the 30 V absolute maximum, upset the EN/UVLO divider on the same node, and make the 5 V rail unstable or reset under load.
Evidence:
Suggested repair: Add at least 10 µF of X5R/X7R ceramic rated 50 V (for example 2 × 4.7 µF or 1 × 10 µF in 1206/1210) from VPWR to GND right at U1 VIN and the D2 anode. Keep C71 as the high-frequency bypass. Consider a bulk electrolytic on VPWR near F2/J3.
2 affected locations (one shared root cause)
C71, pin `2`; ComponentU1, pin `2` (G003-F001)U1, pins `2, 7` (G001-F001)Component
U1, pins `2, 7`: U1 VIN has only about 0.31 µF of ceramic input capacitance; add the required 10 µF ceramic plus bulk. (G001-F001)Observed: U1 VIN (pin 2) is on VPWR. The only capacitors from VPWR to GND anywhere in the design are C199, C202 and C203 (100 nF each, 0603), C71 (10 nF) and C35 (1 nF), about 0.31 µF in total. The design-wide VPWR net has no 10 µF ceramic and no bulk electrolytic. C8, C9 and C10 on Mosfets.SchDoc connect VPWR to the HTR1, HTR2 and HTR3 nets, not to GND.
Requirement: The TPS54531 datasheet says an input decoupling capacitor is required, typically a 10 µF X5R or X7R ceramic rated above the maximum input voltage, placed close to VIN and the catch-diode anode. It also recommends extra bulk capacitance (typically 100 µF electrolytic) when the source is more than a few inches away. Input ripple is ΔVIN = IOUT × 0.25 / (CBULK × fSW).
Consequence: With about 0.31 µF of input capacitance, the ripple equation gives roughly 5–7 V of input ripple at 4–5 A load and 570 kHz. Switching current loops through the barrier-strip input wiring (J3, F2), causing poor regulation, EMI, and a high risk of hot-plug ringing on VPWR. Ringing on a 24 V rail can exceed U1's 30 V VIN/PH absolute maximum.
Evidence:
Suggested repair: Add at least 10 µF (for example 2 × 4.7 µF or 1 × 10 µF, 50 V X7R/X5R) from VPWR to GND right at U1 VIN and the D2 anode. Also add a bulk electrolytic (about 100 µF, 35–50 V) on VPWR near the input.
Datasheets: C71, U1
Replace a datasheet: C71, U1
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[⚠️ Warning] Component
C210, pins1, 2; ComponentD78, pinK: C210 is rated 35 V but the VBED TVS D78 clamps up to 38.9 V; use a 50 V capacitor.Observed: C210 (Nichicon UWT1V101MCL1GS, 100 µF, 35 V aluminium electrolytic) sits across VBED and GND. D78 (SMAJ24A) is the VBED transient clamp, and its clamping voltage reaches 38.9 V (10/1000 µs) or 50.6 V (8/20 µs).
Requirement: The capacitor's applied voltage, including transients the rail TVS allows through, should stay within its rated voltage. C210 is rated 35 V.
Consequence: Surges clamped by D78 can push C210 above its 35 V rating. That can degrade the electrolytic or make it fail. With a 24 V steady state, C210 also runs at about 69 % of rating with little extra margin.
Evidence:
Suggested repair: Use a 50 V rated bulk capacitor on VBED, or make sure the TVS clamp stays below 35 V.
Datasheets: D78, C210
Replace a datasheet: C210, D78
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[🚨 Error] Component
D21, pinsA, K: D21 TVS is reversed on VMOTE and shorts the motor supply; put the cathode on VMOTE.Observed: D21 (SMAJ24A, unidirectional) is drawn with its anode on VMOTE and its cathode on GND. The other three rail TVS diodes on this page are drawn the other way: D22, D43 and D78 each have the cathode on the rail (VPWR, VMOTA, VBED) and the anode on GND. VMOTE comes straight from barrier terminal J3.1. No fuse sits in that path, and the lookup shows no other clamp diode on VMOTE.
Requirement: Per the SMAJ24A datasheet, the cathode goes to the protected line, which must be positive relative to the anode, and the anode usually goes to ground or the return line. In the reverse direction the part forward-conducts, with VF up to 3.5 V at 35 A.
Consequence: When a positive 12-24 V supply is connected to J3.1, D21 is forward-biased straight across the VMOTE input, and there is no fuse to limit the current. The supply is shorted through the diode. D21 cannot survive this (1 W steady-state, 40 A for 8.3 ms only), so it overheats and fails. Either it fails open, leaving the motors 5-8 rail with no transient protection, or it fails short, holding the rail at about 0 V while the supply runs into its current limit. Motors 5-8 cannot be powered as drawn.
Evidence:
Suggested repair: Flip D21 so that K is on VMOTE and A is on GND, matching D22, D43 and D78. Check that the footprint's cathode-band marking matches the new orientation.
2 affected locations (one shared root cause)
D21, pins `A, K` (G011-F001)J3, pin `1`; ComponentD21, pins `A, K` (G009-F001)Component
J3, pin `1`; ComponentD21, pins `A, K`: TVS D21 on the J3 pin 1 VMOTE input is reversed and shorts the motor supply; flip it. (G009-F001)Observed: J3 pin 1 brings in VMOTE, which feeds motors 5-8. On VMOTE, the SMAJ24A TVS D21 is wired backwards: anode on VMOTE, cathode on GND. The three other SMAJ24A clamps on this page (D43 on VMOTA, D22 on VPWR, D78 on VBED) are all wired cathode to rail, anode to GND. VMOTE has no fuse between J3 pin 1 and its loads. The whole-design pin list for VMOTE shows only capacitors, TMC5160 VS/VSA, MOSFET drains, the divider R26, D21 and a test point.
Requirement: A unidirectional TVS on a positive rail must have its cathode on the rail and its anode on ground, so that it stays reverse-biased at the 12-24 V operating input and only conducts above breakdown.
Consequence: When positive voltage is applied to J3 pin 1, D21 is forward-biased straight across the motor supply. VMOTE clamps to about one diode drop, so motors 5-8 never get power. Because nothing in this path is fused, the PSU current flows through D21 and J3 until the diode or the PSU fails, which risks burning the board.
Evidence:
Suggested repair: Swap D21's orientation so K connects to VMOTE and A to GND, matching D43.
Datasheets: D21, J3
Replace a datasheet: D21, J3
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[⚠️ Warning] Component
D43, pinsK, A: D43 SMAJ24A standoff equals the 24 V motor supply; choose a higher-VRWM TVS.Observed: D43 (SMAJ24A) clamps VMOTA to GND, with K on VMOTA and A on GND. The page note says the inputs are compatible with 12-24VDC, so a 24 V supply sits right at D43's 24 V working peak reverse voltage. That leaves no headroom for supply tolerance or a supply adjusted slightly high.
Requirement: A TVS's working peak reverse voltage (VRWM) should be at or above the highest continuous voltage on the rail it protects. For the SMAJ24A, VRWM is 24 V, and the 1 uA leakage limit is only guaranteed at 24 V. Breakdown voltage (VBR) starts at a minimum of 26.7 V at 1 mA.
Consequence: A typical 24 V PSU set to 24-26.4 V, or one with normal tolerance, pushes D43 above its rated standoff voltage. Leakage then rises well beyond 1 uA. Near the 26.7 V minimum breakdown, the TVS can conduct continuously and overheat, and its rated surge capability no longer holds.
Evidence:
Suggested repair: Move to a TVS with VRWM above the highest expected supply, for example an SMAJ28A or SMAJ30A. Confirm that the new clamping voltage stays below the 50 V rating of the rail capacitors and the motor driver's limits.
3 affected locations (one repeated pattern)
D21, pins `A, K` (G011-F002)D22, pin `K`; ComponentD78, pin `K` (G012-F002)D43, pins `K, A` (G010-F001)Component
D21, pins `A, K`: D21 SMAJ24A standoff equals the 24 V maximum input, leaving no margin. (G011-F002)Observed: D21 is an SMAJ24A, with a 24 V working peak reverse voltage, protecting the VMOTE input. A page note says the inputs are compatible with 12-24 VDC. At the top of that range the rail sits right at the TVS standoff voltage, with no margin for supply tolerance or set-point adjustment.
Requirement: SMAJ24A VRWM is 24 V maximum, and the 1.0 uA leakage limit is specified at 24 V. VBR is 26.7 V minimum to 29.5 V maximum at 1 mA. For low leakage and no conduction in steady state, normal operating voltage must stay at or below VRWM.
Consequence: A nominal 24 V supply running a few percent high (for example 25-26 V) is above VRWM and close to the minimum breakdown voltage. D21 then leaks more and heats. If the supply goes past 26.7 V, D21 conducts continuously and will overheat. This is a margin risk that depends on the actual supply tolerance, and it applies once D21's orientation is fixed.
Evidence:
Suggested repair: If 24 V supplies will be used, choose a higher-standoff TVS (for example SMAJ26A-SMAJ28A). Its clamp level must stay below the 50 V rating of the VMOTE capacitors and the motor driver's VS limit. Otherwise, document a lower maximum input voltage.
Component
D22, pin `K`; ComponentD78, pin `K`: D22 and D78 SMAJ24A standoff equals the 24 V maximum input, leaving no tolerance margin. (G012-F002)Observed: D22 (on VPWR) and D78 (on VBED) are both SMAJ24A, with a 24 V working peak reverse voltage. The page note says the inputs are compatible with 12–24 VDC, so at the top of that range the rail sits exactly at VRWM.
Requirement: The TVS standoff (VRWM) should be above the highest steady-state rail voltage, including supply tolerance and adjustment range. VBR for SMAJ24A can be as low as 26.7 V.
Consequence: A 24 V supply has zero standoff headroom. If the supply is set or regulated slightly high (for example a 24 V PSU adjusted to 26–27 V), the TVS diodes leak more, can conduct and heat continuously, and may age or fail. On VPWR, a shorted D22 would blow F2.
Evidence:
Suggested repair: If 24 V supplies with positive tolerance must be supported, use a higher-standoff TVS (for example a 26–28 V VRWM part) and check the clamp against downstream ratings. Otherwise, document a maximum input below 24 V.
Datasheet: D21
Replace a datasheet: D21, D22, D43, D78
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[⚠️ Warning] Component
D22, pinsK, A; ComponentU1, pin2; ComponentU20, pin3: D22 clamps VPWR well above the 30 V absolute maximum of U1 and U20, so it cannot protect them.Observed: D22 (SMAJ24A) is the only TVS on VPWR, wired K to VPWR and A to GND after fuse F2. VPWR also feeds U1 VIN (pin 2) and U20 IN (pin 3) directly. D22 does not start to break down until 26.7–29.5 V at 1 mA, and it clamps at up to 38.9 V (10/1000 µs, 10.3 A) or 50.6 V (8/20 µs).
Requirement: A rail TVS must hold transients below the absolute maximum of the parts it protects. U1 VIN is rated 30 V absolute maximum (28 V recommended), and U20 (L78L05) DC input is rated 30 V absolute maximum.
Consequence: During a surge or load-dump on the 24 V input, D22 lets VPWR rise well above 30 V before it clamps. U1 and U20 can then be overstressed or destroyed, even though a TVS is fitted.
Evidence:
Suggested repair: Pick a TVS whose clamping voltage at the expected surge current stays below 30 V. One option is a lower-standoff part, accepting that it reduces the allowed input range. Another is to add series impedance or a pre-regulator or clamp ahead of U1 and U20.
3 affected locations (one shared root cause)
U1, pins `2, 8`; ComponentD22, pins `K, A` (G001-F002)D22, pins `K, A`; ComponentU1, pin `2`; ComponentU20, pin `3` (G012-F001)U20, pin `3`; ComponentD22, pin `K` (G005-F001)Component
U1, pins `2, 8`; ComponentD22, pins `K, A`: D22 clamps VPWR at up to 38.9 V, above U1's 30 V VIN/PH absolute maximum. (G001-F002)Observed: VPWR, which feeds U1 VIN directly (no series element after fuse F2), is clamped only by D22, an SMAJ24A. Its breakdown voltage is 26.7–29.5 V and its maximum clamping voltage is 38.9 V at 10.3 A (10/1000 µs) and 50.6 V at 51.5 A (8/20 µs).
Requirement: U1 VIN and PH absolute maximum is 30 V, and the recommended VIN range is 3.5–28 V.
Consequence: A surge large enough to make D22 conduct significantly lets VPWR rise above U1's 30 V absolute maximum before the clamp holds. U1 can be damaged even though the TVS survives. Exposure depends on what transients the 12–24 VDC supply wiring sees.
Evidence:
Suggested repair: Use a protection scheme whose clamp voltage at the expected surge current stays at or below 30 V while standing off the maximum 24 V input. Alternatively, add series impedance or a pre-regulator in front of U1, or choose a regulator with a higher VIN rating.
Component
U20, pin `3`; ComponentD22, pin `K`: U20's 30 V input rating sits below D22's 38.9 V clamp on VPWR, so surges can overstress the 78L05. (G005-F001)Observed: U20 (L78L05ABUTR) pin 3 IN sits directly on VPWR. The only surge clamp on VPWR is D22 (SMAJ24A, cathode on VPWR). Its maximum clamping voltage is 38.9 V at 10.3 A (10/1000 µs) and 50.6 V at 51.5 A (8/20 µs), and its breakdown voltage can be as high as 29.5 V. There is no series element or secondary clamp between VPWR and U20 IN.
Requirement: The L78L05 (VO = 3.3 to 9 V group) has an absolute-maximum DC input voltage of 30 V.
Consequence: At a 24 V nominal input, any surge that D22 handles near its rated current lets VPWR rise to 38.9 to 50.6 V. That is 9 to 21 V above U20's 30 V absolute maximum, so U20 can be overstressed. If U20 fails, 5V0_AUX is lost, and with it the INA381 current-limit supply and the comparator reference dividers. Steady-state 24 V operation is inside the rating.
Evidence:
Suggested repair: Pick a lower-clamp TVS on VPWR that is still compatible with the 24 V working input, or add input protection local to U20, for example a series resistor plus a Zener/TVS at U20 IN. Another option is a regulator with an input rating of at least 40 V.
Datasheets: D22, U20, U1
Replace a datasheet: D22, U1, U20
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[💡 Recommendation] Component
F1, pins1, 2: F1 library name 3557-2 does not match its MPN 3557-20; align the metadata.Observed: F1's library name is '3557-2' and its symbol and description say 'FUSE PTH ATO'. Its MANUFACTURER #, PART, distributor number and Comment all say 3557-20. F2 uses the same library name but carries MPN 3557-2.
Requirement: A component's library identity and its ordering part number should name the same part, so the BOM, assembly and lookups resolve without ambiguity.
Consequence: The two holders appear mechanically interchangeable, so this is mainly a documentation and procurement issue. Tools or buyers keyed on the library name may order the wrong colour variant, and the colour coding meant to separate the VBED holder from the VPWR holder would be lost.
Evidence:
Suggested repair: Rename F1's library entry or name attribute to 3557-20, or give it a distinct symbol, so the name matches the MPN.
Datasheet: F1
Replace a datasheet: F1
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[💡 Recommendation] Component
F1, pins1, 2; ComponentF2, pins1, 2: F1/F2 fuse ratings are not specified; document fuse values within J3's 20 A rating.Observed: F1 and F2 are fuse holders only, with VALUE '-NA-'. No fuse element or fuse rating is specified anywhere in the design; a search for 'fuse' finds only these two holders. Both holders are rated 30 A. The J3 positions that carry VBED_IN, VBED and VPWR_IN are rated 20 A each (UL Class C).
Requirement: The protective element and its rating must be defined so that the fuse protects the downstream wiring and connectors. Here that means at most 20 A per J3 position.
Consequence: With no fuse rating on record, a user may fit a fuse up to the holder's 30 A rating. That would let more current through J3 pins 5/7/9 than their 20 A rating, and give no protection to the VPWR logic and heater loads below it.
Evidence:
Suggested repair: Add the intended fuse ratings (for example ATO xx A) as BOM line items or a schematic note, choosing values no higher than J3's 20 A per-position rating.
Datasheets: F1, F2
Replace a datasheet: F1, F2
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[💡 Recommendation] Component
J3, pins1, 3: Motor supply inputs on J3 pins 1 and 3 are unfused; consider adding fuses.Observed: J3 pins 1 (VMOTE) and 3 (VMOTA) connect directly to the motor-driver rails. The rails are protected only by TVS diodes and have no fuse. VPWR and VBED, by contrast, go through F2 and F1.
Requirement: No datasheet requirement mandates a fuse here. This is a robustness practice for high-energy supply inputs feeding 470 uF bulk capacitance and MOSFET bridges.
Consequence: A shorted driver bridge or a failed TVS on a motor rail is limited only by the PSU, so it can burn the board and the J3 terminals.
Evidence:
Suggested repair: Consider adding fuse holders or PTCs on VMOTA and VMOTE like those on the other inputs.
Datasheet: J3
Replace a datasheet: J3
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[⚠️ Warning] Component
R103, pins1, 2; ComponentP1, pins1, 3: R103 0603 jumper (1 A rated) feeds all VFAN fans plus the P1 expansion; confirm current or upsize.Observed: R103 is a CR0603 0 Ω jumper and the only path from VPWR to VFAN. VFAN feeds four 3-pin fan connectors on Fans.SchDoc (J22, J29, J30, J31), their LED indicators, and two paralleled contacts of the P1 expansion header (pins 1 and 3).
Requirement: The CR0603 zero-ohm jumper is rated for 1 A continuous, with a 2.5 A maximum overload.
Consequence: If the four fans and whatever is attached to P1 draw more than 1 A in total, R103 runs above its rating. It will heat up and can go open, which cuts power to every fan, including part-cooling and hotend fans. The actual fan load is not documented, so this risk is conditional.
Evidence:
Suggested repair: Document the VFAN current budget. If it can exceed about 1 A, replace R103 with a jumper or fuse rated for that current, such as a 1206/2512 zero-ohm part, a wire link, or a resettable fuse.
Datasheet: R103
Upload/replace a datasheet: P1, R103
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[⚠️ Warning] Component
R11, pins1, 2; ComponentR2, pins1, 2; ComponentU1, pin3: R11/R2 EN divider puts U1 UVLO near 11 V with ~30 mV hysteresis, marginal for 12 V input.Observed: R11 (10 kΩ, VPWR to EN) and R2 (1.4 kΩ, EN to GND) set U1's EN start and stop thresholds. Ratio 11.4/1.4 = 8.14 gives about 10.2 V typical. At the 1.35 V maximum enable threshold it is about 11.0 V, and about 11.2 V with 1% resistor tolerance. The hysteresis comes only from the extra 3 µA EN current into the 1.23 kΩ Thevenin impedance: about 3.7 mV at EN, or about 30 mV at VPWR.
Requirement: The page note says the board's inputs work with 12–24 VDC. U1's EN threshold is 1.25 V typical and 1.35 V maximum, with a 1 µA pull-up below threshold and 4 µA above. The datasheet sizes UVLO hysteresis through the upper resistor (Ren1 = ΔV/3 µA), so a divider this stiff gives almost no hysteresis.
Consequence: With a 12 V supply, worst-case parts leave under 1 V between nominal input and the 5 V converter's turn-off point, and the stop/start hysteresis is only about 30–40 mV. Supply tolerance, fuse and cable drop under heater load, or a slow-ramping PSU can make U1 stop or chatter on and off near the threshold. That repeatedly drops +5VCC and the 3.3 V rail derived from it.
Evidence:
Suggested repair: If 12 V operation must be robust, lower the start threshold (for example around 9 V) and add real hysteresis. Raise the R11/R2 impedance per the datasheet UVLO equations, while keeping the pull-up strong enough for the U6/U21/U19 open-drain pull-downs.
2 affected locations (one shared root cause)
R11, pins `1, 2`; ComponentR2, pins `1, 2`; ComponentU1, pin `3` (G003-F002)U1, pin `3` (G001-F003)Component
U1, pin `3`: U1 EN divider R11/R2 sets UVLO at about 10.2–11 V with about 30 mV hysteresis, marginal for a 12 V input. (G001-F003)Observed: U1 EN (NetR2_2) is set by the divider R11 = 10 kΩ (VPWR to EN) and R2 = 1.4 kΩ (EN to GND). The start threshold is about 1.25 V × 11.4 / 1.4 ≈ 10.2 V typical and about 11.0 V with the 1.35 V maximum EN threshold. Hysteresis is about 3 µA × 10 kΩ ≈ 30 mV. The page states the inputs are compatible with 12–24 VDC.
Requirement: The EN enable threshold is 1.25 V typical and 1.35 V maximum, with 1 µA pull-up plus 3 µA hysteresis current. The datasheet recommends at least 500 mV of UVLO hysteresis (unless VIN is greater than VOUT + 2 V). For 12 V operation, the UVLO stop point must sit below the minimum expected input voltage under load.
Consequence: On a 12 V supply, the 5 V rail starts and stops between about 10.2 V and 11 V, with only about 30 mV of hysteresis. That leaves about 1–1.8 V of margin below 12 V nominal. A supply at its low tolerance, or sag from cable drop and heater/motor current on the shared input, can shut the 5 V and 3.3 V logic rails down or make them chatter.
Evidence:
Suggested repair: If 12 V operation is intended, lower the UVLO threshold (for example, increase R2 or reduce R11 so it starts around 8–9 V) and raise R11 for more hysteresis. Or confirm that the threshold was chosen deliberately to sit near 10 V.
Datasheets: R2, R11, U1
Replace a datasheet: R11, R2, U1
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[⚠️ Warning] Component
R157, pins1, 2: R157 is marked 1% but its MPN RC0402JR-07130KL is a 5% part; settle the tolerance.Observed: R157's symbol name is '130k 1% 0402' and its TOLERANCE attribute is 1%. Its ordering data (MPN RC0402JR-07130KL, Digi-Key YAG3273CT-ND) and its PART DESCRIPTION both give a ±5% part. R157 is the top resistor of the U21 IN- reference divider (R157 130k from 5V0_AUX to NetR157_1, R158 100k 1% to GND). Nominal reference: 5 V × 100k/230k = 2.174 V. With R157 at ±5% and R158 at ±1%, the reference can fall anywhere from about 2.10 V to 2.25 V (about ±3.4%). The VMOTA trip point, about 3.4 × Vref (R154/R155 = 24k/10k), therefore moves from about 7.4 V nominal to somewhere between about 7.15 V and 7.65 V.
Requirement: A part's documented tolerance must match the part that will be bought, especially when it sets a comparator threshold. In the Yageo code, J means ±5%.
Consequence: The BOM is ambiguous. Buying by MPN gets a 5% resistor where the symbol says 1%, which roughly triples the reference error. The VMOTA enable/disable threshold for the +5V buck gets about ±0.25 V of extra spread on top of the 5V0_AUX regulator tolerance. The trip stays well below the 12 V minimum input, so the risk is mainly accuracy and documentation, not loss of function.
Evidence:
Suggested repair: If 1% is intended, change the MPN to RC0402FR-07130KL. If 5% is acceptable, correct the name and TOLERANCE fields to 5%. The same mismatch exists on the identical R57.
2 affected locations (one repeated pattern)
R57, pins `1, 2` (G007-F001)R157, pins `1, 2` (G006-F001)Component
R57, pins `1, 2`: R57 is labelled 1% but its MPN is a 5% part; align the tolerance metadata. (G007-F001)Observed: R57 has conflicting tolerance metadata. Its name is '130k 1% 0402' and its TOLERANCE attribute is 1%, but its description says 5%, the PART DESCRIPTION says ±5%, and the ordered MPN is RC0402JR-07130KL, where the J code means ±5%. R57 is the top resistor of the U6 IN- reference divider (R57 130k from 5V0_AUX, R58 100k to GND).
Requirement: The BOM should name a single tolerance for each placed part. The datasheet for the ordered MPN RC0402JR-07130KL gives ±5% (tolerance code J), not the 1% the name and TOLERANCE field claim.
Consequence: Purchasing or a substitute choice could go either way. With the 5% part, the nominal 2.17 V reference moves by about ±2.8% (about 2.11 V to 2.24 V), so the VMOTE trip point moves from about 7.4 V to roughly 7.2–7.6 V. That is still far below the 12–24 V operating range, so this is a documentation and procurement inconsistency rather than a functional failure.
Evidence:
Suggested repair: Make the metadata agree. Either change the MPN to a 1% part (for example the RC0402FR-07130KL family) or change the name and TOLERANCE field to 5%.
Datasheet: R57
Replace a datasheet: R157, R57
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[⚠️ Warning] Component
R119, pins1, 2; ComponentR115, pins1, 2; ComponentU19, pin5: U19 trips at about 2.4 A, not the noted ~4 A; change R119 to about 10 kΩ.Observed: CMPREF (U19 pin 5, NetR115_1) comes from R115 = 15 kΩ to 5V0_AUX and R119 = 4.7 kΩ to GND, which sets CMPREF at 5.0 V × 4.7/19.7 ≈ 1.19 V. U19 is the INA381A2 (gain 50 V/V) sensing across R148 (10 mΩ), and VOUT is tied straight to CMPIN. The trip current is 1.19 V / (50 × 0.01 Ω) ≈ 2.4 A. Using the L78L05AB output range of 4.75–5.25 V, CMPREF is about 1.13–1.25 V, so the trip point is about 2.27–2.50 A before amplifier offset and gain error. The page note asks for about 4 A.
Requirement: The INA381 datasheet gives CMPREF = (I_alert × R_shunt + VOS) × Gain. For the noted ~4 A limit with a 10 mΩ shunt and gain 50, CMPREF needs to be about 2.0 V.
Consequence: U19 is in latch mode (RESET held high through R102) and its ALERT drives the TPS54531 EN low. Any +5VCC load above about 2.4 A, which is well under the documented 4 A budget and the converter's 5 A rating, shuts the 5 V buck off. It stays off until power is cycled. This removes +5VCC from the Microcontroller, Mosfets, Motors, Fans and USB pages.
Evidence:
Suggested repair: Raise CMPREF to about 2.0 V. For example, change R119 to 10 kΩ, which gives 5 V × 10/25 = 2.0 V, about 4.0 A. Alternatively, rescale R115 and R119 for the current limit actually intended.
Datasheets: R115, R119, U19
Replace a datasheet: R115, R119, U19
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[⚠️ Warning] Component
U6, pins1, 2, 3, 4, 5: U6 metadata says quad 14-SOIC from TI, but AP331AWG-7 is a single SOT25 Diodes part; fix it.Observed: U6's description is 'IC QUAD DIFF COMPARATOR 14 -SOIC' and its MANUFACTURER field is 'TEXAS INSTRUMENTS'. The ordered MPN, AP331AWG-7, is a single comparator in SOT25 from Diodes Inc. The 5-pin symbol matches the SOT25 pinout.
Requirement: The package, manufacturer and description fields must agree with the ordered MPN. The datasheet places AP331AWG-7 in SOT25 (3000 per reel) with a single comparator pinout: 1 IN-, 2 GND, 3 IN+, 4 Output, 5 Vcc.
Consequence: The description points to a quad SOIC-14 part and to the wrong manufacturer. If the footprint or a purchasing substitution follows the description, the part will not fit or will not match the 5-pin pinout. The manufacturer field also points sourcing to a vendor that does not make AP331A.
Evidence:
Suggested repair: Change the description to a single comparator in SOT25 and the manufacturer to Diodes Incorporated. Confirm the assigned footprint is SOT25, not SOT25R or SOIC-14.
2 affected locations (one repeated pattern)
U6, pins `1, 2, 3, 4, 5` (G007-F002)U21, pins `1, 2, 3, 4, 5` (G006-F002)Component
U21, pins `1, 2, 3, 4, 5`: U21 metadata says TI quad 14-SOIC but the AP331AWG-7 is a Diodes single SOT25; fix the description. (G006-F002)Observed: U21's description is 'IC QUAD DIFF COMPARATOR 14 -SOIC' and its MANUFACTURER is 'TEXAS INSTRUMENTS'. The MPN AP331AWG-7 and distributor part AP331AWGDITR-ND are a Diodes Inc. single comparator in a 5-pin SOT25 package. The 5-pin symbol's pinout (1 IN-, 2 GND, 3 IN+, 4 OUT, 5 VCC) matches the SOT25 pinout.
Requirement: Component description, manufacturer and package metadata should agree with the MPN so that procurement and footprint checks resolve to one device.
Consequence: The MPN and distributor number are unambiguous, but the description and manufacturer fields point to a different device and package (a 14-pin quad from another vendor). That invites a wrong substitution or a wrong footprint during BOM scrubbing.
Evidence:
Suggested repair: Change the description to a single comparator in SOT-25 and the manufacturer to Diodes Incorporated, and confirm the footprint is SOT-25. U6 has the same metadata.
Datasheet: U6
Replace a datasheet: U21, U6
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[🚨 Error] Component
U9, pins14, 16, 12, 13; ComponentC29, pin1; ComponentC33, pin1: U9 VDD2/VBUS2 are on unsourced net +3.3VCC while PIN/SPD use 3.3VCC; merge them onto 3.3VCC.Observed: U9 VDD2 (pin 14) and VBUS2 (pin 16) connect only to net '+3.3VCC'. The only other things on that net are the two +3.3VCC ports on this page, decoupling caps C29/C33 and pull-up R51. No regulator, connector or sheet entry feeds it. U9 PIN (pin 12) and SPD (pin 13) connect to a different net, '3.3VCC', which runs to 8 other pages, including Power.SchDoc.
Requirement: ADuM3160 side 2 needs power: either 3.3 V on both VBUS2 and VDD2, or 4.5–5.5 V on VBUS2. The datasheet says to tie PIN and SPD to VDD2. The absolute maximum on VPIN and VSPD is VDD2 + 0.5 V.
Consequence: Side 2 of U9 has no supply, so the upstream pull-up stays disconnected and the board never enumerates on USB. Meanwhile PIN and SPD sit at 3.3 V while VDD2 is near 0 V, far above the VDD2 + 0.5 V absolute maximum. That risks back-powering side 2 through the input pins and damaging the part. C29/C33 decouple a dead net. The R51 FWUP pull-up on the same net is also unpowered.
Evidence:
Suggested repair: Join the +3.3VCC ports to the sourced 3.3VCC rail, for example by renaming both +3.3VCC ports to 3.3VCC. That way VDD2, VBUS2, PIN, SPD, C29/C33 and R51 all share one powered rail.
3 affected locations (one shared root cause)
U9, pins `14, 16, 12, 13`; ComponentC29, pin `1`; ComponentC33, pin `1` (G002-F001)R51, pin `2`; ComponentU9, pins `14, 16` (G005-F001)U11B, pin `53`; ComponentR51, pin `2`; ComponentU9, pins `14, 16` (G004-F001)Component
R51, pin `2`; ComponentU9, pins `14, 16`: R51 FWUP pull-up goes to +3.3VCC, a net with no supply; connect it to the 3.3VCC rail. (G005-F001)Observed: R51 pin 2, the 100K FWUP pull-up, connects to net +3.3VCC. In the whole design that net reaches only C29.1, C33.1, R51.2, U9.14 (VDD2), U9.16 (VBUS2) and two +3.3VCC ports on this same page. No regulator or other supply drives it. The real 3.3 V rail is the separately named net 3.3VCC. It is cross-page and feeds U9.12/13 and, through FB27, VDDANA.
Requirement: A pull-up has to go to a rail that is actually supplied. The SAM3X datasheet treats FWUP as a force-wake-up input (a low level wakes the part from backup) and lists its backup current with FWUP = VDDBU. That means FWUP has to sit at a defined high level when unused. The isolator's side-2 supply pins also need a powered rail.
Consequence: FWUP is pulled only toward an unpowered net that is loaded by U9's unpowered side-2 supply pins. It therefore has no defined high level, and the backup/wake-up behaviour is unpredictable. The same split rail leaves U9 VDD2/VBUS2 unpowered, so the isolated USB path cannot work.
Evidence:
Suggested repair: Rename or connect the +3.3VCC ports and net to the supplied 3.3VCC rail, or put a proper source on +3.3VCC. Make sure R51 goes to the rail that powers VDDBU.
Component
U11B, pin `53`; ComponentR51, pin `2`; ComponentU9, pins `14, 16`: +3.3VCC has no source, so the FWUP pull-up R51 and U9 VDD2/VBUS2 are unpowered; join it to 3.3VCC. (G004-F001)Observed: FWUP (U11B pin 53) is pulled up by R51 (100k) to the net +3.3VCC. Across the whole design, +3.3VCC connects only to C29.1, C33.1, R51.2, U9.14 (VDD2), U9.16 (VBUS2) and two ports, all on this page. Nothing drives it. The working 3.3 V rail on this page is a different net, 3.3VCC (no '+'). It connects to U9.12/13 and is the rail that supplies U11C VDDBU (pin 52) and VDDIN.
Requirement: FWUP is a VDDBU-domain wake-up input, and a low level on FWUP is a wake-up source, so it has to be held at a defined high level from a powered rail. Every supply pin on the U9 downstream side also needs a source, because the U11B USB D+/D- lines (DHSDP/DHSDM/DFSDP/DFSDM) reach the host only through U9.
Consequence: No rail drives +3.3VCC, so it has no defined voltage. U9's downstream side gets no supply, which leaves the U11B USB device interface with no path to the host. FWUP has no valid pull-up and can float or sit low through the unpowered U9 rail, so it can assert a forced wake-up or hold an undefined level. That stops backup/shutdown behaviour from working.
Evidence:
Suggested repair: Join +3.3VCC to the supplied 3.3VCC rail, which is the VDDBU domain. For example, rename the +3.3VCC ports to 3.3VCC, or add a net tie.
Datasheets: R51, U9, U11B, C29
Replace a datasheet: C29, C33, R51, U11B, U9
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[⚠️ Warning] Component
D26, pinsC, A: D26's 39 V TVS across USB_GND/GND caps the 2.5 kV USB isolation barrier at about 35 V.Observed: D26 (RSB39VTE-17) connects USB_GND directly to GND, and so sits across the isolation barrier formed by U9 (ADuM3160, EE_SPEC 2500V ISO) and U18 (TLP293, 3.75 kV). The other cross-barrier parts are absent or optional: C27, C50 and R61 are DNI, and JP2 is an optional bridge. That leaves D26 as the installed element that sets how much voltage the barrier can hold off.
Requirement: The RSB39V breaks down at VZ 35.1 to 42.9 V and is specified for lines working below about 30 V (IR 0.1 uA max at 30 V). Its dissipation limit is Pd 200 mW. A part across a 2500 Vrms isolation barrier has to tolerate the intended common-mode working voltage. The barrier is only as good as its lowest-rated bridging element.
Consequence: The USB isolation only holds off about 30 to 35 V, not the 2.5 kV that the isolator spec suggests. A sustained ground offset or fault above roughly 35 V between the PC ground and the printer ground sends current through a 200 mW SOD-323 diode. The likely result is a short-circuit failure that bonds the two grounds permanently. Polarity itself does not matter, because the device is bidirectional.
Evidence:
Suggested repair: If the isolation is only meant to break ground loops, document the roughly 30 V working limit. If real high-voltage isolation is intended, replace D26 with a part rated for the barrier, for example a safety-rated Y-cap or a high-voltage RC bleed, or remove it.
Datasheet: D26
Replace a datasheet: D26
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[⚠️ Warning] Component
FB29, pin1; ComponentJP1, pins1, 2: JP1 lets FB29's VBUS path short to the on-board +5VCC supply with no backfeed protection.Observed: FB29 carries host VBUS from J8.1 (via NetC43_2) onto VUSB. JP1 is a solder jumper ('Bridge to power from USB') that, once bridged, ties VUSB straight to +5VCC. There is no diode, load switch or ideal-diode element in between. +5VCC is not only a USB rail: it has its own on-board source on Power.SchDoc, which reaches +5VCC through R148 (0.01R) from an L1/C3/C4/C5 node, plus 5 V loads on the Fans, Mosfets, Microcontroller and Motors pages.
Requirement: A USB device must not drive voltage back onto the host's VBUS. Inrush and load on VBUS also have to stay inside what the host port can supply. With the bridge closed, nothing on the drawn path stops the board's own 5 V supply and VBUS from feeding each other.
Consequence: If JP1 is bridged and the board's own 5 V supply is also running, it pushes current back into the PC's VBUS. VBUS and the regulator output then fight each other. Even with the board's supply off, the whole board's 5 V capacitance and load hang on the host port through FB29. This can trip or overload the host port. It also bypasses the galvanic isolation that U9 and U18 are meant to provide, since JP2 would be bridged in the same configuration.
Evidence:
Suggested repair: Put a Schottky/ideal-diode OR-ing element or a load switch between VUSB and +5VCC instead of a bare solder bridge. Otherwise, add a clear assembly note that JP1/JP2 must only be bridged when the board's own 5 V source is unpowered or not fitted.
2 affected locations (one shared root cause)
FB29, pin `1`; ComponentJP1, pins `1, 2` (G001-F001)JP1, pins `1, 2`; ComponentU18, pins `1, 2` (G006-F001)Component
JP1, pins `1, 2`; ComponentU18, pins `1, 2`: JP1 ties host VBUS straight to the on-board +5VCC rail; add a reverse-blocking diode. (G006-F001)Observed: JP1 is a bare solder jumper between VUSB (host VBUS after FB29, also the U18 LED supply through R152) and +5VCC. +5VCC is the board's own regulated rail: on Power.SchDoc it comes from an inductor/shunt output stage (L1, R148) and feeds the U8 3.3 V LDO. Nothing blocks current in either direction. When JP1 is bridged, the board's +5VCC drives the host VBUS pin of J8 whenever the board is powered. VUSB also stops being an independent host-presence signal, because it is held at +5VCC. With JP2 bridged as well (USB_GND = GND), U18's LED stays on whenever +5VCC exists, so VBUS_UC reads 'attached' even with no cable plugged in.
Requirement: A USB device must not source current into the host's VBUS (no back-drive). The 'Bridge to power from USB' option should only let current flow from the host into the board. The VBUS-detect opto chain (R152/U18/Q8/R150) only works if VUSB comes from the host alone.
Consequence: If JP1 is fitted and the board is powered from its main supply with a USB cable attached, the board's 5 V rail and the host's VBUS are shorted together. Current can flow back into the host port or fight the host's VBUS switch, and the board rail can be loaded by the host. Firmware also loses real VBUS detection, so USB attach/detach events become wrong.
Evidence:
Suggested repair: Replace JP1 with, or add in series, a Schottky diode (or ideal-diode/power-mux) from VUSB to +5VCC, so the host can power the board but the board cannot drive VBUS. That also keeps VUSB independent for the U18 detect path. Alternatively, document that JP1 is only for USB-only powered builds where the main supply is absent.
Datasheets: FB29, U18
Upload/replace a datasheet: FB29, JP1, U18
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[⚠️ Warning] Component
R48, pins1, 2; ComponentR42, pins1, 2; ComponentR47, pins1, 2; ComponentR45, pins1, 2: R42/R48 are 24 Ω where the SAM3X needs 39 Ω on DFSDM/DFSDP, and they stack with R45/R47.Observed: R48 (DFSDP pin 42 to UMCU_P) and R42 (DFSDM pin 43 to UMCU_N) are both 24 Ω RC0402FR-0724RL parts. The UMCU_P/UMCU_N nodes then pass through a second 24 Ω resistor (R47/R45) to the ADuM3160 DD+/DD- pins. The MCU full-speed driver therefore sees 24 Ω on its own pin and 48 Ω of total series resistance to U9, against the 39 Ω the MCU datasheet calls for. DHSDP/DHSDM connect straight to the UMCU nodes.
Requirement: The SAM3X datasheet (U11B) places a 39 Ω series resistor between DFSDP/DFSDM and the USB D+/D- lines and connects DHSDP/DHSDM directly. The ADuM3160 datasheet (U9) separately asks for 24 Ω ±1% on each DD+/DD- line, for U9's own driver.
Consequence: The source impedance of the MCU full-speed transmitter does not match what the MCU datasheet specifies. Its pin resistor is 24 Ω instead of 39 Ω, and the stacked R48+R47 path puts 48 Ω between DFSDP and U9 instead of a single 39 Ω termination. Reflections and edge shape on the MCU-to-isolator link can then fall outside the conditions the full-speed transceiver was characterised for, which erodes signal-integrity margin. A short point-to-point trace will probably still work, so this is a margin risk rather than a demonstrated failure.
Evidence:
Suggested repair: Make the MCU-side stack match the datasheet. One option is to change R42/R48 to 39 Ω. Another is to size R42/R48 and R45/R47 together so the DFSDP/DFSDM path gives the intended 39 Ω, while U9's DD side keeps its required 24 Ω placed close to U9.
2 affected locations (one shared root cause)
R48, pins `1, 2`; ComponentR42, pins `1, 2`; ComponentR47, pins `1, 2`; ComponentR45, pins `1, 2` (G003-F001)U11B, pins `42, 43`; ComponentR48, pins `1, 2`; ComponentR42, pins `1, 2` (G004-F002)Component
U11B, pins `42, 43`; ComponentR48, pins `1, 2`; ComponentR42, pins `1, 2`: DFSDP/DFSDM series resistors R48/R42 are 24 Ω where the SAM3X datasheet specifies 39 Ω. (G004-F002)Observed: DFSDP (pin 42) and DFSDM (pin 43) each reach UMCU_P/UMCU_N through a 24 Ω resistor (R48, R42). DHSDP and DHSDM tie to the same UMCU_P/N nodes. From there, a second pair of 24 Ω resistors (R47, R45) runs to U9 UD+2/UD-2. That puts 48 Ω in series on the full-speed path and 24 Ω on the HS pins.
Requirement: The U11B datasheet places 39 Ω series resistors between DFSDP/DFSDM and USB D+/D-, and connects DHSDP/DHSDM directly to D+/D-.
Consequence: The full-speed driver termination does not match the manufacturer's reference. Edge rate and reflection behaviour on the MCU-to-isolator segment are no longer the validated ones, which reduces signal-integrity margin on the USB full-speed link.
Evidence:
Suggested repair: Use the datasheet 39 Ω values on DFSDP/DFSDM, or document how the 24 Ω + 24 Ω chain was chosen together with the U9 isolator's input requirements.
Datasheets: R48, U11B
Replace a datasheet: R42, R45, R47, R48, U11B
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[💡 Recommendation] Component
U9, pin1: U9 symbol name says ADuM4160 but MPN is ADuM3160; align the metadata.Observed: U9's symbol name is 'ADuM4160' but its MANUFACTURER #, PART and Comment fields all say ADUM3160BRWZ-RL / ADuM3160. Its description reads 'USB Opto Isolator', although the part is a transformer-coupled (iCoupler) isolator.
Requirement: The symbol name, description and orderable part number should all identify the same device. The ADuM3160 is rated 2500 Vrms.
Consequence: The name conflict leaves it unclear which isolation grade belongs in the BOM. It could lead to the wrong part being substituted, or to clearance/creepage being sized for the wrong isolation rating.
Evidence:
Suggested repair: Rename the symbol and description to match ADuM3160BRWZ-RL, or update the MPN if the higher-isolation part is what was intended.
Datasheet: U9
Replace a datasheet: U9
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