diff --git a/.allspice/issue_template/new_component_request.yml b/.allspice/issue_template/new_component_request.yml new file mode 100644 index 0000000..a628168 --- /dev/null +++ b/.allspice/issue_template/new_component_request.yml @@ -0,0 +1,101 @@ +name: New component request +about: Submit to add/update a component/symbol/footprint to the library +title: "[New component request]: " +body: + - type: markdown + attributes: + value: Submit to add/update a component/symbol/footprint to the library + + # Justification + - type: input + id: why + attributes: + label: Justification + description: Describe why an existing component can't be used + placeholder: "No existing LVDS clock fanout buffers" + value: "" + validations: + required: true + + # Component type + - type: dropdown + id: component-type + attributes: + label: Component type + multiple: false + options: + - Passive + - Power supply + - Microcontrollers + - Analog + - Digital + - Other + + # Where used + - type: input + id: where-used + attributes: + label: Where used + description: List what assemblies / pcbs will use this component + placeholder: ASMXXXX + value: "" + + # QTY estimate + - type: input + id: qty-estimate + attributes: + label: Estimated annual quantity + description: Estimated annual quantity + placeholder: "10,000" + value: "" + + # Footprint + - type: input + id: footprint + attributes: + label: Footprint + description: Package family, LxWxH mm, pitch + placeholder: "SOIC-16 5x4.5x1.2mm, 0.65mm " + value: "" + validations: + required: true + + # Part numbers + - type: textarea + id: part-numbers + attributes: + label: Part numbers + description: List mfg and internal part numbers, add at least one distributor part number + placeholder: "List mfg and internal part numbers,\nadd at least one distributor part number" + value: "" + render: "true" + validations: + required: true + + # Checklist + - type: checkboxes + id: checklist + attributes: + label: Checklist (fill out later) + options: + - label: Checked library for existing parts + - label: Price check + - label: QTY check + - label: Lead time check + - label: Distributor part number + - label: Datasheet review + - label: Symbol review + - label: Footprint review + - label: Component check (symbol+footprint review) + - label: Package check + - label: Dimension check + - label: Automotive grade + - label: Space grade + - label: FMEA analysis + + + - type: markdown + attributes: + value: | + ## Attach files + (datasheet, design notes, firmware) \ No newline at end of file diff --git a/.allspice/issue_template/update_component_request.yml b/.allspice/issue_template/update_component_request.yml new file mode 100644 index 0000000..61f598d --- /dev/null +++ b/.allspice/issue_template/update_component_request.yml @@ -0,0 +1,67 @@ +name: Update component request +about: Request a component to be updated/deleted +title: "[Update component request]: " +body: + - type: markdown + attributes: + value: Request a component to be updated/deleted + + # Justification + - type: input + id: what + attributes: + label: Requested changes + description: Describe requested changes + placeholder: "Add thermal pad to footprint" + value: "" + validations: + required: true + + # Where used + - type: input + id: where-used + attributes: + label: Affected components + description: List what components are affected + placeholder: "All quad flat pack footprints with ground pads" + value: "" + + # Part numbers + - type: textarea + id: description + attributes: + label: Description + description: Describe the changes you'd like to make + placeholder: "Update all footprints of quad packages that have footprints to include the thermal ground pad" + value: "" + render: "true" + validations: + required: true + + # Checklist + - type: checkboxes + id: checklist + attributes: + label: Checklist + options: + - label: Checked library for existing parts + - label: Price check + - label: QTY check + - label: Lead time check + - label: Distributor part number + - label: Datasheet review + - label: Symbol review + - label: Footprint review + - label: Component check (symbol+footprint review) + - label: Package check + - label: Dimension check + - label: Automotive grade + - label: Space grade + - label: FMEA analysis + + + - type: markdown + attributes: + value: | + ## Attach files + (datasheet, design notes, firmware) \ No newline at end of file diff --git a/.allspice/pull_request_template.md b/.allspice/pull_request_template.md new file mode 100644 index 0000000..7459587 --- /dev/null +++ b/.allspice/pull_request_template.md @@ -0,0 +1,141 @@ +--- + +name: "AllSpice component review template" +about: "Optional description" + +--- + +*This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!* + +## Resolved Issues + +... + +## Description + +... + +## Design Review Checklist +### Process +- [ ] Commits in correct branch +- [ ] File names follow standard +- [ ] Update project README page +### System +- [ ] Power + - [ ] Supply rated for necessary country specifications + - [ ] Estimated total worst-case power supply draw +- [ ] Connectors + - [ ] Sufficient Current and Voltage rating + - [ ] Mating connectors have matching pinout + - [ ] Same contact material specified for mating connectors +- [ ] Testing + - [ ] Test procedure written +- [ ] Environmental + - [ ] Specified min/max operating temperature + - [ ] Specified min/max storage temperature + - [ ] Specified min/max humidity +- [ ] ROHS compliance requirement review +### Components +- [ ] Components meet environmental specifications +- [ ] All components have quantity, reference designator and description +- [ ] Suggested and alternate manufacturers listed +- [ ] Price and stock checked for each component +- [ ] Component derating + - [ ] Voltage + - [ ] Current + - [ ] Power at worst-case operating temperature + - [ ] Temperature at worst-case power +### Schematics +- [ ] Microcontrollers / ICs + - [ ] Check the data sheet errata and apnotes for weird IC behaviors +- [ ] Busses + - [ ] UART/USART TX->RX and RX<-TX + - [ ] I2C SDA and SCL pins correct(https://www.ti.com/lit/an/slva689/slva689.pdf) +- [ ] Analog + - [ ] Sufficient power rails for analog circuits + - [ ] Amplifiers checked for stability + - [ ] Consider signal rate-of-rise and fall for noise radiation +- [ ] General + - [ ] Sufficient bulk capacitance calculated + - [ ] Polarized components checked + - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage + - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF + - [ ] Check pin numbers of all custom-generated parts + - [ ] Check reverse base-emitter current/voltage on bipolar transistors + - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) + - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default +### PCB +- [ ] Manufacturing + - [ ] PCB manufacturing requirements noted on `fab` layer + - [ ] Plating specified + - [ ] Plating material + - [ ] Plating thickness + - [ ] Layer stack-up specified + - [ ] Minimum trace/space specified + - [ ] Minimum hole size specified + - [ ] Controlled impedance specified + - [ ] Blind or buried vias specified +- [ ] Footprints + - [ ] Pin 1 marked in a consistent manner + - [ ] Component polarity marked + - [ ] Diodes, LEDs + - [ ] Electrolytic, tantalum capacitors + - [ ] Keyed components like connectors + - [ ] Footprint dimensions cross-checked with datasheet recommendation + - [ ] Sufficient thermal pads on high-power components or nets +- [ ] Clearance + - [ ] Keep-out areas honored + - [ ] Around mounting holes + - [ ] For programming tools + - [ ] For assembly tools (wrenches, screwdrivers etc.) + - [ ] For connectors + - [ ] Trace-to-trace clearance based upon voltage rating + - [ ] Component size based upon voltage rating +- [ ] Mechanical + - [ ] CAD file uploaded + - [ ] Clearance above connectors + - [ ] Clearance below through-hole components + - [ ] Mounting holes electrically isolated if necessary + - [ ] Mounting holes have via stitching + - [ ] Hole diameters leave margin for plating +- [ ] Electrical + - [ ] ERC passes + - [ ] Isolation barriers are large enough +- [ ] Signal integrity + - [ ] Gaps in ground planes checked and minimized + - [ ] High-speed signals avoid gaps in ground planes + - [ ] Stubs minimized for high-speed signals + - [ ] Differential pair spacing based upon impedance matching + - [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda) + - [ ] Option for a shielding can over sensitive circuitry e.g. RF? +- [ ] Copper pour + - [ ] All planes have been poured + - [ ] Planes and pours checked for high-impedance paths + - [ ] No pour between adjacent pins on ICs +- [ ] Traces + - [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more) + - [ ] Trace widths sufficient for the current draw and max heating + - [ ] No connections between adjacent pins on ICs + - [ ] Vias for internal power traces sufficiently large + - [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces +- [ ] Thermal + - [ ] Temperature sensitive components placed away from hot components + - [ ] Thermal vias in thermal pads +- [ ] Silk screen + - [ ] Notes and documentation + - [ ] Updated revision number + - [ ] Updated date + - [ ] No silk screen over pads / vias + - [ ] Text is readable from at most two directions + - [ ] Silk screen size / font will legible after printing + - [ ] Connector pin-outs labeled + - [ ] Fuse size and type marked on PCB + - [ ] Functional groups marked + - [ ] Functionality labeled + - [ ] Test points + - [ ] LEDs + - [ ] Buttons + - [ ] Connectors/terminals + - [ ] Jumpers/fuses + + \ No newline at end of file diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..853e5c5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,53 @@ +# ---> AltiumDesigner +# For PCBs designed using Altium Designer +# Website: https://www.altium.com/altium-designer/ + +# Directories containing cache data +History +__Previews + +# Directories containing logs and generated outputs +Project\ Logs* +Project\ Outputs* + +# Misc files generated by altium +debug.log +Status\ Report.txt +*.PcbDoc.htm +*.SchDocPreview +*.PcbDocPreview + +# Lock files sometimes left behind +.~lock.* + +# ---> KiCad +# For PCBs designed using KiCad: https://www.kicad.org/ +# Format documentation: https://kicad.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.kicad_sch-bak +*-backups +*.kicad_prl +*.sch-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv + diff --git a/Antenna.SchLib b/Antenna.SchLib new file mode 100644 index 0000000..2db0b3a Binary files /dev/null and b/Antenna.SchLib differ diff --git a/ICs.SCHLIB b/ICs.SCHLIB new file mode 100644 index 0000000..ebb050f Binary files /dev/null and b/ICs.SCHLIB differ diff --git a/LEDs.SCHLIB b/LEDs.SCHLIB new file mode 100644 index 0000000..5438a3b Binary files /dev/null and b/LEDs.SCHLIB differ diff --git a/WS-ENTV.PcbLib b/WS-ENTV.PcbLib new file mode 100644 index 0000000..5407307 Binary files /dev/null and b/WS-ENTV.PcbLib differ diff --git a/cap.SCHLIB b/cap.SCHLIB new file mode 100644 index 0000000..7a0435e Binary files /dev/null and b/cap.SCHLIB differ diff --git a/connectors.SCHLIB b/connectors.SCHLIB new file mode 100644 index 0000000..345419b Binary files /dev/null and b/connectors.SCHLIB differ diff --git a/footprints.PcbLib b/footprints.PcbLib new file mode 100644 index 0000000..e7e5c5f Binary files /dev/null and b/footprints.PcbLib differ diff --git a/images/book-shelf.png b/images/book-shelf.png new file mode 100644 index 0000000..e65a2b1 Binary files /dev/null and b/images/book-shelf.png differ diff --git a/images/library-management-overview.png b/images/library-management-overview.png new file mode 100644 index 0000000..27d0cd6 Binary files /dev/null and b/images/library-management-overview.png differ diff --git a/images/pico-pinout.svg b/images/pico-pinout.svg new file mode 100644 index 0000000..959593f --- /dev/null +++ b/images/pico-pinout.svg @@ -0,0 +1,10747 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + diff --git a/images/pico_family.jpg b/images/pico_family.jpg new file mode 100644 index 0000000..f0646f5 Binary files /dev/null and b/images/pico_family.jpg differ diff --git a/images/read-book.png b/images/read-book.png new file mode 100644 index 0000000..04d5276 Binary files /dev/null and b/images/read-book.png differ diff --git a/misc.SCHLIB b/misc.SCHLIB new file mode 100644 index 0000000..d067c13 Binary files /dev/null and b/misc.SCHLIB differ diff --git a/readme.md b/readme.md new file mode 100644 index 0000000..97e9ffd --- /dev/null +++ b/readme.md @@ -0,0 +1,111 @@ +# Altium Library Demo + +This repository demonstrates the ability to view `.schlib` symbol files and `.pcblib` PCB footprint files using AllSpice. + + + +## Overview + +AllSpice provides a platform for hardware engineers to collaborate on electronics design, much like GitHub but tailored for hardware projects. This repository showcases how to handle schematic library (`.schlib`) and PCB library (`.pcblib`) files within the AllSpice ecosystem. + +## Features + +- View `.schlib` symbol files directly within the AllSpice interface. +- Examine `.pcblib` PCB layout files without needing external tools. +- Track changes and collaborate on hardware designs using AllSpice's version control capabilities. +- Visual diff of symbol and layout changes +- Attribute Diffs +- AllSpice Actions can be used to verify your components + +## How does library management work? +Every component library starts with a set of project files. + + + +## Create a component library repository +Create a location for your designs. This can be as sophisticated as a git repo, or a shared network folder. + +## Discuss the location and logistics with your team before implementing. The most important thing is that everyone will reference the centralized library instead of creating their own. + +## Separate symbol and component files by function +Separate components into separate files by function. Each one of these component types have different common attributes and are easier to maintain and fix. + +- Resistors +- Capacitors +- Connectors +- Power regulation +- Level translators +- High speed digital +- Radio frequency + +Sometimes it’s easier to understand an example. Check out one of these library examples to see how we separate components. + +[Celestial Altium library](https://hub.allspice.io/AllSpice-Demos/Altium-Celestial-library) + +[Wurth Altium library](https://hub.allspice.io/AllSpice-Demos/Wurth-component-library-Altium) + +## Pair symbol libraries with footprint libraries +Ensure that symbol libraries and footprint libraries have synchronized names and known folder locations. If the libraries get separated, they have a tendency to diverge. + +For example: + +`/symbols/Resistors.schlib` + +`/footprints/Resistors.pcblib` + +## Create a new component process +The best way to keep a library correct is to have a new component process. This can be as formal as your team needs. This prevents new and untested components from being added to the library and that all components in the library are tested and approved. + +- Email +- Spreadsheet +- Issue Tracker (Jira, MS Teams) +- Git repo workflow + +## Update component attributes +Whether you keep your attributes in a symbol library or in a separate intlib/dblib, updating the component attributes will help ensure your BOM and purchasing are correct. + +You may want to start with an empty library file and merge the library file as you add and review the attributes. + +Important fields are Manufacturer, Manufacturer Part Number, Distributor, Alternate Parts, Related footprint. + +## Remove duplicates +Duplicate component shown and highlighted in red within an library. +One you have a library, it is important to find and delete duplicate components. If you have more than one copy of the information, it’s easy to only fix one copy, with the other copies remaining for reuse. + +## Fix component errors +Component errors shown in library. +Engineers often fix errors as they see them. It’s important to make sure the fixes get into the library as they’re made. + +It’s also important to set aside time each product release to prune the library of incorrect parts. + +In the example above, an engineer modified a 10K resistor partnumber with a 5K reference designator. The wrong part would be ordered if this component were used. + +## Dedicated resources to library management +Not every team needs a full-time parts librarian. Each designer should know how to properly maintain a library even if you have a dedicated librarian. Discuss and agree with the team how much time to budget and add to the schedule to ensure the components are correct. + +## Any improvement is an improvement +Even small changes to habits can bring about a huge improvement to the quality and reuse of components. It’s better to do several small improvements than postpone all improvements. + + + + +## Symbol Best Practices + +1. Consistency: Ensure that all symbols in your library follow a consistent style and naming convention. This makes it easier to understand and use the symbols in your designs. +2. Clarity: Design symbols that are easy to read and understand. Use clear and unambiguous labels for pins and components. +3. Pin Configuration: Arrange pins logically, grouping similar functions together (e.g., power pins, ground pins, I/O pins). This makes schematics easier to read and reduces the chance of errors. +4. Standardization: Adhere to industry standards (e.g., IEEE, IEC) when creating symbols. This ensures compatibility and reduces learning curves for new team members. +5. Documentation: Include relevant information within the symbol, such as pin names, numbers, and functions. This aids in the design and review process. + +## Footprint Best Practices + +1. Accuracy: Ensure that the footprint dimensions are accurate and match the component datasheet specifications. Incorrect footprints can lead to manufacturing issues and component placement problems. +2. Pad Sizes and Shapes: Use appropriate pad sizes and shapes for the type of component and soldering method. Ensure sufficient pad spacing to avoid solder bridges. +3. Clearances: Maintain adequate clearances between pads, traces, and other components to meet electrical and manufacturing requirements. Follow the design rules provided by your PCB manufacturer. +4. Silkscreen: Include clear and legible silkscreen markings for component outlines, reference designators, and orientation indicators. This aids in manual assembly and inspection. + 5. Thermal Relief: For components that require heat dissipation, design appropriate thermal reliefs and copper pours. This ensures reliable solder joints and component performance. + 6. Test Points: Include test points for critical signals to facilitate testing and debugging. Ensure they are easily accessible and clearly marked. + +By following these best practices, you can create reliable, manufacturable, and easy-to-use symbols and footprints that enhance the quality and efficiency of your PCB designs. + +Feel free to adjust the blurb to better fit your specific needs or style. \ No newline at end of file diff --git a/resistors.SCHLIB b/resistors.SCHLIB new file mode 100644 index 0000000..cc1e2d2 Binary files /dev/null and b/resistors.SCHLIB differ diff --git a/smd_solder_jumper.schlib b/smd_solder_jumper.schlib new file mode 100644 index 0000000..2bfb388 Binary files /dev/null and b/smd_solder_jumper.schlib differ