Daniel Lindmark 63a5cf2ee0
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Generate BOM / Generate_BOM (push) Failing after 13s
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2025-07-30 16:29:55 -05:00

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Verilog

// generated by newgenasym Wed Jul 31 16:44:59 2019
module mpm3632 (agnd, bst, en, fb, out, out_sense, pg, pgnd, sw, vcc, vin);
input [1:0] agnd;
inout bst;
inout en;
inout fb;
output out;
output out_sense;
output pg;
input [3:0] pgnd;
output [2:0] sw;
output vcc;
input [1:0] vin;
initial
begin
end
endmodule