Daniel Lindmark 63a5cf2ee0
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Generate BOM / Generate_BOM (push) Failing after 13s
V1 commit
2025-07-30 16:29:55 -05:00

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240 B
Verilog

// generated by newgenasym Mon Sep 02 09:35:56 2019
module mpm3804 (en, fb, gnd, out, sw, vin);
inout en;
output fb;
input gnd;
output out;
output sw;
input vin;
initial
begin
end
endmodule