15 lines
365 B
VHDL
15 lines
365 B
VHDL
-- generated by newgenasym Mon Sep 02 09:35:56 2019
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mpm3804 is
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port (
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EN: INOUT STD_LOGIC;
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FB: OUT STD_LOGIC;
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GND: IN STD_LOGIC;
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\out\: OUT STD_LOGIC;
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SW: OUT STD_LOGIC;
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VIN: IN STD_LOGIC);
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end mpm3804;
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