Daniel Lindmark 63a5cf2ee0
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Generate BOM / Generate_BOM (push) Failing after 13s
V1 commit
2025-07-30 16:29:55 -05:00

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337 B
Verilog

// generated by newgenasym Thu Aug 01 14:31:15 2019
module mpm3833 (agnd, en, fb, nc, out, out_s, pg, pgnd, sw, vin);
input agnd;
inout en;
output fb;
inout nc;
output out;
output out_s;
inout pg;
input pgnd;
output [1:0] sw;
input [1:0] vin;
initial
begin
end
endmodule