Daniel Lindmark 63a5cf2ee0
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Generate BOM / Generate_BOM (push) Failing after 13s
V1 commit
2025-07-30 16:29:55 -05:00

19 lines
541 B
VHDL

-- generated by newgenasym Thu Aug 01 14:31:15 2019
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity mpm3833 is
port (
AGND: IN STD_LOGIC;
EN: INOUT STD_LOGIC;
FB: OUT STD_LOGIC;
NC: INOUT STD_LOGIC;
\out\: OUT STD_LOGIC;
OUT_S: OUT STD_LOGIC;
PG: INOUT STD_LOGIC;
PGND: IN STD_LOGIC;
SW: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
VIN: IN STD_LOGIC_VECTOR (1 DOWNTO 0));
end mpm3833;