58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
// generated by newgenasym Thu Sep 19 14:51:47 2019
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module mt41k256m16ha (a0, a1, a10_ap, a11, a12_bc_n, a13, a14, a15_nc, a2, a3, a4, a5,
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a6, a7, a8, a9, ba0, ba1, ba2, cas_n, cke, ckn, ckp, cs_n, dq, ldm,
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ldqsn, ldqsp, nc, odt, ras_n, reset_n, udm, udqsn, udqsp, vdd,
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vddq, vrefca, vrefdq, vss, vssq, we_n, zq);
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input a0;
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input a1;
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input a10_ap;
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input a11;
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input a12_bc_n;
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input a13;
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input a14;
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input a15_nc;
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input a2;
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input a3;
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input a4;
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input a5;
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input a6;
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input a7;
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input a8;
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input a9;
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input ba0;
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input ba1;
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input ba2;
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input cas_n;
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input cke;
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input ckn;
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input ckp;
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input cs_n;
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inout [15:0] dq;
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input ldm;
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inout ldqsn;
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inout ldqsp;
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inout [3:0] nc;
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input odt;
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input ras_n;
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input reset_n;
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input udm;
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inout udqsn;
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inout udqsp;
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input [8:0] vdd;
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input [8:0] vddq;
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input vrefca;
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input vrefdq;
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input [11:0] vss;
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input [8:0] vssq;
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input we_n;
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inout zq;
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initial
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begin
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end
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endmodule
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