52 lines
1.7 KiB
VHDL
52 lines
1.7 KiB
VHDL
-- generated by newgenasym Thu Sep 19 14:51:47 2019
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mt41k256m16ha is
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port (
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A0: IN STD_LOGIC;
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A1: IN STD_LOGIC;
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A10_AP: IN STD_LOGIC;
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A11: IN STD_LOGIC;
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A12_BC_N: IN STD_LOGIC;
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A13: IN STD_LOGIC;
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A14: IN STD_LOGIC;
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A15_NC: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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A5: IN STD_LOGIC;
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A6: IN STD_LOGIC;
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A7: IN STD_LOGIC;
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A8: IN STD_LOGIC;
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A9: IN STD_LOGIC;
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BA0: IN STD_LOGIC;
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BA1: IN STD_LOGIC;
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BA2: IN STD_LOGIC;
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CAS_N: IN STD_LOGIC;
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CKE: IN STD_LOGIC;
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CKN: IN STD_LOGIC;
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CKP: IN STD_LOGIC;
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CS_N: IN STD_LOGIC;
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DQ: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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LDM: IN STD_LOGIC;
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LDQSN: INOUT STD_LOGIC;
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LDQSP: INOUT STD_LOGIC;
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NC: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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ODT: IN STD_LOGIC;
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RAS_N: IN STD_LOGIC;
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RESET_N: IN STD_LOGIC;
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UDM: IN STD_LOGIC;
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UDQSN: INOUT STD_LOGIC;
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UDQSP: INOUT STD_LOGIC;
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VDD: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
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VDDQ: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
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VREFCA: IN STD_LOGIC;
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VREFDQ: IN STD_LOGIC;
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VSS: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
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VSSQ: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
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WE_N: IN STD_LOGIC;
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ZQ: INOUT STD_LOGIC);
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end mt41k256m16ha;
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