Daniel Lindmark 63a5cf2ee0
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Generate BOM / Generate_BOM (push) Failing after 13s
V1 commit
2025-07-30 16:29:55 -05:00

34 lines
587 B
Verilog

// generated by newgenasym Wed Sep 11 15:06:32 2019
module si5351a (a0, clk0, clk1, clk2, clk3, clk4, clk5, clk6, clk7, gnd, oeb,
scl, sda, ssen, vdd, vdd0d, vddoa, vddob, vddoc, xa, xb);
input a0;
output clk0;
output clk1;
output clk2;
output clk3;
output clk4;
output clk5;
output clk6;
output clk7;
input gnd;
input oeb;
input scl;
inout sda;
input ssen;
input vdd;
input vdd0d;
input vddoa;
input vddob;
input vddoc;
input xa;
input xb;
initial
begin
end
endmodule