30 lines
875 B
VHDL
30 lines
875 B
VHDL
-- generated by newgenasym Wed Sep 11 15:06:32 2019
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity si5351a is
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port (
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A0: IN STD_LOGIC;
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CLK0: OUT STD_LOGIC;
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CLK1: OUT STD_LOGIC;
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CLK2: OUT STD_LOGIC;
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CLK3: OUT STD_LOGIC;
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CLK4: OUT STD_LOGIC;
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CLK5: OUT STD_LOGIC;
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CLK6: OUT STD_LOGIC;
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CLK7: OUT STD_LOGIC;
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GND: IN STD_LOGIC;
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OEB: IN STD_LOGIC;
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SCL: IN STD_LOGIC;
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SDA: INOUT STD_LOGIC;
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SSEN: IN STD_LOGIC;
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VDD: IN STD_LOGIC;
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VDD0D: IN STD_LOGIC;
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VDDOA: IN STD_LOGIC;
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VDDOB: IN STD_LOGIC;
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VDDOC: IN STD_LOGIC;
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XA: IN STD_LOGIC;
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XB: IN STD_LOGIC);
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end si5351a;
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