generated from AllSpice-Demos/AllSpice-Altium-template-repo
Initial commit
This commit is contained in:
AllSpice-demos
commit
bed948c2a5
22
.allspice/.gitignore/.gitignore.altium
Normal file
22
.allspice/.gitignore/.gitignore.altium
Normal file
@ -0,0 +1,22 @@
|
||||
# ---> AltiumDesigner
|
||||
# For PCBs designed using Altium Designer
|
||||
# Website: https://www.altium.com/altium-designer/
|
||||
|
||||
# Directories containing cache data
|
||||
History
|
||||
__Previews
|
||||
|
||||
# Directories containing logs and generated outputs
|
||||
Project\ Logs*
|
||||
Project\ Outputs*
|
||||
|
||||
# Misc files generated by altium
|
||||
debug.log
|
||||
Status\ Report.txt
|
||||
*.PcbDoc.htm
|
||||
*.SchDocPreview
|
||||
*.PcbDocPreview
|
||||
|
||||
# Lock files sometimes left behind
|
||||
.~lock.*
|
||||
|
||||
53
.allspice/.gitignore/.gitignore.eagle
Normal file
53
.allspice/.gitignore/.gitignore.eagle
Normal file
@ -0,0 +1,53 @@
|
||||
# ---> Eagle
|
||||
# Ignore list for Eagle, a PCB layout tool
|
||||
|
||||
# Backup files
|
||||
*.s#?
|
||||
*.b#?
|
||||
*.l#?
|
||||
*.b$?
|
||||
*.s$?
|
||||
*.l$?
|
||||
|
||||
# Eagle project file
|
||||
# It contains a serial number and references to the file structure
|
||||
# on your computer.
|
||||
# comment the following line if you want to have your project file included.
|
||||
eagle.epf
|
||||
|
||||
# Autorouter files
|
||||
*.pro
|
||||
*.job
|
||||
|
||||
# CAM files
|
||||
*.$$$
|
||||
*.cmp
|
||||
*.ly2
|
||||
*.l15
|
||||
*.sol
|
||||
*.plc
|
||||
*.stc
|
||||
*.sts
|
||||
*.crc
|
||||
*.crs
|
||||
|
||||
*.dri
|
||||
*.drl
|
||||
*.gpi
|
||||
*.pls
|
||||
*.ger
|
||||
*.xln
|
||||
|
||||
*.drd
|
||||
*.drd.*
|
||||
|
||||
*.s#*
|
||||
*.b#*
|
||||
|
||||
*.info
|
||||
|
||||
*.eps
|
||||
|
||||
# file locks introduced since 7.x
|
||||
*.lck
|
||||
|
||||
31
.allspice/.gitignore/.gitignore.kicad
Normal file
31
.allspice/.gitignore/.gitignore.kicad
Normal file
@ -0,0 +1,31 @@
|
||||
# ---> KiCad
|
||||
# For PCBs designed using KiCad: https://www.kicad.org/
|
||||
# Format documentation: https://kicad.org/help/file-formats/
|
||||
|
||||
# Temporary files
|
||||
*.000
|
||||
*.bak
|
||||
*.bck
|
||||
*.kicad_pcb-bak
|
||||
*.kicad_sch-bak
|
||||
*-backups
|
||||
*.kicad_prl
|
||||
*.sch-bak
|
||||
*~
|
||||
_autosave-*
|
||||
*.tmp
|
||||
*-save.pro
|
||||
*-save.kicad_pcb
|
||||
fp-info-cache
|
||||
|
||||
# Netlist files (exported from Eeschema)
|
||||
*.net
|
||||
|
||||
# Autorouter files (exported from Pcbnew)
|
||||
*.dsn
|
||||
*.ses
|
||||
|
||||
# Exported BOM files
|
||||
*.xml
|
||||
*.csv
|
||||
|
||||
36
.allspice/.gitignore/.gitignore.orcad
Normal file
36
.allspice/.gitignore/.gitignore.orcad
Normal file
@ -0,0 +1,36 @@
|
||||
# ---> OrCAD
|
||||
# .gitignore for Cadence OrCAD projects
|
||||
# Website: https://www.orcad.com/
|
||||
|
||||
### OrCAD ###
|
||||
## Schematic
|
||||
# schematic design lock file
|
||||
*.DSNlck
|
||||
# design backup archive
|
||||
*.DBK
|
||||
|
||||
## PCB
|
||||
# pcb design lock file
|
||||
*.brd.lck
|
||||
# generated autorouter metadata
|
||||
*.did
|
||||
# local backup file
|
||||
AUTOSAVE.brd
|
||||
*.SAV
|
||||
last_import_time.txt
|
||||
# generated journal files
|
||||
*.jrl
|
||||
# generated error log file
|
||||
*.dmp
|
||||
|
||||
## General
|
||||
*.log
|
||||
# generated metadata file
|
||||
*_convert.txt
|
||||
# project lock file
|
||||
*.OLBlck
|
||||
# ultralibrarian generated documentation
|
||||
ImportGuide.html
|
||||
# generated orcad file, including which file was last opened
|
||||
master.tag
|
||||
|
||||
59
.allspice/issue_template/bug_report.yml
Normal file
59
.allspice/issue_template/bug_report.yml
Normal file
@ -0,0 +1,59 @@
|
||||
name: Bug Report
|
||||
about: File a bug report
|
||||
title: "[Bug]: "
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Thanks for taking the time to fill out this bug report!
|
||||
- type: input
|
||||
id: contact
|
||||
attributes:
|
||||
label: Contact Details
|
||||
description: How can we get in touch with you if we need more info?
|
||||
placeholder: ex. email@example.com
|
||||
validations:
|
||||
required: false
|
||||
- type: textarea
|
||||
id: what-happened
|
||||
attributes:
|
||||
label: What happened?
|
||||
description: Also tell us, what did you expect to happen?
|
||||
placeholder: Tell us what you see!
|
||||
value: "A bug happened!"
|
||||
validations:
|
||||
required: true
|
||||
- type: dropdown
|
||||
id: version
|
||||
attributes:
|
||||
label: Version
|
||||
description: What version of our software are you running?
|
||||
options:
|
||||
- 1.0.2 (Default)
|
||||
- 1.0.3 (Edge)
|
||||
validations:
|
||||
required: true
|
||||
- type: dropdown
|
||||
id: browsers
|
||||
attributes:
|
||||
label: What browsers are you seeing the problem on?
|
||||
multiple: true
|
||||
options:
|
||||
- Firefox
|
||||
- Chrome
|
||||
- Safari
|
||||
- Microsoft Edge
|
||||
- type: textarea
|
||||
id: logs
|
||||
attributes:
|
||||
label: Relevant log output
|
||||
description: Please copy and paste any relevant log output. This will be automatically formatted into code, so no need for backticks.
|
||||
render: shell
|
||||
- type: checkboxes
|
||||
id: terms
|
||||
attributes:
|
||||
label: Code of Conduct
|
||||
description: By submitting this issue, you agree to follow our [Code of Conduct](https://example.com)
|
||||
options:
|
||||
- label: I agree to follow this project's Code of Conduct
|
||||
required: true
|
||||
61
.allspice/issue_template/new_component_request.yml
Normal file
61
.allspice/issue_template/new_component_request.yml
Normal file
@ -0,0 +1,61 @@
|
||||
name: New component request
|
||||
about: Submit to add/update a component/symbol/footprint to the library
|
||||
title: "[Component]: "
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Submit to add/update a component/symbol/footprint to the library
|
||||
- type: dropdown
|
||||
id: component-type
|
||||
attributes:
|
||||
label: Component type
|
||||
multiple: false
|
||||
options:
|
||||
- Passive
|
||||
- Power supply
|
||||
- Microcontrollers
|
||||
- Analog
|
||||
- Digital
|
||||
- Other
|
||||
- type: input
|
||||
id: where-used
|
||||
attributes:
|
||||
label: Where used
|
||||
description: List what assemblies / pcbs will use this component
|
||||
placeholder: ASMXXXX
|
||||
value: "ASMXXXX"
|
||||
- type: input
|
||||
id: qty-estimate
|
||||
attributes:
|
||||
label: Estimated annual quantity
|
||||
description: Estimated annual quantity
|
||||
placeholder: Ten
|
||||
value: "10,000"
|
||||
- type: textarea
|
||||
id: part-numbers
|
||||
attributes:
|
||||
label: Part numbers
|
||||
description: List mfg and internal part numbers
|
||||
placeholder: List mfg and internal part numbers, add at least one distributor part number
|
||||
value: "add part numbers"
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: description
|
||||
attributes:
|
||||
label: Description
|
||||
description: Give an explanation for why we need this new part, as well as any details or notes
|
||||
placeholder: why we need this part
|
||||
value: "why we need this part"
|
||||
validations:
|
||||
required: true
|
||||
|
||||
- type: checkboxes
|
||||
id: terms
|
||||
attributes:
|
||||
label: Due diligence done
|
||||
description: By submitting this issue, you agree you searched our component library for existing components before requesting a new component
|
||||
options:
|
||||
- label: I checked the library for existing parts
|
||||
required: true
|
||||
208
.allspice/pull_request_template.md
Normal file
208
.allspice/pull_request_template.md
Normal file
@ -0,0 +1,208 @@
|
||||
---
|
||||
|
||||
name: "AllSpice Pull Request Template"
|
||||
about: "Optional description"
|
||||
|
||||
---
|
||||
|
||||
*This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!*
|
||||
|
||||
## Resolved Issues
|
||||
<!-- Include any relevant issues closed by this pull request. Use the form "Closes #<number of issue>" -->
|
||||
...
|
||||
|
||||
## Description
|
||||
<!-- Include a description for this design review. What is the primary purpose? What will be the status of this design after approval? -->
|
||||
...
|
||||
|
||||
## Design Review Checklist
|
||||
### Process
|
||||
- [ ] Schematic and PCB file names follow standard
|
||||
- [ ] Export necessary review files (3D model, BOM, etc.)
|
||||
- [ ] Update relevant system architecture documents
|
||||
- [ ] Update project README page
|
||||
- [ ] Simulations uploaded and outputs explained
|
||||
### System
|
||||
- [ ] Power
|
||||
- [ ] Sufficient power supplied from upstream source
|
||||
- [ ] Supply rated for necessary country specifications
|
||||
- [ ] Estimated total worst-case power supply draw
|
||||
- [ ] Connectors
|
||||
- [ ] I/Os are specified
|
||||
- [ ] Sufficient Current and Voltage rating
|
||||
- [ ] Mating connectors have matching pinout
|
||||
- [ ] Same contact material specified for mating connectors
|
||||
- [ ] Testing
|
||||
- [ ] Test procedure written
|
||||
- [ ] Environmental
|
||||
- [ ] Specified min/max operating temperature
|
||||
- [ ] Specified min/max storage temperature
|
||||
- [ ] Specified min/max humidity
|
||||
- [ ] ROHS compliance requirement review
|
||||
### Components
|
||||
- [ ] Unpopulated components are denoted DNI
|
||||
- [ ] Components meet environmental specifications
|
||||
- [ ] All components have quantity, reference designator and description
|
||||
- [ ] Suggested and alternate manufacturers listed
|
||||
- [ ] Price and stock checked for each component
|
||||
- [ ] Component derating
|
||||
- [ ] Voltage
|
||||
- [ ] Current
|
||||
- [ ] Power at worst-case operating temperature
|
||||
- [ ] Temperature at worst-case power
|
||||
### Schematics
|
||||
- [ ] Document
|
||||
- [ ] Dot on each connection
|
||||
- [ ] No four-point connections
|
||||
- [ ] Title block completed for each sheet
|
||||
- [ ] All components have reference designators and values
|
||||
- [ ] Multi-part components don't have unplaced symbols
|
||||
- [ ] Page title present and consistent on all pages if not in title block
|
||||
- [ ] Symbols identify open collector/drain pins and internal pulled up/down pins
|
||||
- [ ] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
|
||||
- [ ] Components follow preferred reference designator pattern <!-- Link to spec -->
|
||||
- [ ] External I/O
|
||||
- [ ] Filtered for EMI
|
||||
- [ ] Protected against electrostatic discharge (ESD)
|
||||
- [ ] Unused inputs terminated
|
||||
- [ ] Microcontrollers / ICs
|
||||
- [ ] Predictable or controlled power-up state
|
||||
- [ ] Reset filtered
|
||||
- [ ] Sufficient bypass capacitance
|
||||
- [ ] Oscillators checked for reliable startup
|
||||
- [ ] Pullups on open-collector pins
|
||||
- [ ] Logic-low and logic-high voltage levels checked
|
||||
- [ ] No-connect pins labeled NC
|
||||
- [ ] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
|
||||
- [ ] Check for input voltages applied with power off and CMOS latchup possibilities
|
||||
- [ ] Check the data sheet errata and apnotes for weird IC behaviors
|
||||
- [ ] Busses
|
||||
- [ ] UART/USART TX->RX and RX<-TX
|
||||
- [ ] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf)
|
||||
- [ ] Setup, hold, access times for data and address busses
|
||||
- [ ] Analog
|
||||
- [ ] Sufficient power rails for analog circuits
|
||||
- [ ] Amplifiers checked for stability
|
||||
- [ ] Consider signal rate-of-rise and fall for noise radiation
|
||||
- [ ] General
|
||||
- [ ] Sufficient bulk capacitance calculated
|
||||
- [ ] Polarized components checked
|
||||
- [ ] Electrolytic/tantalum capacitors checked for no reverse voltage
|
||||
- [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
|
||||
- [ ] Sufficient capacitance on low dropout voltage regulators
|
||||
- [ ] Sufficient time delays and slew rates for comparators
|
||||
- [ ] Sufficient common mode input voltage rating on opamps
|
||||
- [ ] Check pin numbers of all custom-generated parts
|
||||
- [ ] Check reverse base-emitter current/voltage on bipolar transistors
|
||||
- [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`)
|
||||
- [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default
|
||||
### PCB
|
||||
- [ ] Manufacturing
|
||||
- [ ] PCB manufacturing requirements noted on `fab` layer
|
||||
- [ ] Plating specified
|
||||
- [ ] Plating material
|
||||
- [ ] Plating thickness
|
||||
- [ ] Layer stack-up specified
|
||||
- [ ] Minimum trace/space specified
|
||||
- [ ] Minimum hole size specified
|
||||
- [ ] PCB color specified
|
||||
- [ ] Silkscreen color specified
|
||||
- [ ] Controlled impedance specified
|
||||
- [ ] Blind or buried vias specified
|
||||
- [ ] Panelization specified
|
||||
- [ ] External routing specified (ex. v-groove vs route)
|
||||
- [ ] Drill table generated
|
||||
- [ ] All specifications exceed manufacturing tolerance
|
||||
- [ ] Space between power planes minimized
|
||||
- [ ] Solder paste openings proper size
|
||||
- [ ] Fiducials placed if necessary
|
||||
- [ ] Footprints
|
||||
- [ ] Pin 1 marked in a consistent manner
|
||||
- [ ] Component polarity marked
|
||||
- [ ] Diodes, LEDs
|
||||
- [ ] Electrolytic, tantalum capacitors
|
||||
- [ ] Keyed components like connectors
|
||||
- [ ] Footprint dimensions cross-checked with datasheet recommendation
|
||||
- [ ] Sufficient thermal pads on high-power components or nets
|
||||
- [ ] Placement
|
||||
- [ ] Jumpers accessible
|
||||
- [ ] Debug connectors accessible
|
||||
- [ ] Filter resistors closer to source
|
||||
- [ ] Termination resistors close to target
|
||||
- [ ] Small loop path on switch-mode power supplies
|
||||
- [ ] Bypass capacitors close to ICs
|
||||
- [ ] Bypass capacitors close to connectors
|
||||
- [ ] Drivers / receivers close to connectors
|
||||
- [ ] SMT components on top side, through-hole components on bottom side if possible
|
||||
- [ ] Clearance
|
||||
- [ ] Keep-out areas honored
|
||||
- [ ] Around mounting holes
|
||||
- [ ] For programming tools
|
||||
- [ ] For assembly tools (wrenches, screwdrivers etc.)
|
||||
- [ ] For connectors
|
||||
- [ ] Trace-to-trace clearance based upon voltage rating
|
||||
- [ ] Component size based upon voltage rating
|
||||
- [ ] Keep components away from board edge
|
||||
- [ ] Mechanical
|
||||
- [ ] CAD file uploaded
|
||||
- [ ] Clearance above connectors
|
||||
- [ ] Clearance below through-hole components
|
||||
- [ ] Enough space for the minimum bending radius of the wire harness
|
||||
- [ ] Mounting holes electrically isolated if necessary
|
||||
- [ ] Mounting holes have via stitching
|
||||
- [ ] Hole diameters leave margin for plating
|
||||
- [ ] Board outline defined
|
||||
- [ ] Mechanical enclosure defined
|
||||
- [ ] Internal corners are rounded and can be milled
|
||||
- [ ] Electrical
|
||||
- [ ] All traces are routed
|
||||
- [ ] Analog and digital commons joined at only one point
|
||||
- [ ] ERC passes
|
||||
- [ ] Isolation barriers are large enough
|
||||
- [ ] Signal integrity
|
||||
- [ ] Gaps in ground planes checked and minimized
|
||||
- [ ] High-speed signals avoid gaps in ground planes
|
||||
- [ ] Stubs minimized for high-speed signals
|
||||
- [ ] Differential pair spacing based upon impedance matching
|
||||
- [ ] Transmission lines terminated with an appropriate impedance
|
||||
- [ ] Crystal connections kept short
|
||||
- [ ] Guard ring around crystals
|
||||
- [ ] Traces avoided under sensitive components
|
||||
- [ ] Traces avoided under noisy components
|
||||
- [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
|
||||
- [ ] Option for a shielding can over sensitive circuitry e.g. RF?
|
||||
- [ ] Copper pour
|
||||
- [ ] All planes have been poured
|
||||
- [ ] Planes and pours checked for high-impedance paths
|
||||
- [ ] No pour between adjacent pins on ICs
|
||||
- [ ] Traces
|
||||
- [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more)
|
||||
- [ ] Trace widths sufficient for the current draw and max heating
|
||||
- [ ] No connections between adjacent pins on ICs
|
||||
- [ ] Vias for internal power traces sufficiently large
|
||||
- [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
|
||||
- [ ] Thermal
|
||||
- [ ] Temperature sensitive components placed away from hot components
|
||||
- [ ] Thermal vias in thermal pads
|
||||
- [ ] Testing
|
||||
- [ ] Test points on PCBs for critical circuits, hard to reach nets
|
||||
- [ ] Ground connection points close to analog test points
|
||||
- [ ] Silk screen
|
||||
- [ ] Notes and documentation
|
||||
- [ ] Updated revision number
|
||||
- [ ] Updated date
|
||||
- [ ] Blank space designated for a serial / assembly number
|
||||
- [ ] No silk screen over pads / vias
|
||||
- [ ] Text is readable from at most two directions
|
||||
- [ ] Silk screen size / font will legible after printing
|
||||
- [ ] Connector pin-outs labeled
|
||||
- [ ] Fuse size and type marked on PCB
|
||||
- [ ] Functional groups marked
|
||||
- [ ] Functionality labeled
|
||||
- [ ] Test points
|
||||
- [ ] LEDs
|
||||
- [ ] Buttons
|
||||
- [ ] Connectors/terminals
|
||||
- [ ] Jumpers/fuses
|
||||
|
||||
<!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
|
||||
5
.gitattributes
vendored
Normal file
5
.gitattributes
vendored
Normal file
@ -0,0 +1,5 @@
|
||||
*.[oO][uU][tT][jJ][oO][bB] binary linguist-detectable
|
||||
*.[pP][cC][bB][dD][oO][cC] diff=allspice linguist-detectable
|
||||
*.[pP][rR][jJ][pP][cC][bB] binary linguist-generated
|
||||
*.[sS][cC][hH][dD][oO][cC] diff=allspice linguist-detectable
|
||||
*.cmp diff=allspice linguist-detectable
|
||||
22
.gitignore
vendored
Normal file
22
.gitignore
vendored
Normal file
@ -0,0 +1,22 @@
|
||||
# ---> AltiumDesigner
|
||||
# For PCBs designed using Altium Designer
|
||||
# Website: https://www.altium.com/altium-designer/
|
||||
|
||||
# Directories containing cache data
|
||||
History
|
||||
__Previews
|
||||
|
||||
# Directories containing logs and generated outputs
|
||||
Project\ Logs*
|
||||
Project\ Outputs*
|
||||
|
||||
# Misc files generated by altium
|
||||
debug.log
|
||||
Status\ Report.txt
|
||||
*.PcbDoc.htm
|
||||
*.SchDocPreview
|
||||
*.PcbDocPreview
|
||||
|
||||
# Lock files sometimes left behind
|
||||
.~lock.*
|
||||
|
||||
BIN
images/new_repo.png
Normal file
BIN
images/new_repo.png
Normal file
Binary file not shown.
|
After 
(image error) Size: 1.3 MiB |
Loading…
Reference in New Issue
Block a user