README.md

@@ -1,3 +1,53 @@
-# HW-FW-Releases-Demo
+# Archimajor
 
-A repository demonstrating the usage of git submodules to track and map HW releases to FW releases.
+<img align="left" width="300" height="200" src="./hw/.allspice/PCB.PNG">
+
+## Summary
+
+3D printer motherboard, designed by [Ultimachine](https://ultimachine.com/). Features include:
+
+- **5x integrated 256 microstep motor drivers**
+- **6x PWM Mosfet outputs**
+- **4x thermistor inputs**
+- **SPI (Serial Peripheral Interface)**
+- ** Removed infinite loop on self-calibration.
+
+---
+
+## Specifications
+
+### General Specifications
+
+**Input Power Supply**: 12V - 24V DC, 16A+
+
+**Operating Temperature Range (est.)**: 0dC ~ 70dC
+
+## Component library
+
+[Archimajor Component Library](https://hub.allspice.io/Allspice-demos/Altium-component-library-demo)
+
+
+## Firmware
+
+### Firmware Repo
+
+[Current FW image](https://github.com/ultimachine/Marlin/commit/2f9e3b771e2669118cce922ad52785165e16d1e9)
+
+### Original source
+[Source](https://github.com/ultimachine/Marlin4due/tree/Archim2)
+
+### Legacy firmware (use releases for current fw)
+[Binary](https://github.com/MarlinFirmware/Marlin/archive/bugfix-2.0.x.zip)
+
+## Bill of Materials
+
+[Archimajor.csv](./Archimajor.csv)
+
+## Note
+
+Changed heat bed fuse holder to yellow to differentiate channels.
+
+
+## Disclaimer
+
+*NOTE: This does not represent actual data from the Rambo/Archimajor PCBA

hw/.allspice/.gitignore/.gitignore.altium

@@ -0,0 +1,22 @@
+# ---> AltiumDesigner
+# For PCBs designed using Altium Designer
+# Website: https://www.altium.com/altium-designer/
+
+# Directories containing cache data
+History
+__Previews
+
+# Directories containing logs and generated outputs
+Project\ Logs*
+Project\ Outputs*
+
+# Misc files generated by altium
+debug.log
+Status\ Report.txt
+*.PcbDoc.htm
+*.SchDocPreview
+*.PcbDocPreview
+
+# Lock files sometimes left behind
+.~lock.*
+

hw/.allspice/.gitignore/.gitignore.eagle

@@ -0,0 +1,53 @@
+# ---> Eagle
+# Ignore list for Eagle, a PCB layout tool
+
+# Backup files
+*.s#?
+*.b#?
+*.l#?
+*.b$?
+*.s$?
+*.l$?
+
+# Eagle project file
+# It contains a serial number and references to the file structure
+# on your computer.
+# comment the following line if you want to have your project file included.
+eagle.epf
+
+# Autorouter files
+*.pro
+*.job
+
+# CAM files
+*.$$$
+*.cmp
+*.ly2
+*.l15
+*.sol
+*.plc
+*.stc
+*.sts
+*.crc
+*.crs
+
+*.dri
+*.drl
+*.gpi
+*.pls
+*.ger
+*.xln
+
+*.drd
+*.drd.*
+
+*.s#*
+*.b#*
+
+*.info
+
+*.eps
+
+# file locks introduced since 7.x
+*.lck
+

hw/.allspice/.gitignore/.gitignore.kicad

@@ -0,0 +1,31 @@
+# ---> KiCad
+# For PCBs designed using KiCad: https://www.kicad.org/
+# Format documentation: https://kicad.org/help/file-formats/
+
+# Temporary files
+*.000
+*.bak
+*.bck
+*.kicad_pcb-bak
+*.kicad_sch-bak
+*-backups
+*.kicad_prl
+*.sch-bak
+*~
+_autosave-*
+*.tmp
+*-save.pro
+*-save.kicad_pcb
+fp-info-cache
+
+# Netlist files (exported from Eeschema)
+*.net
+
+# Autorouter files (exported from Pcbnew)
+*.dsn
+*.ses
+
+# Exported BOM files
+*.xml
+*.csv
+

hw/.allspice/.gitignore/.gitignore.orcad

@@ -0,0 +1,36 @@
+# ---> OrCAD
+# .gitignore for Cadence OrCAD projects
+# Website: https://www.orcad.com/
+
+### OrCAD ###
+## Schematic
+# schematic design lock file
+*.DSNlck
+# design backup archive
+*.DBK
+
+## PCB
+# pcb design lock file
+*.brd.lck
+# generated autorouter metadata
+*.did
+# local backup file
+AUTOSAVE.brd
+*.SAV
+last_import_time.txt
+# generated journal files
+*.jrl
+# generated error log file
+*.dmp
+
+## General
+*.log
+# generated metadata file
+*_convert.txt
+# project lock file
+*.OLBlck
+# ultralibrarian generated documentation
+ImportGuide.html
+# generated orcad file, including which file was last opened
+master.tag
+

hw/.allspice/columns.json

@@ -0,0 +1,6 @@
+{
+  "Part Number": ["PART", "MANUFACTURER #", "_part_id"],
+  "Manufacturer": ["Manufacturer", "MANUFACTURER"],
+  "Designator": ["Designator"],
+  "Description": ["PART DESCRIPTION"]
+}

hw/.allspice/issue_template/bug_report.yml

@@ -0,0 +1,59 @@
+name: Bug Report
+about: File a bug report
+title: "[Bug]: "
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Thanks for taking the time to fill out this bug report!        
+  - type: input
+    id: contact
+    attributes:
+      label: Contact Details
+      description: How can we get in touch with you if we need more info?
+      placeholder: ex. email@example.com
+    validations:
+      required: false
+  - type: textarea
+    id: what-happened
+    attributes:
+      label: What happened?
+      description: Also tell us, what did you expect to happen?
+      placeholder: Tell us what you see!
+      value: "A bug happened!"
+    validations:
+      required: true
+  - type: dropdown
+    id: version
+    attributes:
+      label: Version
+      description: What version of our software are you running?
+      options:
+        - 1.0.2 (Default)
+        - 1.0.3 (Edge)
+    validations:
+      required: true
+  - type: dropdown
+    id: browsers
+    attributes:
+      label: What browsers are you seeing the problem on?
+      multiple: true
+      options:
+        - Firefox
+        - Chrome
+        - Safari
+        - Microsoft Edge
+  - type: textarea
+    id: logs
+    attributes:
+      label: Relevant log output
+      description: Please copy and paste any relevant log output. This will be automatically formatted into code, so no need for backticks.
+      render: shell
+  - type: checkboxes
+    id: terms
+    attributes:
+      label: Code of Conduct
+      description: By submitting this issue, you agree to follow our [Code of Conduct](https://example.com)
+      options:
+        - label: I agree to follow this project's Code of Conduct
+          required: true

hw/.allspice/issue_template/new_component_request.yml

@@ -0,0 +1,61 @@
+name: New component request
+about: Submit to add/update a component/symbol/footprint to the library
+title: "[Component]: "
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Submit to add/update a component/symbol/footprint to the library      
+  - type: dropdown
+    id: component-type
+    attributes:
+      label: Component type
+      multiple: false
+      options:
+        - Passive
+        - Power supply
+        - Microcontrollers
+        - Analog
+        - Digital
+        - Other
+  - type: input
+    id: where-used
+    attributes:
+      label: Where used
+      description: List what assemblies / pcbs will use this component
+      placeholder: ASMXXXX
+      value: "ASMXXXX"
+  - type: input
+    id: qty-estimate
+    attributes:
+      label: Estimated annual quantity
+      description: Estimated annual quantity
+      placeholder: Ten
+      value: "10,000"
+  - type: textarea
+    id: part-numbers
+    attributes:
+      label: Part numbers
+      description: List mfg and internal part numbers
+      placeholder: List mfg and internal part numbers, add at least one distributor part number
+      value: "add part numbers"
+    validations:
+      required: true
+  - type: textarea
+    id: description
+    attributes:
+      label: Description
+      description: Give an explanation for why we need this new part, as well as any details or notes
+      placeholder: why we need this part
+      value: "why we need this part"
+    validations:
+      required: true
+
+  - type: checkboxes
+    id: terms
+    attributes:
+      label: Due diligence done
+      description: By submitting this issue, you agree you searched our component library for existing components before requesting a new component
+      options:
+        - label: I checked the library for existing parts
+          required: true

hw/.allspice/pull_request_template.md

@@ -0,0 +1,208 @@
+---
+
+name: "AllSpice Pull Request Template"
+about: "Optional description"
+
+---
+
+*This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!*
+
+## Resolved Issues
+<!-- Include any relevant issues closed by this pull request. Use the form "Closes #<number of issue>" -->
+...
+
+## Description
+<!-- Include a description for this design review. What is the primary purpose? What will be the status of this design after approval? -->
+...
+
+## Design Review Checklist
+### Process
+- [ ] Schematic and PCB file names follow standard
+- [ ] Export necessary review files (3D model, BOM, etc.)
+- [ ] Update relevant system architecture documents
+- [ ] Update project README page
+- [ ] Simulations uploaded and outputs explained
+### System
+- [ ] Power
+  - [ ] Sufficient power supplied from upstream source
+  - [ ] Supply rated for necessary country specifications
+  - [ ] Estimated total worst-case power supply draw
+- [ ] Connectors
+  - [ ] I/Os are specified
+  - [ ] Sufficient Current and Voltage rating
+  - [ ] Mating connectors have matching pinout
+  - [ ] Same contact material specified for mating connectors
+- [ ] Testing
+  - [ ] Test procedure written
+- [ ] Environmental
+  - [ ] Specified min/max operating temperature
+  - [ ] Specified min/max storage temperature
+  - [ ] Specified min/max humidity
+- [ ] ROHS compliance requirement review
+### Components
+- [ ] Unpopulated components are denoted DNI
+- [ ] Components meet environmental specifications
+- [ ] All components have quantity, reference designator and description
+- [ ] Suggested and alternate manufacturers listed
+- [ ] Price and stock checked for each component
+- [ ] Component derating
+  - [ ] Voltage
+  - [ ] Current
+  - [ ] Power at worst-case operating temperature
+  - [ ] Temperature at worst-case power
+### Schematics
+- [ ] Document
+  - [ ] Dot on each connection
+  - [ ] No four-point connections
+  - [ ] Title block completed for each sheet
+  - [ ] All components have reference designators and values
+  - [ ] Multi-part components don't have unplaced symbols
+  - [ ] Page title present and consistent on all pages if not in title block
+  - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins
+  - [ ] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
+  - [ ] Components follow preferred reference designator pattern <!-- Link to spec -->
+- [ ] External I/O
+  - [ ] Filtered for EMI
+  - [ ] Protected against electrostatic discharge (ESD)
+  - [ ] Unused inputs terminated
+- [ ] Microcontrollers / ICs
+  - [ ] Predictable or controlled power-up state
+    - [ ] Reset filtered
+  - [ ] Sufficient bypass capacitance
+  - [ ] Oscillators checked for reliable startup
+  - [ ] Pullups on open-collector pins
+  - [ ] Logic-low and logic-high voltage levels checked
+  - [ ] No-connect pins labeled NC
+  - [ ] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
+  - [ ] Check for input voltages applied with power off and CMOS latchup possibilities
+  - [ ] Check the data sheet errata and apnotes for weird IC behaviors
+- [ ] Busses
+  - [ ] UART/USART TX->RX and RX<-TX
+  - [ ] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf)
+  - [ ] Setup, hold, access times for data and address busses
+- [ ] Analog
+  - [ ] Sufficient power rails for analog circuits
+  - [ ] Amplifiers checked for stability
+  - [ ] Consider signal rate-of-rise and fall for noise radiation
+- [ ] General
+  - [ ] Sufficient bulk capacitance calculated
+  - [ ] Polarized components checked
+  - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage
+  - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
+  - [ ] Sufficient capacitance on low dropout voltage regulators
+  - [ ] Sufficient time delays and slew rates for comparators
+  - [ ] Sufficient common mode input voltage rating on opamps
+  - [ ] Check pin numbers of all custom-generated parts
+  - [ ] Check reverse base-emitter current/voltage on bipolar transistors
+  - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`)
+  - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default
+### PCB
+- [ ] Manufacturing
+  - [ ] PCB manufacturing requirements noted on `fab` layer
+    - [ ] Plating specified
+      - [ ] Plating material
+      - [ ] Plating thickness
+    - [ ] Layer stack-up specified
+    - [ ] Minimum trace/space specified
+    - [ ] Minimum hole size specified
+    - [ ] PCB color specified
+    - [ ] Silkscreen color specified
+    - [ ] Controlled impedance specified
+    - [ ] Blind or buried vias specified
+    - [ ] Panelization specified
+      - [ ] External routing specified (ex. v-groove vs route)
+    - [ ] Drill table generated
+    - [ ] All specifications exceed manufacturing tolerance
+  - [ ] Space between power planes minimized
+  - [ ] Solder paste openings proper size
+  - [ ] Fiducials placed if necessary
+- [ ] Footprints
+  - [ ] Pin 1 marked in a consistent manner
+  - [ ] Component polarity marked
+    - [ ] Diodes, LEDs
+    - [ ] Electrolytic, tantalum capacitors
+    - [ ] Keyed components like connectors
+  - [ ] Footprint dimensions cross-checked with datasheet recommendation
+  - [ ] Sufficient thermal pads on high-power components or nets
+- [ ] Placement
+  - [ ] Jumpers accessible
+  - [ ] Debug connectors accessible
+  - [ ] Filter resistors closer to source
+  - [ ] Termination resistors close to target
+  - [ ] Small loop path on switch-mode power supplies
+  - [ ] Bypass capacitors close to ICs
+  - [ ] Bypass capacitors close to connectors
+  - [ ] Drivers / receivers close to connectors
+  - [ ] SMT components on top side, through-hole components on bottom side if possible
+- [ ] Clearance
+  - [ ] Keep-out areas honored
+    - [ ] Around mounting holes
+    - [ ] For programming tools
+    - [ ] For assembly tools (wrenches, screwdrivers etc.)
+    - [ ] For connectors
+  - [ ] Trace-to-trace clearance based upon voltage rating
+  - [ ] Component size based upon voltage rating
+  - [ ] Keep components away from board edge
+- [ ] Mechanical
+  - [ ] CAD file uploaded
+  - [ ] Clearance above connectors
+  - [ ] Clearance below through-hole components
+  - [ ] Enough space for the minimum bending radius of the wire harness
+  - [ ] Mounting holes electrically isolated if necessary
+    - [ ] Mounting holes have via stitching
+  - [ ] Hole diameters leave margin for plating
+  - [ ] Board outline defined
+  - [ ] Mechanical enclosure defined
+  - [ ] Internal corners are rounded and can be milled
+- [ ] Electrical
+  - [ ] All traces are routed
+  - [ ] Analog and digital commons joined at only one point
+  - [ ] ERC passes
+  - [ ] Isolation barriers are large enough
+- [ ] Signal integrity
+  - [ ] Gaps in ground planes checked and minimized
+  - [ ] High-speed signals avoid gaps in ground planes
+  - [ ] Stubs minimized for high-speed signals
+  - [ ] Differential pair spacing based upon impedance matching
+  - [ ] Transmission lines terminated with an appropriate impedance
+  - [ ] Crystal connections kept short
+  - [ ] Guard ring around crystals
+  - [ ] Traces avoided under sensitive components
+  - [ ] Traces avoided under noisy components
+  - [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
+  - [ ] Option for a shielding can over sensitive circuitry e.g. RF?
+- [ ] Copper pour
+  - [ ] All planes have been poured
+  - [ ] Planes and pours checked for high-impedance paths
+  - [ ] No pour between adjacent pins on ICs
+- [ ] Traces
+  - [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more)
+  - [ ] Trace widths sufficient for the current draw and max heating
+  - [ ] No connections between adjacent pins on ICs
+  - [ ] Vias for internal power traces sufficiently large
+  - [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
+- [ ] Thermal
+  - [ ] Temperature sensitive components placed away from hot components
+  - [ ] Thermal vias in thermal pads
+- [ ] Testing
+  - [ ] Test points on PCBs for critical circuits, hard to reach nets
+  - [ ] Ground connection points close to analog test points
+- [ ] Silk screen
+  - [ ] Notes and documentation
+    - [ ] Updated revision number
+    - [ ] Updated date
+    - [ ] Blank space designated for a serial / assembly number
+  - [ ] No silk screen over pads / vias
+  - [ ] Text is readable from at most two directions
+  - [ ] Silk screen size / font will legible after printing
+  - [ ] Connector pin-outs labeled
+  - [ ] Fuse size and type marked on PCB
+  - [ ] Functional groups marked
+  - [ ] Functionality labeled
+    - [ ] Test points
+    - [ ] LEDs
+    - [ ] Buttons
+    - [ ] Connectors/terminals
+    - [ ] Jumpers/fuses
+
+<!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->

hw/.allspice/utils/generate_netlist.py

@@ -0,0 +1,104 @@
+#! /usr/bin/env python3
+
+# Generate a Netlist from a PcbDoc file.
+# For more information, read the README file in this directory.
+
+import argparse
+import os
+import sys
+from contextlib import ExitStack
+
+from allspice import AllSpice
+from allspice.utils.netlist_generation import generate_netlist
+
+
+if __name__ == "__main__":
+    print("Hello World")
+    # Parse command line arguments. If you're writing a special purpose script,
+    # you can hardcode these values instead of using command line arguments.
+    parser = argparse.ArgumentParser(
+        prog="generate_pcb_netlist", description="Generate a netlist from a PCB file."
+    )
+    parser.add_argument("repository", help="The repo containing the project")
+    parser.add_argument(
+        "pcb_file",
+        help="The path to the PCB file in the source repo.",
+    )
+    parser.add_argument(
+        "--source_ref",
+        help="The git reference the netlist should be generated for (eg. branch name, tag name, commit SHA). Defaults to main.",
+        default="main",
+    )
+    parser.add_argument(
+        "--allspice_hub_url",
+        help="The URL of your AllSpice Hub instance. Defaults to https://hub.allspice.io.",
+    )
+    parser.add_argument(
+        "--output_file",
+        help="The path to the output file. If absent, the output will direct to the command line.",
+    )
+
+    args = parser.parse_args()
+
+    # Use Environment Variables to store your auth token. This keeps your token
+    # secure when sharing code.
+    auth_token = os.environ.get("ALLSPICE_AUTH_TOKEN")
+    if auth_token is None:
+        print("Please set the environment variable ALLSPICE_AUTH_TOKEN")
+        exit(1)
+
+    if args.allspice_hub_url is None:
+        allspice = AllSpice(token_text=auth_token)
+    else:
+        allspice = AllSpice(
+            token_text=auth_token, allspice_hub_url=args.allspice_hub_url
+        )
+
+    try:
+        # Test connection and key
+        print("AllSpice Version: " + allspice.get_version())
+
+        # Test private API call
+        print("API-Token belongs to user: " + allspice.get_user().username)
+
+    except Exception as e:
+        print(f"Could not connect to AllSpice Hub: {e}")
+        exit(1)
+
+    repo_owner, repo_name = args.repository.split("/")
+    try:
+        print(f"repo_owner={repo_owner}, repo_name={repo_name}")
+        repository = allspice.get_repository(repo_owner, repo_name)
+    except Exception as e:
+        print(f"Could not find repository {args.repository}: {e}")
+        exit(1)        
+    pcb_file = args.pcb_file
+
+    print("Generating PCB Netlist...🏃", file=sys.stderr)
+
+    netlist_rows = generate_netlist(
+        allspice,
+        repository,
+        pcb_file,
+        args.source_ref,
+    )
+
+    with ExitStack() as stack:
+        if args.output_file is not None:
+            writer = stack.enter_context(open(args.output_file, "w"))
+        else:
+            writer = sys.stdout
+
+        nets = list(netlist_rows.keys())
+
+        # It's helpful to sort here to generate repeatable netlist files
+        nets.sort()
+
+        # You can change formatting here
+        for net in nets:
+            writer.write(net + "\n")
+            pins_on_net = netlist_rows[net]
+            pins_on_net.sort()
+            writer.write(" " + " ".join(pins_on_net) + "\n")
+
+    print("Generated PCB netlist.", file=sys.stderr)

hw/.allspice/utils/hello-world.py

@@ -0,0 +1 @@
+print("Hello World!")

hw/.allspice/utils/py-allspice-BIST.py

@@ -0,0 +1,57 @@
+# HelloWorld.py
+
+# If you're new to scripting, this is a great place to start.
+
+# Hello World starts you out easy with some simple server requests.
+# This will help you troubleshoot your connection and show you the basics of making an api request
+#
+# For more information read our README.md
+from allspice import AllSpice
+import argparse, sys
+
+
+
+    
+print("Starting Test")
+
+parser = argparse.ArgumentParser(
+        prog="Allspice_API_BIST", description="Test connection and execution of API actions"
+    )
+
+parser.add_argument(
+    "--allspice_hub_url",
+    help="The URL of your AllSpice Hub instance. Defaults to https://hub.allspice.io.",
+)
+parser.add_argument(
+    "--allspice_token",
+    help="Your AllSpice application token. Generate a token: https://hub.allspice.io/user/settings/applications",
+)
+
+print("Parsing args")
+args = parser.parse_args()
+
+auth_token = args.allspice_token
+if auth_token is None:
+    print("Please supply a token with --allspice_token <your_token> Generate a token: https://hub.allspice.io/user/settings/applications")
+    sys.exit(1)
+print(f"Auth token {auth_token}")
+
+if args.allspice_hub_url is None:
+    allspice = AllSpice(token_text="https://hub.allspice.io")
+else:
+    try:
+        allspice = AllSpice(
+            token_text=auth_token, allspice_hub_url=args.allspice_hub_url
+        )
+    except Exception as e:
+        print("Error")
+        sys.exit(1)
+
+print("Finish making connection")
+# Test connection and key
+print("AllSpice Version: " + allspice.get_version())
+
+# Test private API call
+print("API-Token belongs to user: " + allspice.get_user().username)
+
+print("End test")

hw/.allspice/utils/requirements.txt

@@ -0,0 +1,2 @@
+py-allspice~=3.0
+rich~=13.0

hw/.allspice/workflows/02-Running-common-Actions.yml

@@ -0,0 +1,47 @@
+# AllSpice Running common Actions workflow
+# Action triggers on push and issues
+# Action runs "generate-bom-altium" action
+# .allspice/workflows/generate_bom.yml
+name: Generate BOM
+on:
+  push:
+  issues:
+    types: [opened, closed, reopened]
+
+jobs:
+  Generate_BOM:
+    runs-on: ubuntu-latest
+    steps:
+     # Checkout is only needed if columns.json is committed in your Altium project repo.
+      - name: Checkout
+        uses: actions/checkout@v3
+
+      - name: Generate BOM
+        uses: https://hub.allspice.io/Actions/generate-bom@v0.3
+        with:
+          # The path to the project file in your repo (.PrjPcb for Altium, .DSN for OrCad).
+          source_path: Archimajor.PrjPcb
+          # [optional] A path to a JSON file mapping columns to the component attributes
+          # they are from. This file must be provided.
+          # Default: 'columns.json'
+          columns: .allspice/columns.json
+          # [optional] The path to the output file that will be generated.
+          # Default: 'bom.csv'
+          output_file_name: bom.csv
+          # [optional] A comma-separated list of columns to group the BOM by. If empty
+          # or not present, the BOM will be flat.
+          # Default: ''
+          group_by: 'Part Number'
+          # [optional] The variant of the project to generate the BOM for. If empty
+          # or not present, the BOM will be generated for the default variant.
+          # Default: ''
+          variant: ''          
+      # Print bom.csv to terminal
+      - name: Show BOM
+        run: cat bom.csv
+
+      - name: Upload file as artifact
+        uses: actions/upload-artifact@v3
+        with:
+          name: BOM.csv
+          path: bom.csv

hw/.allspice/workflows/03-Python-py-allspice.yml

@@ -0,0 +1,54 @@
+
+# Python-py-allspice demo repository
+# This workflow demonstrates how to use Python and py-allspice to interact with the AllSpice API
+# AllSpice Actions documentation: https://learn.allspice.io/docs/actions-cicd
+name: Python-py-allspice
+on: 
+  push:
+  issues:
+    types: [opened, closed, reopened]
+
+jobs:
+  py-allspice test:
+    runs-on: ubuntu-latest
+    steps:
+      # Check out repository code
+      - name: "[📚->🖥️] Check out repository code"
+        uses: actions/checkout@v3
+
+      - name: "[🔎->📂] List files in repo 🔎"
+        run: |
+          ls -la ${{ github.workspace }}
+
+      # Installs python requirements from the requirements.txt file
+      - name: "[🤼->🖥️] Install python requirements"
+        run: pip install -r .allspice/utils/requirements.txt
+
+      # Call a python script from the .allspice/utils directory
+      - name: "[🏃->🐍] Run .allspice/utils/hello-world.py 🔎"
+        run: python .allspice/utils/hello-world.py
+
+      # Run the py-allspice self-test script, this will ping the server and verify the API is working
+      # Parameters: ${github.server_url} and ${github.token} are automatic Workflow variables and are used to authenticate the AllSpice API
+      - name: "[🔑->🕸️] Test AllSpice API with py-allspice 🔎"
+        run: python .allspice/utils/py-allspice-BIST.py --allspice_hub_url ${{ github.server_url }}  --allspice_token ${{ github.token }}
+                          
+      # Generate a netlist from Altium .PcbDoc file
+      # Run the generate_netlist.py script from the .allspice/utils directory
+      - name: Generate Netlist
+        run: |
+          echo -e "repo ${{ github.repository }}"
+          ALLSPICE_AUTH_TOKEN=${{ github.token }} python .allspice/utils/generate_netlist.py "${{ github.repository }}" "Archimajor.PcbDoc" --allspice_hub_url "${{ github.server_url }}" --output_file Archimajor.pcbdoc.netlist.txt                      
+      
+    
+      # Print the netlist file to the terminal
+      - name: Show Netlist 🔎
+        run: cat Archimajor.pcbdoc.netlist.txt
+
+      # Archive the netlist file as an artifact file
+      - name: Archive code coverage results
+        uses: actions/upload-artifact@v3
+        with:
+          name: Archimajor.PcbDoc.netlist.txt
+          path: Archimajor.pcbdoc.netlist.txt
+

hw/Archimajor.RUL

@@ -0,0 +1,67 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=OnLayer('Mid1')|SCOPE2EXPRESSION=All|NAME=Internal Positive Layer|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=IRRHXPIM|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=10mil|GENERICCLEARANCE=10mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES=ClearanceObj_Arc-ClearanceObj_Arc:70000;ClearanceObj_Arc-ClearanceObj_Track:70000;ClearanceObj_Arc-ClearanceObj_SMDPad:70000;ClearanceObj_Arc-ClearanceObj_THPad:70000;ClearanceObj_Arc-ClearanceObj_Via:70000;ClearanceObj_Track-ClearanceObj_Track:70000;ClearanceObj_Track-ClearanceObj_SMDPad:70000;ClearanceObj_Track-ClearanceObj_THPad:70000;ClearanceObj_Track-ClearanceObj_Via:70000;ClearanceObj_SMDPad-ClearanceObj_SMDPad:70000;ClearanceObj_SMDPad-ClearanceObj_THPad:70000;ClearanceObj_SMDPad-ClearanceObj_Via:70000;ClearanceObj_THPad-ClearanceObj_THPad:70000;ClearanceObj_THPad-ClearanceObj_Via:70000;ClearanceObj_Via-ClearanceObj_Via:70000¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InPolygon|SCOPE2EXPRESSION=All|NAME=Polygon|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=UUTBXGTA|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=8mil|GENERICCLEARANCE=8mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES=ClearanceObj_Fill-ClearanceObj_Fill:100000;ClearanceObj_Fill-ClearanceObj_Poly:100000;ClearanceObj_Fill-ClearanceObj_Region:100000;ClearanceObj_Poly-ClearanceObj_Poly:100000;ClearanceObj_Poly-ClearanceObj_Region:100000;ClearanceObj_Region-ClearanceObj_Region:100000¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InPolygon and InNetClass('PWR_INPUT')|SCOPE2EXPRESSION=All|NAME=Clearance_PWR_INPUT_POLYGONS|ENABLED=FALSE|PRIORITY=3|COMMENT= |UNIQUEID=BWXFTLNA|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=10mil|GENERICCLEARANCE=10mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES=ClearanceObj_Arc-ClearanceObj_Hole:0;ClearanceObj_Track-ClearanceObj_Hole:0;ClearanceObj_SMDPad-ClearanceObj_Hole:0;ClearanceObj_THPad-ClearanceObj_Hole:0;ClearanceObj_Via-ClearanceObj_Hole:0;ClearanceObj_Fill-ClearanceObj_Hole:0;ClearanceObj_Poly-ClearanceObj_Hole:0;ClearanceObj_Region-ClearanceObj_Hole:0;ClearanceObj_Text-ClearanceObj_Hole:0¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Clearance|ENABLED=TRUE|PRIORITY=4|COMMENT= |UNIQUEID=MQBIHWCT|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=8mil|GENERICCLEARANCE=8mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES= ¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Width|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InNet(UMCU_N) Or InNet(UMCU_P) Or InNet('NetD27_1') Or InNet('NetD27_3') Or InNet('NetD27_4') Or InNet('NetD27_6') Or InNet('NetL5_4') Or InNet('NetL5_1')  Or InNet('UD_P') Or InNet('UD_N') Or InNet('NetR42_1') Or InNet('UMCU_N') OR InNet('UMCU_P') Or InNet('NetR48_1')|SCOPE2EXPRESSION=All|NAME=Width_USB|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=UXSBYLPY|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=8mil|MINLIMIT=6mil|PREFEREDWIDTH=8mil|TOPLAYER_MAXWIDTH=6mil|TOPLAYER_PREFWIDTH=6mil|MIDLAYER1_MINWIDTH=8mil|MIDLAYER2_MINWIDTH=8mil|MIDLAYER3_MINWIDTH=8mil|MIDLAYER4_MINWIDTH=8mil|MIDLAYER5_MINWIDTH=8mil|MIDLAYER6_MINWIDTH=8mil|MIDLAYER7_MINWIDTH=8mil|MIDLAYER8_MINWIDTH=8mil|MIDLAYER9_MINWIDTH=8mil|MIDLAYER10_MINWIDTH=8mil|MIDLAYER11_MINWIDTH=8mil|MIDLAYER12_MINWIDTH=8mil|MIDLAYER13_MINWIDTH=8mil|MIDLAYER14_MINWIDTH=8mil|MIDLAYER15_MINWIDTH=8mil|MIDLAYER16_MINWIDTH=8mil|MIDLAYER17_MINWIDTH=8mil|MIDLAYER18_MINWIDTH=8mil|MIDLAYER19_MINWIDTH=8mil|MIDLAYER20_MINWIDTH=8mil|MIDLAYER21_MINWIDTH=8mil|MIDLAYER22_MINWIDTH=8mil|MIDLAYER23_MINWIDTH=8mil|MIDLAYER24_MINWIDTH=8mil|MIDLAYER25_MINWIDTH=8mil|MIDLAYER26_MINWIDTH=8mil|MIDLAYER27_MINWIDTH=8mil|MIDLAYER28_MINWIDTH=8mil|MIDLAYER29_MINWIDTH=8mil|MIDLAYER30_MINWIDTH=8mil|BOTTOMLAYER_MAXWIDTH=6mil|BOTTOMLAYER_PREFWIDTH=6mil|MINIMP=50.000000|MAXIMP=50.000000|FAVIMP=50.000000¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Width|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Width|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=FRUTRIRB|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=380mil|MINLIMIT=6mil|PREFEREDWIDTH=8mil|TOPLAYER_MAXWIDTH=200mil|MIDLAYER1_MAXWIDTH=200mil|MIDLAYER2_MAXWIDTH=200mil|MIDLAYER3_MAXWIDTH=50mil|MIDLAYER4_MAXWIDTH=50mil|MIDLAYER5_MAXWIDTH=50mil|MIDLAYER6_MAXWIDTH=50mil|MIDLAYER7_MAXWIDTH=50mil|MIDLAYER8_MAXWIDTH=50mil|MIDLAYER9_MAXWIDTH=50mil|MIDLAYER10_MAXWIDTH=50mil|MIDLAYER11_MAXWIDTH=50mil|MIDLAYER12_MAXWIDTH=50mil|MIDLAYER13_MAXWIDTH=50mil|MIDLAYER14_MAXWIDTH=50mil|MIDLAYER15_MAXWIDTH=50mil|MIDLAYER16_MAXWIDTH=50mil|MIDLAYER17_MAXWIDTH=50mil|MIDLAYER18_MAXWIDTH=50mil|MIDLAYER19_MAXWIDTH=50mil|MIDLAYER20_MAXWIDTH=50mil|MIDLAYER21_MAXWIDTH=50mil|MIDLAYER22_MAXWIDTH=50mil|MIDLAYER23_MAXWIDTH=50mil|MIDLAYER24_MAXWIDTH=50mil|MIDLAYER25_MAXWIDTH=50mil|MIDLAYER26_MAXWIDTH=50mil|MIDLAYER27_MAXWIDTH=50mil|MIDLAYER28_MAXWIDTH=50mil|MIDLAYER29_MAXWIDTH=50mil|MIDLAYER30_MAXWIDTH=50mil|MINIMP=50.000000|MAXIMP=50.000000|FAVIMP=50.000000¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InComponent('J3')|SCOPE2EXPRESSION=All|NAME=Do Not Connect|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=QMVODAUD|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=NoConnect|RELIEFEXPANSION=20mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=10mil|RELIEFAIRGAP=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsVia|SCOPE2EXPRESSION=All|NAME=PlaneConnect_Via|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=YNGNVDLB|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Direct|RELIEFEXPANSION=35mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=50mil|RELIEFAIRGAP=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PlaneConnect|ENABLED=TRUE|PRIORITY=3|COMMENT= |UNIQUEID=AVBFEXGG|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Relief|RELIEFEXPANSION=12mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=14mil|RELIEFAIRGAP=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingTopology|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingTopology|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=HHJGCLJI|DEFINEDBYLOGICALDOCUMENT=FALSE|TOPOLOGY=Shortest¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingPriority|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingPriority|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=CKCJHDKN|DEFINEDBYLOGICALDOCUMENT=FALSE|ROUTINGPRIORITY=0¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingLayers|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingLayers|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=OWGQVBJE|DEFINEDBYLOGICALDOCUMENT=FALSE|TOP LAYER_V5=TRUE|MID LAYER 1_V5=TRUE|MID LAYER 2_V5=TRUE|MID LAYER 3_V5=TRUE|MID LAYER 4_V5=TRUE|MID LAYER 5_V5=TRUE|MID LAYER 6_V5=TRUE|MID LAYER 7_V5=TRUE|MID LAYER 8_V5=TRUE|MID LAYER 9_V5=TRUE|MID LAYER 10_V5=TRUE|MID LAYER 11_V5=TRUE|MID LAYER 12_V5=TRUE|MID LAYER 13_V5=TRUE|MID LAYER 14_V5=TRUE|MID LAYER 15_V5=TRUE|MID LAYER 16_V5=TRUE|MID LAYER 17_V5=TRUE|MID LAYER 18_V5=TRUE|MID LAYER 19_V5=TRUE|MID LAYER 20_V5=TRUE|MID LAYER 21_V5=TRUE|MID LAYER 22_V5=TRUE|MID LAYER 23_V5=TRUE|MID LAYER 24_V5=TRUE|MID LAYER 25_V5=TRUE|MID LAYER 26_V5=TRUE|MID LAYER 27_V5=TRUE|MID LAYER 28_V5=TRUE|MID LAYER 29_V5=TRUE|MID LAYER 30_V5=TRUE|BOTTOM LAYER_V5=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingCorners|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingCorners|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=XGRUNROO|DEFINEDBYLOGICALDOCUMENT=FALSE|CORNERSTYLE=45-Degree|MINSETBACK=100mil|MAXSETBACK=100mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingVias|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=HoleSize < '15'|SCOPE2EXPRESSION=All|NAME=RoutingVias_<15mil|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=IXPAORBA|DEFINEDBYLOGICALDOCUMENT=FALSE|HOLEWIDTH=15mil|WIDTH=30mil|VIASTYLE=Through Hole|MINHOLEWIDTH=10mil|MINWIDTH=22mil|MAXHOLEWIDTH=15mil|MAXWIDTH=30mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingVias|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingVias|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=HFQDTFAH|DEFINEDBYLOGICALDOCUMENT=FALSE|HOLEWIDTH=15mil|WIDTH=28mil|VIASTYLE=Through Hole|MINHOLEWIDTH=10mil|MINWIDTH=28mil|MAXHOLEWIDTH=50mil|MAXWIDTH=70mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PlaneClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=CKQOKLCO|DEFINEDBYLOGICALDOCUMENT=FALSE|CLEARANCE=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsVia|SCOPE2EXPRESSION=All|NAME=Via SolderMask|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=FBKQRWWL|DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=-15mil|ISTENTINGTOP=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Global SolderMaskExpansion|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=SJDEOFNJ|DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=2mil|ISTENTINGTOP=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PasteMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PasteMaskExpansion|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=YNEIKKER|DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=-1mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ShortCircuit|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=ShortCircuit|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=CDXDWPFB|DEFINEDBYLOGICALDOCUMENT=FALSE|ALLOWED=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=UnRoutedNet|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=UnRoutedNet|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=LCRMXNQO|DEFINEDBYLOGICALDOCUMENT=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MinimumAnnularRing|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=MinimumAnnularRing|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=QKOGCNCD|DEFINEDBYLOGICALDOCUMENT=FALSE|MINIMUMRING=6mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsVia|SCOPE2EXPRESSION=All|NAME=Vias|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=QWTOLSWJ|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Direct|RELIEFCONDUCTORWIDTH=10mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InComponent('F1') or InComponent('F2') or InComponent('F3') or InComponent('J3')|SCOPE2EXPRESSION=OnLayer('Mid1')|NAME=Internal No Connect|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=JUFUMKAH|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=NoConnect|RELIEFCONDUCTORWIDTH=10mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsNamedPolygon('24milConnect')|SCOPE2EXPRESSION=All|NAME=24mil Connect|ENABLED=TRUE|PRIORITY=3|COMMENT= |UNIQUEID=RQXWPWAK|DEFINEDBYLOGICALDOCUMENT=FALSE|THPAD.CONNECTSTYLE=Relief|THPAD.RELIEFCONDUCTORWIDTH=24mil|THPAD.RELIEFENTRIES=4|THPAD.POLYGONRELIEFANGLE=90 Angle|THPAD.AIRGAPWIDTH=10mil|SMDPAD.CONNECTSTYLE=Relief|SMDPAD.RELIEFCONDUCTORWIDTH=12mil|SMDPAD.RELIEFENTRIES=4|SMDPAD.POLYGONRELIEFANGLE=90 Angle|SMDPAD.AIRGAPWIDTH=10mil|VIA.CONNECTSTYLE=Relief|VIA.RELIEFCONDUCTORWIDTH=12mil|VIA.RELIEFENTRIES=4|VIA.POLYGONRELIEFANGLE=90 Angle|VIA.AIRGAPWIDTH=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsNamedPolygon('Connect')|SCOPE2EXPRESSION=All|NAME=12mil Connect|ENABLED=TRUE|PRIORITY=4|COMMENT= |UNIQUEID=URROECRP|DEFINEDBYLOGICALDOCUMENT=FALSE|THPAD.CONNECTSTYLE=Relief|THPAD.RELIEFCONDUCTORWIDTH=24mil|THPAD.RELIEFENTRIES=4|THPAD.POLYGONRELIEFANGLE=90 Angle|THPAD.AIRGAPWIDTH=10mil|SMDPAD.CONNECTSTYLE=Relief|SMDPAD.RELIEFCONDUCTORWIDTH=12mil|SMDPAD.RELIEFENTRIES=4|SMDPAD.POLYGONRELIEFANGLE=90 Angle|SMDPAD.AIRGAPWIDTH=10mil|VIA.CONNECTSTYLE=Relief|VIA.RELIEFCONDUCTORWIDTH=12mil|VIA.RELIEFENTRIES=4|VIA.POLYGONRELIEFANGLE=90 Angle|VIA.AIRGAPWIDTH=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InComponent('F1') or InComponent('F2') or InComponent('F3') or InComponent('J3')|SCOPE2EXPRESSION=OnLayer('Top Layer')|NAME=Top 12mil|ENABLED=TRUE|PRIORITY=5|COMMENT= |UNIQUEID=XFQLHFJB|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Relief|RELIEFCONDUCTORWIDTH=12mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InComponent('J3')|SCOPE2EXPRESSION=OnLayer('Bottom Layer')|NAME=Bottom 50mil|ENABLED=TRUE|PRIORITY=6|COMMENT= |UNIQUEID=VDUQSGWW|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Relief|RELIEFCONDUCTORWIDTH=50mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InComponent('F3') or InComponent('F2') or InComponent('F3')|SCOPE2EXPRESSION=OnLayer('Bottom Layer')|NAME=Bottom Fuses|ENABLED=TRUE|PRIORITY=7|COMMENT= |UNIQUEID=WGQUEIYY|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Direct|RELIEFCONDUCTORWIDTH=50mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=10mil¶
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+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Fanout_Default|ENABLED=TRUE|PRIORITY=5|COMMENT=Fanout_Default (Default Rule)|UNIQUEID=SSGIRGKT|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Height|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Height|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=FUSFIQLH|DEFINEDBYLOGICALDOCUMENT=FALSE|MINHEIGHT=0mil|MAXHEIGHT=1000mil|PREFHEIGHT=500mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=DiffPairsRouting|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=DiffPairsRouting|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=FXMWEALF|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=10mil|MINLIMIT=7mil|MOSTFREQGAP=10mil|TOPLAYER_PREFGAP=8mil|TOPLAYER_MINWIDTH=7mil|TOPLAYER_MAXWIDTH=15mil|TOPLAYER_PREFWIDTH=8mil|MIDLAYER1_MINGAP=10mil|MIDLAYER1_MINWIDTH=15mil|MIDLAYER1_MAXWIDTH=15mil|MIDLAYER1_PREFWIDTH=15mil|MIDLAYER2_MINGAP=10mil|MIDLAYER2_MINWIDTH=15mil|MIDLAYER2_MAXWIDTH=15mil|MIDLAYER2_PREFWIDTH=15mil|MIDLAYER3_MINGAP=10mil|MIDLAYER3_MINWIDTH=15mil|MIDLAYER3_MAXWIDTH=15mil|MIDLAYER3_PREFWIDTH=15mil|MIDLAYER4_MINGAP=10mil|MIDLAYER4_MINWIDTH=15mil|MIDLAYER4_MAXWIDTH=15mil|MIDLAYER4_PREFWIDTH=15mil|MIDLAYER5_MINGAP=10mil|MIDLAYER5_MINWIDTH=15mil|MIDLAYER5_MAXWIDTH=15mil|MIDLAYER5_PREFWIDTH=15mil|MIDLAYER6_MINGAP=10mil|MIDLAYER6_MINWIDTH=15mil|MIDLAYER6_MAXWIDTH=15mil|MIDLAYER6_PREFWIDTH=15mil|MIDLAYER7_MINGAP=10mil|MIDLAYER7_MINWIDTH=15mil|MIDLAYER7_MAXWIDTH=15mil|MIDLAYER7_PREFWIDTH=15mil|MIDLAYER8_MINGAP=10mil|MIDLAYER8_MINWIDTH=15mil|MIDLAYER8_MAXWIDTH=15mil|MIDLAYER8_PREFWIDTH=15mil|MIDLAYER9_MINGAP=10mil|MIDLAYER9_MINWIDTH=15mil|MIDLAYER9_MAXWIDTH=15mil|MIDLAYER9_PREFWIDTH=15mil|MIDLAYER10_MINGAP=10mil|MIDLAYER10_MINWIDTH=15mil|MIDLAYER10_MAXWIDTH=15mil|MIDLAYER10_PREFWIDTH=15mil|MIDLAYER11_MINGAP=10mil|MIDLAYER11_MINWIDTH=15mil|MIDLAYER11_MAXWIDTH=15mil|MIDLAYER11_PREFWIDTH=15mil|MIDLAYER12_MINGAP=10mil|MIDLAYER12_MINWIDTH=15mil|MIDLAYER12_MAXWIDTH=15mil|MIDLAYER12_PREFWIDTH=15mil|MIDLAYER13_MINGAP=10mil|MIDLAYER13_MINWIDTH=15mil|MIDLAYER13_MAXWIDTH=15mil|MIDLAYER13_PREFWIDTH=15mil|MIDLAYER14_MINGAP=10mil|MIDLAYER14_MINWIDTH=15mil|MIDLAYER14_MAXWIDTH=15mil|MIDLAYER14_PREFWIDTH=15mil|MIDLAYER15_MINGAP=10mil|MIDLAYER15_MINWIDTH=15mil|MIDLAYER15_MAXWIDTH=15mil|MIDLAYER15_PREFWIDTH=15mil|MIDLAYER16_MINGAP=10mil|MIDLAYER16_MINWIDTH=15mil|MIDLAYER16_MAXWIDTH=15mil|MIDLAYER16_PREFWIDTH=15mil|MIDLAYER17_MINGAP=10mil|MIDLAYER17_MINWIDTH=15mil|MIDLAYER17_MAXWIDTH=15mil|MIDLAYER17_PREFWIDTH=15mil|MIDLAYER18_MINGAP=10mil|MIDLAYER18_MINWIDTH=15mil|MIDLAYER18_MAXWIDTH=15mil|MIDLAYER18_PREFWIDTH=15mil|MIDLAYER19_MINGAP=10mil|MIDLAYER19_MINWIDTH=15mil|MIDLAYER19_MAXWIDTH=15mil|MIDLAYER19_PREFWIDTH=15mil|MIDLAYER20_MINGAP=10mil|MIDLAYER20_MINWIDTH=15mil|MIDLAYER20_MAXWIDTH=15mil|MIDLAYER20_PREFWIDTH=15mil|MIDLAYER21_MINGAP=10mil|MIDLAYER21_MINWIDTH=15mil|MIDLAYER21_MAXWIDTH=15mil|MIDLAYER21_PREFWIDTH=15mil|MIDLAYER22_MINGAP=10mil|MIDLAYER22_MINWIDTH=15mil|MIDLAYER22_MAXWIDTH=15mil|MIDLAYER22_PREFWIDTH=15mil|MIDLAYER23_MINGAP=10mil|MIDLAYER23_MINWIDTH=15mil|MIDLAYER23_MAXWIDTH=15mil|MIDLAYER23_PREFWIDTH=15mil|MIDLAYER24_MINGAP=10mil|MIDLAYER24_MINWIDTH=15mil|MIDLAYER24_MAXWIDTH=15mil|MIDLAYER24_PREFWIDTH=15mil|MIDLAYER25_MINGAP=10mil|MIDLAYER25_MINWIDTH=15mil|MIDLAYER25_MAXWIDTH=15mil|MIDLAYER25_PREFWIDTH=15mil|MIDLAYER26_MINGAP=10mil|MIDLAYER26_MINWIDTH=15mil|MIDLAYER26_MAXWIDTH=15mil|MIDLAYER26_PREFWIDTH=15mil|MIDLAYER27_MINGAP=10mil|MIDLAYER27_MINWIDTH=15mil|MIDLAYER27_MAXWIDTH=15mil|MIDLAYER27_PREFWIDTH=15mil|MIDLAYER28_MINGAP=10mil|MIDLAYER28_MINWIDTH=15mil|MIDLAYER28_MAXWIDTH=15mil|MIDLAYER28_PREFWIDTH=15mil|MIDLAYER29_MINGAP=10mil|MIDLAYER29_MINWIDTH=15mil|MIDLAYER29_MAXWIDTH=15mil|MIDLAYER29_PREFWIDTH=15mil|MIDLAYER30_MINGAP=10mil|MIDLAYER30_MINWIDTH=15mil|MIDLAYER30_MAXWIDTH=15mil|MIDLAYER30_PREFWIDTH=15mil|BOTTOMLAYER_PREFGAP=8mil|BOTTOMLAYER_MINWIDTH=7mil|BOTTOMLAYER_MAXWIDTH=15mil|BOTTOMLAYER_PREFWIDTH=8mil|MAXUNCOUPLEDLENGTH=200mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=HoleToHoleClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=HoleToHoleClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=QOBCONRH|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=10mil|ALLOWSTACKEDMICROVIAS=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MinimumSolderMaskSliver|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=MinimumSolderMaskSliver|ENABLED=FALSE|PRIORITY=1|COMMENT= |UNIQUEID=MVJMPEOO|DEFINEDBYLOGICALDOCUMENT=FALSE|MINSOLDERMASKWIDTH=4mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSolderMaskClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsPad|SCOPE2EXPRESSION=All|NAME=SilkscreenOverComponentPads|ENABLED=FALSE|PRIORITY=1|COMMENT= |UNIQUEID=OKWEWTXU|DEFINEDBYLOGICALDOCUMENT=FALSE|MINSILKSCREENTOMASKGAP=10mil|CLEARANCETOEXPOSEDCOPPER=TRUE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSilkClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SilkToSilkClearance|ENABLED=FALSE|PRIORITY=1|COMMENT= |UNIQUEID=ADFJYLCH|DEFINEDBYLOGICALDOCUMENT=FALSE|SILKTOSILKCLEARANCE=10mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=NetAntennae|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=NetAntennae|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=TEAJUGGR|DEFINEDBYLOGICALDOCUMENT=FALSE|NETANTENNAETOLERANCE=0mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestpoint|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestpoint|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=KNPRDARH|DEFINEDBYLOGICALDOCUMENT=FALSE|TESTPOINTUNDERCOMPONENT=FALSE|MINSIZE=40mil|MAXSIZE=100mil|PREFEREDSIZE=60mil|MINHOLESIZE=0mil|MAXHOLESIZE=40mil|PREFEREDHOLESIZE=32mil|TESTPOINTGRID=1mil|USEGRID=FALSE|GRIDTOLERANCE=0.01mil|ALLOWSIDETOP=TRUE|ALLOWSIDEBOTTOM=TRUE|MINSPACING=100mil|COMPBODYCLEARANCE=140mil¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestPointUsage|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestPointUsage|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=NNUPNKAY|DEFINEDBYLOGICALDOCUMENT=FALSE|VALID=2¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=UnpouredPolygon|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=UnpouredPolygon|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=AAGUSEHU|DEFINEDBYLOGICALDOCUMENT=FALSE¶
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=BoardOutlineClearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=BoardOutlineClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=MGGOXJHY|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=20mil|GENERICCLEARANCE=20mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES= ¶

hw/Archimajor.csv

@@ -0,0 +1,94 @@
+Description,Designator,Footprint,Quantity,MANUFACTURER,MANUFACTURER #
+
+"CAP CER 0603 100nF 50V 10% X7R","C1, C15, C18, C23A, C23B, C23C, C23D, C36, C47A, C47B, C47C, C47D, C47E, C47F, C47G, C47H, C95, C121A, C121B, C121C, C121D, C121E, C121F, C121G, C121H, C122A, C122B, C122C, C122D, C122E, C122F, C122G, C122H, C199, C202, C203","C0603","36","Kemet","C0603C104K5RACTU"
+"CAP CER 0.1UF 6.3V 10% X5R 0201","C2, C60A, C60B, C60C, C60D, C62A, C62B, C62C, C62D, C67, C78, C91, C100, C105, C106, C149A, C149B, C149C, C149D, C149E, C149F, C149G, C149H, C204, C205, C206, C207, C208, C215, C217","C0201 Large Pads","30","Samsung","CL03A104KQ3NNNC"
+"CAP CER 0402 TBD, CAP CER 0402 22pF 50V 5% C0G","C3, C151","C0402","2","TBD, AVX","TBD, 04025A220JAT2A"
+"CAP CER 47UF 10V X5R 1210","C4, C5","C1210","2","Murata","GRM32ER61A476KE20L"
+"CAP CER 4.7UF 50V X7R 1210","C6, C7, C8","C1210","3","Murata","GRM32ER71H475KA88L"
+"CAP CER 10nF 50V X7R 0402","C12A, C12B, C12C, C12D, C30A, C30B, C30C, C30D, C40, C71, C77, C84, C86, C157, C158, C159, C160, C171, C214, C216","C0402","20","Murata","GRM155R71H103JA88D"
+"1000pF 50V Ceramic Capacitor X7R 0402 (1005 Metric) 0.039"" L x 0.020"" W (1.00mm x 0.50mm)","C13, C17, C35, C94","C0402","4","Murata","GRM155R71H102KA01D"
+"CAP CER 10UF 50V 10% X5R 1206","C14, C16, C38, C93","C1206","4","Murata","490-10756-2-ND"
+"CAP CER 0402 1uF 6.3V 10% X5R","C24, C34","C0402","2","Murata","GRM155R60J105KE19D"
+"CAP ALUM 100UF 35V 20% SMD","C25, C210","CAP-ELEC-063063077","2","Nichicon","UWT1V101MCL1GS"
+"CAP CER 0402 100nF 16V 10% X7R","C26, C28, C29, C33, C39, C45, C46, C51, C52, C54, C56, C63, C66, C68, C69, C73, C76, C81, C82, C92, C103, C155, C156, C161, C164, C165, C166, C167, C169, C200, C201, C212, C213","C0402","33","Murata","GRM155R71C104KA88D"
+"Capacitor Non Polarized","C27, C50, C153, C154, C209, C211","C0603","6","","DNI-C0603TBD"
+"CAP CER 10UF 6.3V 10% JB 0603","C37, C53, C55, C57, C70, C72","C0603","6","TDK","C1608JB0J106K080AB"
+"CAP CER 3PF 50V NP0 0603","C41, C42","C0603","2","AVX Corporation","06031A3R0BAT2A"
+"CAP CER 0.22UF 50V X7R 0603","C48A, C48B, C48C, C48D, C48E, C48F, C48G, C48H, C59A, C59B, C59C, C59D, C59E, C59F, C59G, C59H, C98A, C98B, C98C, C98D, C98E, C98F, C98G, C98H, C99A, C99B, C99C, C99D, C99E, C99F, C99G, C99H","C0603","32","TDK","CGA3E3X7R1H224K080AB"
+"CAP CER 10PF 50V 5% NP0 0402, 470nF 6.3v C0402 - GRM155R60J474KE19D","C49, C132A, C132B, C132C, C132D, C132E, C132F, C132G, C132H","C0402","9","Samsung, Murata","CL05C100JB5NNNC, GRM155R60J474KE19D"
+"CAP CER 1206 4.7uF 50V 10% X5R","C61A, C61B, C61C, C61D, C61E, C61F, C61G, C61H, C125A, C125B, C125C, C125D, C125E, C125F, C125G, C125H","C1206","16","Kemet","C1206C475K5PACTU"
+"CAP CER 0402 TBD","C64, C74, C75, C79, C83, C85, C87, C88, C89, C90, C101, C102, C104","C0402","13","TBD","TBD"
+"CAP CER 0.022UF 100V X7R 0603","C124A, C124B, C124C, C124D, C124E, C124F, C124G, C124H","C0603","8","Kemet","C0603C223K1RACTU"
+"CAP CER 4.7UF 6.3V X7R 0603","C131A, C131B, C131C, C131D, C131E, C131F, C131G, C131H","C0603","8","Samsung","CL10B475KQ8NQNC"
+"CAP CER 0402 2.2nF 25V C0G","C150","C0402","1","Kemet","C0402C222J3GACTU"
+"CAP ALUM 470UF 20% 50V SMD","C152A, C152B, C152C, C152D, C152E, C152F, C152G, C152H","CAP16x17","8","Nichicon","UCZ1H471MNQ1MS"
+"Capacitor Non Polarized","C198","C0402","1","","DNI-C0402TBD"
+"TVS DIODE 3.3VWM 10.4VC SOD923","D1, D71, D72, D73","SOD923-100X40-2N","4","On Semi","ESD9X3.3ST5G"
+"DIODE SCHOTTKY 40V 5A SMB_DO214AA","D2","SMB_DO-214AA_LRG","1","MCC","SK54B-LTP"
+"DIODE SCHOTTKY 30V 200MA SOD523","D5, D12A, D12B, D12C, D12D, D12E, D12F, D12G, D12H, D19A, D19B, D19C, D19D, D19E, D19F, D19G, D19H, D20A, D20B, D20C, D20D, D20E, D20F, D20G, D20H, D28, D29, D30, D31, D36, D37, D40, D41, D50, D51, D52, D53, D54, D55, D56, D57, D60, D61, D63, D70, D74, D75, D76, D77","SOD523_IPC","49","Diodes Incorporated","BAT54WX-TP"
+"TVS DIODE 24V 38.9V SMA","D21, D22, D43, D78","SMA-SM","4","Bourns Inc","SMAJ24A"
+"LED 0805 Red","D24","LED2012120","1","Dialight","5988110107F"
+"TVS DIODE 3.3VWM 10.4VC SOD923","D44","SOD923-D","1","On Semi","ESD9X3.3ST5G"
+"TVS DIODE 5V 9V SOD923","D45","SOD923-D","1","Toshiba","DF2S6.8FS,L3M"
+"FERRITE BEAD 120 OHM 0603 1LN","FB26, FB27, FB28, FB30","FB0603","4","Samsung","CIS10P121AC"
+"Conn - 3mm Pitch Fixed","J2A, J2B, J2C, J2D, J2E, J2F, J2G, J2H","43045-0412","8","Molex","43045-0412"
+"CONN BARRIER STRIP 10CIRC 0.325""","J3","CON-Barrier-10-8.26mm","1","TE","4DB-P108-10"
+"20021121-00010C4LF","J4","FTSH-105-XX-X-DV","1","Amphenol FCI","20021121-00010C4LF"
+"3 Positions Header, Shrouded Connector 0.100"" (2.54mm) Through Hole Gold - Pin in Paste","J5, J6, J7, J9, J10, J11, J22, J29, J30, J31, J32, J33","70543-02 PIN-IN-PASTE","12","Molex","0705430002"
+"","J8","PN61729","1","Amphenol FCI","61729-0010BLF"
+"CONN HEADER VERT 10POS GOLD","J12, J13, J28","HDR2X5 IDC","3","On Shore","302-S101"
+"Connector 2pos - Pin in Paste","J14, J15","70543-01 PIN-IN-PASTE","2","Molex","0705430001"
+"microSD 0475710001Molex Part","J18","SD_MICRO 475710001","1","Molex","0475710001"
+"Header, 12-Pin, Dual row","J20","HDR2X12","1","Multicomp","2213S-24G"
+"TERM BLOCK 2POS 45DEG 3.5MM PCB","J21A, J21B, J21C, J21D","1864286","4","Phoenix Contact","1864286"
+"Header 3Pin 1Row T-Hole","J24","HDR3X1","1","Multicomp","2211S-03G"
+"FIXED IND 4.7UH 10A 15.5 MOHM","L1","IND_10X10","1","Bourns","SRP1038A-4R7M"
+"Common Mode Chokes Dual 90Ohm 100MHz 330mA 350mOhm DCR SMD","L5","DLW21HN900SQ2L","1","Murata","DLW21HN900SQ2L"
+"Header, 4-Pin, Dual row","P1, P2A, P2B, P2C, P2D, P2E, P2F, P2G, P2H","HDR2X4","9","Multicomp, [NoParam]","2213S-08G, [NoParam]"
+"40V 17 MOHM T6 S08FL DUAL","Q7A, Q7B, Q7C, Q7D, Q7E, Q7F, Q7G, Q7H, Q9A, Q9B, Q9C, Q9D, Q9E, Q9F, Q9G, Q9H, Q10A, Q10B, Q10C, Q10D, Q10E, Q10F, Q10G, Q10H, Q11A, Q11B, Q11C, Q11D, Q11E, Q11F, Q11G, Q11H","SO8FL-Dual (DFN8 5x6, 1.26P Dual Flag)","32","ON Semiconductor","NVMFD5C478NT1G"
+"TRANS NPN 60V 0.2A SOT523","Q8","SOT523 SMALL","1","Diodes Incorporated","MMBT3904T-7-F"
+"","Q12, Q13","NCV8402AD-SOIC8","2","On Semi","NCV8402ADDR2G"
+"RES SMD 10.2K OHM 1% 1/16W 0402","R1","R0402","1","Yageo","RC0402FR-0710K2L"
+"RES 47 OHM 1% 1/16W 0402","R3, R4, R13, R32, R59, R84, R86A, R86B, R86C, R86D, R86E, R86F, R86G, R86H, R88A, R88B, R88C, R88D, R89, R93, R94, R116A, R116B, R116C, R116D, R116E, R116F, R116G, R116H, R163A, R163B, R163C, R163D, R163E, R163F, R163G, R163H, R168A, R168B, R168C, R168D, R168E, R168F, R168G, R168H, R170A, R170B, R170C, R170D, R170E, R170F, R170G, R170H","R0402","53","Vishay Dale","CRCW040247R0FKEDC"
+"RES SMD 1.96K OHM 1% 1/16W 0402","R5","R0402","1","Yageo","RC0402FR-071K96L"
+"RES SMD 37.4K OHM 1% 1/16W 0402","R10","R0402","1","Yageo","RC0402FR-0737K4L"
+"RES SMD 10K OHM 1% 1/16W 0402, RES 0402 1k 63mW 1%","R11, R72, R74, R95, R152, R191, R193","R0402","7","Yageo","RC0402FR-0710KP, RC0402FR-071KL"
+"RES SMD 4.7K OHM 1% 1/16W 0402","R16A, R16B, R16C, R16D, R16E, R16F, R16G, R16H, R18A, R18B, R18C, R18D, R18E, R18F, R18G, R18H","R0402","16","YAGEO","RC0402FR-074K7L"
+"Resistor","R17A, R17B, R17C, R17D, R17E, R17F, R17G, R17H, R60","R0402","9","","DNI-R0402TBD"
+"RES 0402 1k 63mW 1%, RES SMD 1K OHM 1% 1/16W 0402","R19, R23, R34, R36, R40, R41, R71, R76, R79, R102, R108A, R108B, R108C, R108D, R108E, R108F, R108G, R108H, R174, R175, R176, R177, R186, R187, R188, R189, R197, R198","R0402","28","Yageo","RC0402FR-071KL"
+"RES SMD 100K OHM 1% 1/16W 0402","R22, R35, R63, R73, R75, R78, R190, R192","R0402","8","Samsung","RC1005F104CS"
+"RES SMD 24K OHM 1% 1/16W 0402","R26, R154","R0402","2","Visha Dale","CRCW040224K0FKEDC"
+"RES 0402 1M 100mW 5%","R28, R156","R0402","2","Panasonic","ERJ2GEJ105X"
+"RES SMD 100K OHM 1% 1/16W 0402","R31, R37, R38, R51, R58, R158","R0402","6","Samsung","RC1005F104CS"
+"Res Thick Film 0402 24 Ohm 1% 0.063W","R42, R43, R45, R46, R47, R48","R0402","6","Yageo","RC0402FR-0724RL"
+"RES SMD 2.37K OHM 1% 1/16W 0402","R44, R50, R81, R87","R0402","4","Yageo","RC0402FR-072K37L"
+"RES SMD 6.8K OHM 1% 1/16W 0402","R49, R150, R151","R0402","3","Vishay Dale","CRCW04026K80FKED"
+"RES SMD 10K OHM 1% 1/16W 0402, RES SMD 4.7K OHM 1% 1/16W 0402","R56, R62, R64, R65, R66, R67, R68, R69, R70, R80, R85, R97, R100, R101, R119, R155, R171, R182, R183","R0402","19","Yageo","RC0402FR-0710KP, RC0402FR-074K7L"
+"RES SMD 130K OHM 5% 1/16W 0402","R57, R157","R0402","2","Yageo","RC0402JR-07130KL"
+"RES 0402 1M 100mW 5%","R61","R0402TBD","1","Panasonic","ERJ2GEJ105X"
+"RES SMD 100 OHM 1% 1/16W 0402","R98, R99, R109, R114, R120, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R149, R153, R159, R160, R161, R180, R181","R0402","25","Yageo","RC0402FR-07100RL"
+"RES SMD 0.0OHM JUMPER 1/10W 0603","R103","R0603","1","Bourns","CR0603-J/-000ELF"
+"RES SMD 2.2 OHM 5% 1/16W 0402","R107A, R107B, R107C, R107D, R107E, R107F, R107G, R107H","R0402","8","Yageo","RC0402JR-072R2L"
+"RES SMD 10 OHM 1% 1/16W 0402","R110A, R110B, R110C, R110D, R110E, R110F, R110G, R110H, R111A, R111B, R111C, R111D, R111E, R111F, R111G, R111H, R112A, R112B, R112C, R112D, R112E, R112F, R112G, R112H, R113A, R113B, R113C, R113D, R113E, R113F, R113G, R113H, R164A, R164B, R164C, R164D, R164E, R164F, R164G, R164H, R165A, R165B, R165C, R165D, R165E, R165F, R165G, R165H, R166A, R166B, R166C, R166D, R166E, R166F, R166G, R166H, R167A, R167B, R167C, R167D, R167E, R167F, R167G, R167H","R0402","64","Yageo","RC0402FR-0710RL"
+"RES SMD 15K 1% 1/16W 0402","R115","R0402","1","Samsung","RC1005F153CS"
+"RES 0.01 OHM 1% 1/2W 0805","R148","R0805","1","Susumu","KRL1220E-M-R010-F-T5"
+"RES 0.05 OHM 1% 2W 2512","R162A, R162B, R162C, R162D, R162E, R162F, R162G, R162H, R169A, R169B, R169C, R169D, R169E, R169F, R169G, R169H","R2512","16","Stackpole","CSRN2512FK50L0"
+"RES SMD 1.8K OHM 1% 1/16W 0402","R172, R173, R184, R185","R0402","4","Yageo","RC0402FR-071K8L"
+"VARISTOR 6.8V 10A 0201","RV1, RV2, RV3, RV4, RV5A, RV5B, RV5C, RV5D, RV5E, RV5F, RV5G, RV5H, RV6A, RV6B, RV6C, RV6D, RV6E, RV6F, RV6G, RV6H, RV7A, RV7B, RV7C, RV7D, RV7E, RV7F, RV7G, RV7H","C0201 Large Pads","28","TDK","AVRM0603C6R8NT101N"
+"SWTCH Momentary Washable","S1","B3F-31XX","1","TE","1571610-2"
+"SWITCH TACTILE SPST-NO 0.05A 12V","S2","KMR 6 Series","1","C&K","KMR741NG ULC LFS"
+"IC REG BUCK ADJ 5A 8SOPWRPAD","U1","SOIC127P600X170_HS-9L","1","TI","TPS54531DDAR"
+"Quadruple Bus Buffer Gates With 3-State Outputs 14-VQFN -40 to 125","U2","QFN50P350X350X100_RGY_S-PVQFN-N14","1","Texas Instruments","SN74AHCT125RGYR"
+"IC QUAD DIFF COMPARATOR 14 -SOIC","U6, U21","SOT23-5","2","TEXAS INSTRUMENTS","AP331AWG-7"
+"LDO 3.3V 500mA - low ESR Cout","U8","TDFN1616-6LD-PL-1","1","Microchip","MIC5353-3.3YMT-TR"
+"USB Opto Isolator","U9","ADuM4160","1","Analog Devices","ADUM3160BRWZ-RL"
+"Atmel","U11","LQFP144_N","1","Atmel","ATSAM3X8EA-AU"
+"IC FLASH 16M SPI 104MHZ 8SOIC","U12","S25FL216K0PMFI041","1","Adesto","AT25SF161-SSHD-T"
+"IC CONV THERMOCOUPLE 14TSSOP","U13A, U13B, U13C, U13D","TSSOP-14L 65P640X110","4","Maxim","MAX31856MUD"
+"Clock Fanout Buffer (Distribution) IC 1:4  8-XFDFN","U14","XSON50P100X50-8L","1","Nexperia","74AVC9112GTX"
+"IC STEPPER MOTOR DVR TQFP48-EP","U15A, U15B, U15C, U15D, U15E, U15F, U15G, U15H","TQFP48-EP","8","Trinamic","TMC5160-TA"
+"IC BUS BUFF TRI-ST QD 14VQFN","U16, U17","PVQFN14_3.5X3.5","2","TI","SN74LVC125ARGYR"
+"Optoisolator Transistor Output 3750Vrms 1 Channel 4-SO","U18","SO-4","1","TOSHIBA","TLP293(TPL,E"
+"IC COMPARATOR BIDIR 8WSON","U19","WSON8_2X2MM","1","TI","INA381A2IDSGR"
+"IC REG LINEAR 5V 100MA SOT89-3","U20","SOT-89-3","1","ST","L78L05ABUTR"
+"Crystal 12MHz <20>30ppm (Tol) <20>50ppm (Stability) 13pF FUND 50Ohm","X1","CRYS320500","1","CTS","405C35B12M00000"