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Add MCU/HDMI/DRAM connections and power conditioning #4

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RevaReviewa merged 1 commits from develop into main 2023-11-15 20:04:34 +00:00
Conversation 3 Commits 1 Files Changed 1
AllSpiceUser commented 2023-11-15 17:37:22 +00:00
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Resolved Issues

#3 - HDMI connections

Description

Add connections between Micro and (DRAM, FLASH, Power, HDMI, Ethernet

Design Review Checklist

Process

  • Commits in correct branch
  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained

System

  • Power
    • Sufficient power supplied from upstream source
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • I/Os are specified
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review

Components

  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power

Schematics

  • Document
    • Dot on each connection
    • No four-point connections
    • Title block completed for each sheet
    • All components have reference designators and values
    • Multi-part components don't have unplaced symbols
    • Page title present and consistent on all pages if not in title block
    • Symbols identify open collector/drain pins and internal pulled up/down pins
    • Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
    • Components follow preferred reference designator pattern
  • External I/O
    • Filtered for EMI
    • Protected against electrostatic discharge (ESD)
    • Unused inputs terminated
  • Microcontrollers / ICs
    • Predictable or controlled power-up state
      • Reset filtered
    • Sufficient bypass capacitance
    • Oscillators checked for reliable startup
    • Pullups on open-collector pins
    • Logic-low and logic-high voltage levels checked
    • No-connect pins labeled NC
    • Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
    • Check for input voltages applied with power off and CMOS latchup possibilities
    • Check the data sheet errata and apnotes for weird IC behaviors
  • Busses
    • UART/USART TX->RX and RX<-TX
    • I2C SDA and SCL pullup with appropriate value per capacitance
    • Setup, hold, access times for data and address busses
  • Analog
    • Sufficient power rails for analog circuits
    • Amplifiers checked for stability
    • Consider signal rate-of-rise and fall for noise radiation
  • General
    • Sufficient bulk capacitance calculated
    • Polarized components checked
    • Electrolytic/tantalum capacitors checked for no reverse voltage
    • Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
    • Sufficient capacitance on low dropout voltage regulators
    • Sufficient time delays and slew rates for comparators
    • Sufficient common mode input voltage rating on opamps
    • Check pin numbers of all custom-generated parts
    • Check reverse base-emitter current/voltage on bipolar transistors
    • Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
    • Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default
## Resolved Issues <!-- Include any relevant issues closed by this pull request. Use the form "Closes #<number of issue>" --> #3 - HDMI connections ## Description <!-- Include a description for this design review. What is the primary purpose? What will be the status of this design after approval? --> Add connections between Micro and (DRAM, FLASH, Power, HDMI, Ethernet ## Design Review Checklist ### Process - [x] Commits in correct branch - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [ ] Update project README page - [x] Simulations uploaded and outputs explained ### System - [x] Power - [x] Sufficient power supplied from upstream source - [ ] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [ ] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [ ] Testing - [ ] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review ### Components - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power ### Schematics - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [x] Components follow preferred reference designator pattern <!-- Link to spec --> - [x] External I/O - [x] Filtered for EMI - [x] Protected against electrostatic discharge (ESD) - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Predictable or controlled power-up state - [x] Reset filtered - [x] Sufficient bypass capacitance - [x] Oscillators checked for reliable startup - [x] Pullups on open-collector pins - [x] Logic-low and logic-high voltage levels checked - [x] No-connect pins labeled NC - [x] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination - [x] Check for input voltages applied with power off and CMOS latchup possibilities - [x] Check the data sheet errata and apnotes for weird IC behaviors - [x] Busses - [ ] UART/USART TX->RX and RX<-TX - [x] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [x] Setup, hold, access times for data and address busses - [x] Analog - [x] Sufficient power rails for analog circuits - [x] Amplifiers checked for stability - [x] Consider signal rate-of-rise and fall for noise radiation - [x] General - [x] Sufficient bulk capacitance calculated - [x] Polarized components checked - [x] Electrolytic/tantalum capacitors checked for no reverse voltage - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF - [x] Sufficient capacitance on low dropout voltage regulators - [x] Sufficient time delays and slew rates for comparators - [x] Sufficient common mode input voltage rating on opamps - [x] Check pin numbers of all custom-generated parts - [x] Check reverse base-emitter current/voltage on bipolar transistors - [x] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) - [x] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default
AllSpiceUser added the
priority/4 - high
feature
documentation
 labels 2023-11-15 17:37:22 +00:00
AllSpiceUser added 1 commit 2023-11-15 17:37:24 +00:00
AllSpiceUser requested review from RevaReviewa 2023-11-15 17:38:24 +00:00
AllSpiceUser requested review from MikaChanical 2023-11-15 17:38:24 +00:00
MikaChanical approved these changes 2023-11-15 19:39:54 +00:00
MikaChanical left a comment
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Reviewed connectors. So far-so good. I'm adding an issue to add mounting holes in the next release

Reviewed connectors. So far-so good. I'm adding an issue to add mounting holes in the next release
PavelInPurchasing commented 2023-11-15 19:45:39 +00:00
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@daniel it doesn't look like the BOM changed. Can you confirm?

@daniel it doesn't look like the BOM changed. Can you confirm?
daniel commented 2023-11-15 19:46:58 +00:00
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@daniel it doesn't look like the BOM changed. Can you confirm?

@PavelInPurchasing, that is correct. Thank you for checking 🥰

> @daniel it doesn't look like the BOM changed. Can you confirm? @PavelInPurchasing, that is correct. Thank you for checking 🥰
RevaReviewa reviewed 2023-11-15 19:48:30 +00:00
BEAGLEBONEBLK_C3.DSN
RevaReviewa commented 2023-11-15 19:48:30 +00:00
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Can we specify this for the next design review?

!thumbnail[](BEAGLEBONEBLK_C3.DSN){ diff="AllSpice/OrCAD_demo:962648ed9a2e52fcf27a7b9d1d816381b840280d...5ccd015e0792da9806ac88839479257a58293797" pr="4" doc-id="5cc21a46707316d7c09c" diff-visibility="full" variant="default" view-coords="69.8,62.3,91.9,77.2" aspect-ratio="1.554" } Can we specify this for the next design review?
daniel commented 2023-11-15 19:48:59 +00:00
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Can we specify this for the next design review?

@RevaReviewa , that's a good idea. I'll make an issue.

> !thumbnail[](BEAGLEBONEBLK_C3.DSN){ diff="AllSpice/OrCAD_demo:962648ed9a2e52fcf27a7b9d1d816381b840280d...5ccd015e0792da9806ac88839479257a58293797" pr="4" doc-id="5cc21a46707316d7c09c" diff-visibility="full" variant="default" view-coords="69.8,62.3,91.9,77.2" aspect-ratio="1.554" } Can we specify this for the next design review? @RevaReviewa , that's a good idea. I'll make an issue.
RevaReviewa reviewed 2023-11-15 19:59:30 +00:00
BEAGLEBONEBLK_C3.DSN
RevaReviewa commented 2023-11-15 19:59:30 +00:00
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@daniel , I'm seeing a few different bypass caps with the same/similar values. Can we condense down to a smaller number of unique capacitors?

!thumbnail[](BEAGLEBONEBLK_C3.DSN){ diff="AllSpice/OrCAD_demo:962648ed9a2e52fcf27a7b9d1d816381b840280d...5ccd015e0792da9806ac88839479257a58293797" pr="4" doc-id="c1039357662fc5dc4b38" diff-visibility="full" variant="default" view-coords="2.0,7.0,30.5,21.8" aspect-ratio="1.554" } @daniel , I'm seeing a few different bypass caps with the same/similar values. Can we condense down to a smaller number of unique capacitors?
RevaReviewa requested changes 2023-11-15 20:00:10 +00:00
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Please reduce number of unique capacitors

Please reduce number of unique capacitors
daniel commented 2023-11-15 20:01:58 +00:00
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Please reduce number of unique capacitors

@RevaReviewa , I created #7 to capture this. Since this is a preliminary design review, can we reduce on the next design review?

> Please reduce number of unique capacitors @RevaReviewa , I created #7 to capture this. Since this is a preliminary design review, can we reduce on the next design review?
daniel requested review from RevaReviewa 2023-11-15 20:03:47 +00:00
RevaReviewa approved these changes 2023-11-15 20:04:25 +00:00
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Approving, pending #7 completed in next design review

Approving, pending #7 completed in next design review
RevaReviewa merged commit ee8ece06fd into main 2023-11-15 20:04:34 +00:00
daniel reviewed 2023-11-29 20:41:46 +00:00
daniel reviewed 2023-11-29 20:54:14 +00:00
AllSpiceUser reviewed 2024-01-18 18:13:54 +00:00
BEAGLEBONEBLK_C3.DSN
AllSpiceUser commented 2024-01-18 18:13:54 +00:00
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@RevaReviewa , can you take a look at this

!thumbnail[](BEAGLEBONEBLK_C3.DSN){ diff="AllSpice-demos/OrCAD-demo:962648ed9a2e52fcf27a7b9d1d816381b840280d...5ccd015e0792da9806ac88839479257a58293797" pr="4" doc-id="e61c3a5c70ad3c0d0414" diff-visibility="full" variant="default" view-coords="15.0,27.2,37.0,48.1" aspect-ratio="1.554" } @RevaReviewa , can you take a look at this
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