Demo Altium repository. Forked from https://github.com/ultimachine/Archimajor
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  1. ---
  2. name: "AllSpice Pull Request Template"
  3. about: "Optional description"
  4. ---
  5. *This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!*
  6. ## Resolved Issues
  7. <!-- Include any relevant issues closed by this pull request. Use the form "Closes #<number of issue>" -->
  8. ...
  9. ## Description
  10. <!-- Include a description for this design review. What is the primary purpose? What will be the status of this design after approval? -->
  11. ...
  12. ## Design Review Checklist
  13. ### Process
  14. - [ ] Schematic and PCB file names follow standard
  15. - [ ] Export necessary review files (3D model, BOM, etc.)
  16. - [ ] Update relevant system architecture documents
  17. - [ ] Update project README page
  18. - [ ] Simulations uploaded and outputs explained
  19. ### System
  20. - [ ] Power
  21. - [ ] Sufficient power supplied from upstream source
  22. - [ ] Supply rated for necessary country specifications
  23. - [ ] Estimated total worst-case power supply draw
  24. - [ ] Connectors
  25. - [ ] I/Os are specified
  26. - [ ] Sufficient Current and Voltage rating
  27. - [ ] Mating connectors have matching pinout
  28. - [ ] Same contact material specified for mating connectors
  29. - [ ] Testing
  30. - [ ] Test procedure written
  31. - [ ] Environmental
  32. - [ ] Specified min/max operating temperature
  33. - [ ] Specified min/max storage temperature
  34. - [ ] Specified min/max humidity
  35. - [ ] ROHS compliance requirement review
  36. ### Components
  37. - [ ] Unpopulated components are denoted DNI
  38. - [ ] Components meet environmental specifications
  39. - [ ] All components have quantity, reference designator and description
  40. - [ ] Suggested and alternate manufacturers listed
  41. - [ ] Price and stock checked for each component
  42. - [ ] Component derating
  43. - [ ] Voltage
  44. - [ ] Current
  45. - [ ] Power at worst-case operating temperature
  46. - [ ] Temperature at worst-case power
  47. ### Schematics
  48. - [ ] Document
  49. - [ ] Dot on each connection
  50. - [ ] No four-point connections
  51. - [ ] Title block completed for each sheet
  52. - [ ] All components have reference designators and values
  53. - [ ] Multi-part components don't have unplaced symbols
  54. - [ ] Page title present and consistent on all pages if not in title block
  55. - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins
  56. - [ ] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
  57. - [ ] Components follow preferred reference designator pattern <!-- Link to spec -->
  58. - [ ] External I/O
  59. - [ ] Filtered for EMI
  60. - [ ] Protected against electrostatic discharge (ESD)
  61. - [ ] Unused inputs terminated
  62. - [ ] Microcontrollers / ICs
  63. - [ ] Predictable or controlled power-up state
  64. - [ ] Reset filtered
  65. - [ ] Sufficient bypass capacitance
  66. - [ ] Oscillators checked for reliable startup
  67. - [ ] Pullups on open-collector pins
  68. - [ ] Logic-low and logic-high voltage levels checked
  69. - [ ] No-connect pins labeled NC
  70. - [ ] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
  71. - [ ] Check for input voltages applied with power off and CMOS latchup possibilities
  72. - [ ] Check the data sheet errata and apnotes for weird IC behaviors
  73. - [ ] Busses
  74. - [ ] UART/USART TX->RX and RX<-TX
  75. - [ ] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf)
  76. - [ ] Setup, hold, access times for data and address busses
  77. - [ ] Analog
  78. - [ ] Sufficient power rails for analog circuits
  79. - [ ] Amplifiers checked for stability
  80. - [ ] Consider signal rate-of-rise and fall for noise radiation
  81. - [ ] General
  82. - [ ] Sufficient bulk capacitance calculated
  83. - [ ] Polarized components checked
  84. - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage
  85. - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
  86. - [ ] Sufficient capacitance on low dropout voltage regulators
  87. - [ ] Sufficient time delays and slew rates for comparators
  88. - [ ] Sufficient common mode input voltage rating on opamps
  89. - [ ] Check pin numbers of all custom-generated parts
  90. - [ ] Check reverse base-emitter current/voltage on bipolar transistors
  91. - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`)
  92. - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default
  93. ### PCB
  94. - [ ] Manufacturing
  95. - [ ] PCB manufacturing requirements noted on `fab` layer
  96. - [ ] Plating specified
  97. - [ ] Plating material
  98. - [ ] Plating thickness
  99. - [ ] Layer stack-up specified
  100. - [ ] Minimum trace/space specified
  101. - [ ] Minimum hole size specified
  102. - [ ] PCB color specified
  103. - [ ] Silkscreen color specified
  104. - [ ] Controlled impedance specified
  105. - [ ] Blind or buried vias specified
  106. - [ ] Panelization specified
  107. - [ ] External routing specified (ex. v-groove vs route)
  108. - [ ] Drill table generated
  109. - [ ] All specifications exceed manufacturing tolerance
  110. - [ ] Space between power planes minimized
  111. - [ ] Solder paste openings proper size
  112. - [ ] Fiducials placed if necessary
  113. - [ ] Footprints
  114. - [ ] Pin 1 marked in a consistent manner
  115. - [ ] Component polarity marked
  116. - [ ] Diodes, LEDs
  117. - [ ] Electrolytic, tantalum capacitors
  118. - [ ] Keyed components like connectors
  119. - [ ] Footprint dimensions cross-checked with datasheet recommendation
  120. - [ ] Sufficient thermal pads on high-power components or nets
  121. - [ ] Placement
  122. - [ ] Jumpers accessible
  123. - [ ] Debug connectors accessible
  124. - [ ] Filter resistors closer to source
  125. - [ ] Termination resistors close to target
  126. - [ ] Small loop path on switch-mode power supplies
  127. - [ ] Bypass capacitors close to ICs
  128. - [ ] Bypass capacitors close to connectors
  129. - [ ] Drivers / receivers close to connectors
  130. - [ ] SMT components on top side, through-hole components on bottom side if possible
  131. - [ ] Clearance
  132. - [ ] Keep-out areas honored
  133. - [ ] Around mounting holes
  134. - [ ] For programming tools
  135. - [ ] For assembly tools (wrenches, screwdrivers etc.)
  136. - [ ] For connectors
  137. - [ ] Trace-to-trace clearance based upon voltage rating
  138. - [ ] Component size based upon voltage rating
  139. - [ ] Keep components away from board edge
  140. - [ ] Mechanical
  141. - [ ] CAD file uploaded
  142. - [ ] Clearance above connectors
  143. - [ ] Clearance below through-hole components
  144. - [ ] Enough space for the minimum bending radius of the wire harness
  145. - [ ] Mounting holes electrically isolated if necessary
  146. - [ ] Mounting holes have via stitching
  147. - [ ] Hole diameters leave margin for plating
  148. - [ ] Board outline defined
  149. - [ ] Mechanical enclosure defined
  150. - [ ] Internal corners are rounded and can be milled
  151. - [ ] Electrical
  152. - [ ] All traces are routed
  153. - [ ] Analog and digital commons joined at only one point
  154. - [ ] ERC passes
  155. - [ ] Isolation barriers are large enough
  156. - [ ] Signal integrity
  157. - [ ] Gaps in ground planes checked and minimized
  158. - [ ] High-speed signals avoid gaps in ground planes
  159. - [ ] Stubs minimized for high-speed signals
  160. - [ ] Differential pair spacing based upon impedance matching
  161. - [ ] Transmission lines terminated with an appropriate impedance
  162. - [ ] Crystal connections kept short
  163. - [ ] Guard ring around crystals
  164. - [ ] Traces avoided under sensitive components
  165. - [ ] Traces avoided under noisy components
  166. - [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
  167. - [ ] Option for a shielding can over sensitive circuitry e.g. RF?
  168. - [ ] Copper pour
  169. - [ ] All planes have been poured
  170. - [ ] Planes and pours checked for high-impedance paths
  171. - [ ] No pour between adjacent pins on ICs
  172. - [ ] Traces
  173. - [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more)
  174. - [ ] Trace widths sufficient for the current draw and max heating
  175. - [ ] No connections between adjacent pins on ICs
  176. - [ ] Vias for internal power traces sufficiently large
  177. - [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
  178. - [ ] Thermal
  179. - [ ] Temperature sensitive components placed away from hot components
  180. - [ ] Thermal vias in thermal pads
  181. - [ ] Testing
  182. - [ ] Test points on PCBs for critical circuits, hard to reach nets
  183. - [ ] Ground connection points close to analog test points
  184. - [ ] Silk screen
  185. - [ ] Notes and documentation
  186. - [ ] Updated revision number
  187. - [ ] Updated date
  188. - [ ] Blank space designated for a serial / assembly number
  189. - [ ] No silk screen over pads / vias
  190. - [ ] Text is readable from at most two directions
  191. - [ ] Silk screen size / font will legible after printing
  192. - [ ] Connector pin-outs labeled
  193. - [ ] Fuse size and type marked on PCB
  194. - [ ] Functional groups marked
  195. - [ ] Functionality labeled
  196. - [ ] Test points
  197. - [ ] LEDs
  198. - [ ] Buttons
  199. - [ ] Connectors/terminals
  200. - [ ] Jumpers/fuses
  201. <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->