Replaced Z1 and Z2 with SMD #10
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allspice-admin
commented 2023-10-23 16:51:00 +00:00
Review
!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice/SingleBoardComputer:a543d861d15983c59209cc625f0323032248ab68...fd403cb83b124bd5df7b3ab76f0425ec6a0b175c" pr="10" layers="82,81,63,61,60,59,58,57,33,37,1,32,34" diff-visibility="full" variant="default" view-coords="39.9,34.1,48.0,37.8" aspect-ratio="1.404" } @valentina Is this connector correctly positioned?
@ -376,18 +376,23 @@
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"rule_severities": {
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"bus_to_net_conflict": "error",
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"conflicting_netclasses": "error",
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"different_unit_footprint": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"lib_symbol_issues": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_unit": "warning",
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"multiple_net_names": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_connected": "warning",
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@ -397,6 +402,7 @@
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"pin_to_pin": "warning",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"similar_labels": "warning",
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"simulation_model_issue": "error",
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"unannotated": "error",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"unresolved_variable": "error",
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@ -452,6 +458,8 @@
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"schematic": {
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"schematic": {
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"annotate_start_num": 0,
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"annotate_start_num": 0,
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"drawing": {
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_line_thickness": 6.0,
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"default_line_thickness": 6.0,
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"default_text_size": 50.0,
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"default_text_size": 50.0,
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"field_names": [],
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"field_names": [],
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@ -483,7 +491,11 @@
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"page_layout_descr_file": "",
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"page_layout_descr_file": "",
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"plot_directory": "",
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"plot_directory": "",
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"spice_adjust_passive_values": false,
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"spice_adjust_passive_values": false,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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"spice_external_command": "spice \"%I\"",
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"spice_model_current_sheet_as_root": true,
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"spice_save_all_currents": false,
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"spice_save_all_voltages": false,
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"subpart_first_id": 65,
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"subpart_first_id": 65,
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"subpart_id_separator": 0
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"subpart_id_separator": 0
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},
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},
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