Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/README.txt

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+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_crossbar_0_0/sim/design_1_axi_crossbar_0_0.v

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+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_axi_crossbar_0_0 (
+  aclk,
+  aresetn,
+  s_axi_awaddr,
+  s_axi_awprot,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arprot,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
+input wire [0 : 0] s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
+output wire [0 : 0] s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
+input wire [0 : 0] s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
+output wire [0 : 0] s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
+output wire [0 : 0] s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
+input wire [0 : 0] s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
+input wire [0 : 0] s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
+output wire [0 : 0] s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
+output wire [0 : 0] s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRIT\
+E_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
+input wire [0 : 0] s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
+output wire [63 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
+output wire [5 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
+output wire [1 : 0] m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
+input wire [1 : 0] m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
+output wire [63 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
+output wire [7 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
+output wire [1 : 0] m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
+input wire [1 : 0] m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
+input wire [3 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
+input wire [1 : 0] m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
+output wire [1 : 0] m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
+output wire [63 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
+output wire [5 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
+output wire [1 : 0] m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
+input wire [1 : 0] m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
+input wire [63 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
+input wire [3 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
+input wire [1 : 0] m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRIT\
+E_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0\
+.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
+output wire [1 : 0] m_axi_rready;
+
+  axi_crossbar_v2_1_22_axi_crossbar #(
+    .C_FAMILY("artix7"),
+    .C_NUM_SLAVE_SLOTS(1),
+    .C_NUM_MASTER_SLOTS(2),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_PROTOCOL(2),
+    .C_NUM_ADDR_RANGES(1),
+    .C_M_AXI_BASE_ADDR(128'H00000000400000000000000040020000),
+    .C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
+    .C_S_AXI_BASE_ID(32'H00000000),
+    .C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
+    .C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
+    .C_R_REGISTER(0),
+    .C_S_AXI_SINGLE_THREAD(32'H00000001),
+    .C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
+    .C_S_AXI_READ_ACCEPTANCE(32'H00000001),
+    .C_M_AXI_WRITE_ISSUING(64'H0000000100000001),
+    .C_M_AXI_READ_ISSUING(64'H0000000100000001),
+    .C_S_AXI_ARB_PRIORITY(32'H00000000),
+    .C_M_AXI_SECURE(32'H00000000),
+    .C_CONNECTIVITY_MODE(0)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(8'H00),
+    .s_axi_awsize(3'H0),
+    .s_axi_awburst(2'H0),
+    .s_axi_awlock(1'H0),
+    .s_axi_awcache(4'H0),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(4'H0),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(1'H1),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(8'H00),
+    .s_axi_arsize(3'H0),
+    .s_axi_arburst(2'H0),
+    .s_axi_arlock(1'H0),
+    .s_axi_arcache(4'H0),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(4'H0),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(2'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(2'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(2'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(2'H3),
+    .m_axi_ruser(2'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_crossbar_0_1/sim/design_1_axi_crossbar_0_1.v

@@ -0,0 +1,429 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_axi_crossbar_0_1 (
+  aclk,
+  aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awqos,
+  s_axi_awuser,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awid,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awuser,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bid,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_arid,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rid,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
+input wire [63 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
+input wire [15 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
+input wire [5 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
+input wire [3 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
+input wire [7 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
+input wire [5 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
+input wire [7 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWUSER [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWUSER [3:0] [7:4]" *)
+input wire [7 : 0] s_axi_awuser;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [255:0] [255:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [255:0] [511:256]" *)
+input wire [511 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [31:0] [63:32]" *)
+input wire [63 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
+output wire [3 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
+input wire [63 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
+input wire [15 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
+input wire [5 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
+input wire [3 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
+input wire [7 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
+input wire [5 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
+input wire [7 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [255:0] [255:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [255:0] [511:256]" *)
+output wire [511 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
+output wire [3 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
+output wire [1 : 0] s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 4, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_\
+THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 4, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.00\
+0, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
+input wire [1 : 0] s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
+output wire [0 : 0] m_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWUSER" *)
+output wire [3 : 0] m_axi_awuser;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
+output wire [0 : 0] m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
+input wire [0 : 0] m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
+output wire [255 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
+output wire [31 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
+output wire [0 : 0] m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
+output wire [0 : 0] m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
+input wire [0 : 0] m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
+input wire [0 : 0] m_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
+input wire [0 : 0] m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
+output wire [0 : 0] m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
+output wire [0 : 0] m_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
+output wire [0 : 0] m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
+input wire [0 : 0] m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
+input wire [0 : 0] m_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
+input wire [255 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
+input wire [0 : 0] m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
+input wire [0 : 0] m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 4, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE\
+_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
+output wire [0 : 0] m_axi_rready;
+
+  axi_crossbar_v2_1_22_axi_crossbar #(
+    .C_FAMILY("artix7"),
+    .C_NUM_SLAVE_SLOTS(2),
+    .C_NUM_MASTER_SLOTS(1),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(256),
+    .C_AXI_PROTOCOL(0),
+    .C_NUM_ADDR_RANGES(1),
+    .C_M_AXI_BASE_ADDR(64'H0000000000000000),
+    .C_M_AXI_ADDR_WIDTH(32'H0000001d),
+    .C_S_AXI_BASE_ID(64'H0000000100000000),
+    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
+    .C_AXI_SUPPORTS_USER_SIGNALS(1),
+    .C_AXI_AWUSER_WIDTH(4),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_M_AXI_WRITE_CONNECTIVITY(32'H00000002),
+    .C_M_AXI_READ_CONNECTIVITY(32'H00000001),
+    .C_R_REGISTER(0),
+    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
+    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000002),
+    .C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002),
+    .C_M_AXI_WRITE_ISSUING(32'H00000008),
+    .C_M_AXI_READ_ISSUING(32'H00000008),
+    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
+    .C_M_AXI_SECURE(32'H00000000),
+    .C_CONNECTIVITY_MODE(1)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(s_axi_awuser),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(2'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(2'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(2'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awuser(m_axi_awuser),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_datamover_0_0/sim/design_1_axi_datamover_0_0.vhd

@@ -0,0 +1,387 @@
+-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_datamover:5.1
+-- IP Revision: 23
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_datamover_v5_1_23;
+USE axi_datamover_v5_1_23.axi_datamover;
+
+ENTITY design_1_axi_datamover_0_0 IS
+  PORT (
+    m_axi_s2mm_aclk : IN STD_LOGIC;
+    m_axi_s2mm_aresetn : IN STD_LOGIC;
+    s2mm_halt : IN STD_LOGIC;
+    s2mm_halt_cmplt : OUT STD_LOGIC;
+    s2mm_err : OUT STD_LOGIC;
+    m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
+    m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
+    s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
+    s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
+    s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
+    m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
+    m_axis_s2mm_sts_tready : IN STD_LOGIC;
+    m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
+    s2mm_allow_addr_req : IN STD_LOGIC;
+    s2mm_addr_req_posted : OUT STD_LOGIC;
+    s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
+    s2mm_ld_nxt_len : OUT STD_LOGIC;
+    s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    m_axi_s2mm_awvalid : OUT STD_LOGIC;
+    m_axi_s2mm_awready : IN STD_LOGIC;
+    m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axi_s2mm_wlast : OUT STD_LOGIC;
+    m_axi_s2mm_wvalid : OUT STD_LOGIC;
+    m_axi_s2mm_wready : IN STD_LOGIC;
+    m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    m_axi_s2mm_bvalid : IN STD_LOGIC;
+    m_axi_s2mm_bready : OUT STD_LOGIC;
+    s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+    s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    s_axis_s2mm_tlast : IN STD_LOGIC;
+    s_axis_s2mm_tvalid : IN STD_LOGIC;
+    s_axis_s2mm_tready : OUT STD_LOGIC;
+    s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END design_1_axi_datamover_0_0;
+
+ARCHITECTURE design_1_axi_datamover_0_0_arch OF design_1_axi_datamover_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_datamover_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_datamover IS
+    GENERIC (
+      C_INCLUDE_MM2S : INTEGER;
+      C_M_AXI_MM2S_ARID : INTEGER;
+      C_M_AXI_MM2S_ID_WIDTH : INTEGER;
+      C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
+      C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
+      C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
+      C_INCLUDE_MM2S_STSFIFO : INTEGER;
+      C_MM2S_STSCMD_FIFO_DEPTH : INTEGER;
+      C_MM2S_STSCMD_IS_ASYNC : INTEGER;
+      C_INCLUDE_MM2S_DRE : INTEGER;
+      C_MM2S_BURST_SIZE : INTEGER;
+      C_MM2S_BTT_USED : INTEGER;
+      C_MM2S_ADDR_PIPE_DEPTH : INTEGER;
+      C_INCLUDE_S2MM : INTEGER;
+      C_M_AXI_S2MM_AWID : INTEGER;
+      C_M_AXI_S2MM_ID_WIDTH : INTEGER;
+      C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
+      C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
+      C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
+      C_INCLUDE_S2MM_STSFIFO : INTEGER;
+      C_S2MM_STSCMD_FIFO_DEPTH : INTEGER;
+      C_S2MM_STSCMD_IS_ASYNC : INTEGER;
+      C_INCLUDE_S2MM_DRE : INTEGER;
+      C_S2MM_BURST_SIZE : INTEGER;
+      C_S2MM_BTT_USED : INTEGER;
+      C_S2MM_SUPPORT_INDET_BTT : INTEGER;
+      C_S2MM_ADDR_PIPE_DEPTH : INTEGER;
+      C_FAMILY : STRING;
+      C_MM2S_INCLUDE_SF : INTEGER;
+      C_S2MM_INCLUDE_SF : INTEGER;
+      C_ENABLE_CACHE_USER : INTEGER;
+      C_ENABLE_MM2S_TKEEP : INTEGER;
+      C_ENABLE_S2MM_TKEEP : INTEGER;
+      C_ENABLE_SKID_BUF : STRING;
+      C_ENABLE_S2MM_ADV_SIG : INTEGER;
+      C_ENABLE_MM2S_ADV_SIG : INTEGER;
+      C_CMD_WIDTH : INTEGER
+    );
+    PORT (
+      m_axi_mm2s_aclk : IN STD_LOGIC;
+      m_axi_mm2s_aresetn : IN STD_LOGIC;
+      mm2s_halt : IN STD_LOGIC;
+      mm2s_halt_cmplt : OUT STD_LOGIC;
+      mm2s_err : OUT STD_LOGIC;
+      m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
+      m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
+      s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
+      s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
+      s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
+      m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
+      m_axis_mm2s_sts_tready : IN STD_LOGIC;
+      m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
+      mm2s_allow_addr_req : IN STD_LOGIC;
+      mm2s_addr_req_posted : OUT STD_LOGIC;
+      mm2s_rd_xfer_cmplt : OUT STD_LOGIC;
+      m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_mm2s_arvalid : OUT STD_LOGIC;
+      m_axi_mm2s_arready : IN STD_LOGIC;
+      m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_mm2s_rlast : IN STD_LOGIC;
+      m_axi_mm2s_rvalid : IN STD_LOGIC;
+      m_axi_mm2s_rready : OUT STD_LOGIC;
+      m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axis_mm2s_tlast : OUT STD_LOGIC;
+      m_axis_mm2s_tvalid : OUT STD_LOGIC;
+      m_axis_mm2s_tready : IN STD_LOGIC;
+      mm2s_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      mm2s_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axi_s2mm_aclk : IN STD_LOGIC;
+      m_axi_s2mm_aresetn : IN STD_LOGIC;
+      s2mm_halt : IN STD_LOGIC;
+      s2mm_halt_cmplt : OUT STD_LOGIC;
+      s2mm_err : OUT STD_LOGIC;
+      m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
+      m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
+      s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
+      s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
+      s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
+      m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
+      m_axis_s2mm_sts_tready : IN STD_LOGIC;
+      m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
+      s2mm_allow_addr_req : IN STD_LOGIC;
+      s2mm_addr_req_posted : OUT STD_LOGIC;
+      s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
+      s2mm_ld_nxt_len : OUT STD_LOGIC;
+      s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_s2mm_awvalid : OUT STD_LOGIC;
+      m_axi_s2mm_awready : IN STD_LOGIC;
+      m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+      m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axi_s2mm_wlast : OUT STD_LOGIC;
+      m_axi_s2mm_wvalid : OUT STD_LOGIC;
+      m_axi_s2mm_wready : IN STD_LOGIC;
+      m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_s2mm_bvalid : IN STD_LOGIC;
+      m_axi_s2mm_bready : OUT STD_LOGIC;
+      s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+      s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      s_axis_s2mm_tlast : IN STD_LOGIC;
+      s_axis_s2mm_tvalid : IN STD_LOGIC;
+      s_axis_s2mm_tready : OUT STD_LOGIC;
+      s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_datamover;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 16, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awuser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, NUM_WRITE_OUTSTANDING 2, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 4, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WR" & 
+"ITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TKEEP";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_sts_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_CMDSTS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_S2MM_CMDSTS_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_CMDSTS_AWCLK, ASSOCIATED_BUSIF S_AXIS_S2MM_CMD:M_AXIS_S2MM_STS, ASSOCIATED_RESET m_axis_s2mm_cmdsts_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_S2MM_CMDSTS_AWCLK CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aresetn: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_S2MM_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_ACLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM, ASSOCIATED_RESET m_axi_s2mm_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
+BEGIN
+  U0 : axi_datamover
+    GENERIC MAP (
+      C_INCLUDE_MM2S => 0,
+      C_M_AXI_MM2S_ARID => 0,
+      C_M_AXI_MM2S_ID_WIDTH => 4,
+      C_M_AXI_MM2S_ADDR_WIDTH => 32,
+      C_M_AXI_MM2S_DATA_WIDTH => 32,
+      C_M_AXIS_MM2S_TDATA_WIDTH => 32,
+      C_INCLUDE_MM2S_STSFIFO => 0,
+      C_MM2S_STSCMD_FIFO_DEPTH => 4,
+      C_MM2S_STSCMD_IS_ASYNC => 0,
+      C_INCLUDE_MM2S_DRE => 0,
+      C_MM2S_BURST_SIZE => 16,
+      C_MM2S_BTT_USED => 16,
+      C_MM2S_ADDR_PIPE_DEPTH => 3,
+      C_INCLUDE_S2MM => 1,
+      C_M_AXI_S2MM_AWID => 0,
+      C_M_AXI_S2MM_ID_WIDTH => 1,
+      C_M_AXI_S2MM_ADDR_WIDTH => 32,
+      C_M_AXI_S2MM_DATA_WIDTH => 256,
+      C_S_AXIS_S2MM_TDATA_WIDTH => 128,
+      C_INCLUDE_S2MM_STSFIFO => 1,
+      C_S2MM_STSCMD_FIFO_DEPTH => 4,
+      C_S2MM_STSCMD_IS_ASYNC => 0,
+      C_INCLUDE_S2MM_DRE => 0,
+      C_S2MM_BURST_SIZE => 128,
+      C_S2MM_BTT_USED => 16,
+      C_S2MM_SUPPORT_INDET_BTT => 0,
+      C_S2MM_ADDR_PIPE_DEPTH => 4,
+      C_FAMILY => "artix7",
+      C_MM2S_INCLUDE_SF => 0,
+      C_S2MM_INCLUDE_SF => 1,
+      C_ENABLE_CACHE_USER => 0,
+      C_ENABLE_MM2S_TKEEP => 1,
+      C_ENABLE_S2MM_TKEEP => 1,
+      C_ENABLE_SKID_BUF => "11111",
+      C_ENABLE_S2MM_ADV_SIG => 1,
+      C_ENABLE_MM2S_ADV_SIG => 0,
+      C_CMD_WIDTH => 72
+    )
+    PORT MAP (
+      m_axi_mm2s_aclk => '0',
+      m_axi_mm2s_aresetn => '1',
+      mm2s_halt => '0',
+      m_axis_mm2s_cmdsts_aclk => '0',
+      m_axis_mm2s_cmdsts_aresetn => '1',
+      s_axis_mm2s_cmd_tvalid => '0',
+      s_axis_mm2s_cmd_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 72)),
+      m_axis_mm2s_sts_tready => '0',
+      mm2s_allow_addr_req => '1',
+      m_axi_mm2s_arready => '0',
+      m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      m_axi_mm2s_rlast => '0',
+      m_axi_mm2s_rvalid => '0',
+      m_axis_mm2s_tready => '0',
+      mm2s_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      m_axi_s2mm_aclk => m_axi_s2mm_aclk,
+      m_axi_s2mm_aresetn => m_axi_s2mm_aresetn,
+      s2mm_halt => s2mm_halt,
+      s2mm_halt_cmplt => s2mm_halt_cmplt,
+      s2mm_err => s2mm_err,
+      m_axis_s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk,
+      m_axis_s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn,
+      s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid,
+      s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready,
+      s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata,
+      m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid,
+      m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready,
+      m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata,
+      m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep,
+      m_axis_s2mm_sts_tlast => m_axis_s2mm_sts_tlast,
+      s2mm_allow_addr_req => s2mm_allow_addr_req,
+      s2mm_addr_req_posted => s2mm_addr_req_posted,
+      s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt,
+      s2mm_ld_nxt_len => s2mm_ld_nxt_len,
+      s2mm_wr_len => s2mm_wr_len,
+      m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
+      m_axi_s2mm_awlen => m_axi_s2mm_awlen,
+      m_axi_s2mm_awsize => m_axi_s2mm_awsize,
+      m_axi_s2mm_awburst => m_axi_s2mm_awburst,
+      m_axi_s2mm_awprot => m_axi_s2mm_awprot,
+      m_axi_s2mm_awcache => m_axi_s2mm_awcache,
+      m_axi_s2mm_awuser => m_axi_s2mm_awuser,
+      m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
+      m_axi_s2mm_awready => m_axi_s2mm_awready,
+      m_axi_s2mm_wdata => m_axi_s2mm_wdata,
+      m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
+      m_axi_s2mm_wlast => m_axi_s2mm_wlast,
+      m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
+      m_axi_s2mm_wready => m_axi_s2mm_wready,
+      m_axi_s2mm_bresp => m_axi_s2mm_bresp,
+      m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
+      m_axi_s2mm_bready => m_axi_s2mm_bready,
+      s_axis_s2mm_tdata => s_axis_s2mm_tdata,
+      s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
+      s_axis_s2mm_tlast => s_axis_s2mm_tlast,
+      s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
+      s_axis_s2mm_tready => s_axis_s2mm_tready,
+      s2mm_dbg_sel => s2mm_dbg_sel,
+      s2mm_dbg_data => s2mm_dbg_data
+    );
+END design_1_axi_datamover_0_0_arch;

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_dwidth_converter_0_0/sim/design_1_axi_dwidth_converter_0_0.v

@@ -0,0 +1,271 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 21
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_axi_dwidth_converter_0_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [1 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [1 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_TH\
+READS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [255 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_TH\
+READS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_21_top #(
+    .C_FAMILY("artix7"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(2),
+    .C_SUPPORTS_ID(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(128),
+    .C_M_AXI_DATA_WIDTH(256),
+    .C_AXI_SUPPORTS_WRITE(0),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(2'H0),
+    .s_axi_awaddr(32'H00000000),
+    .s_axi_awlen(8'H00),
+    .s_axi_awsize(3'H0),
+    .s_axi_awburst(2'H1),
+    .s_axi_awlock(1'H0),
+    .s_axi_awcache(4'H0),
+    .s_axi_awprot(3'H0),
+    .s_axi_awregion(4'H0),
+    .s_axi_awqos(4'H0),
+    .s_axi_awvalid(1'H0),
+    .s_axi_awready(),
+    .s_axi_wdata(128'H00000000000000000000000000000000),
+    .s_axi_wstrb(16'HFFFF),
+    .s_axi_wlast(1'H1),
+    .s_axi_wvalid(1'H0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'H0),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'H0),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'H0),
+    .m_axi_bresp(2'H0),
+    .m_axi_bvalid(1'H0),
+    .m_axi_bready(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd

@@ -0,0 +1,343 @@
+-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_fifo_mm_s:4.2
+-- IP Revision: 3
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_fifo_mm_s_v4_2_3;
+USE axi_fifo_mm_s_v4_2_3.axi_fifo_mm_s;
+
+ENTITY design_1_axi_fifo_mm_s_0_0 IS
+  PORT (
+    interrupt : OUT STD_LOGIC;
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    mm2s_prmry_reset_out_n : OUT STD_LOGIC;
+    axi_str_txd_tvalid : OUT STD_LOGIC;
+    axi_str_txd_tready : IN STD_LOGIC;
+    axi_str_txd_tlast : OUT STD_LOGIC;
+    axi_str_txd_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END design_1_axi_fifo_mm_s_0_0;
+
+ARCHITECTURE design_1_axi_fifo_mm_s_0_0_arch OF design_1_axi_fifo_mm_s_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_fifo_mm_s_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_fifo_mm_s IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ID_WIDTH : INTEGER;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_S_AXI4_DATA_WIDTH : INTEGER;
+      C_TX_FIFO_DEPTH : INTEGER;
+      C_RX_FIFO_DEPTH : INTEGER;
+      C_TX_CASCADE_HEIGHT : INTEGER;
+      C_RX_CASCADE_HEIGHT : INTEGER;
+      C_TX_FIFO_PF_THRESHOLD : INTEGER;
+      C_TX_FIFO_PE_THRESHOLD : INTEGER;
+      C_RX_FIFO_PF_THRESHOLD : INTEGER;
+      C_RX_FIFO_PE_THRESHOLD : INTEGER;
+      C_USE_TX_CUT_THROUGH : INTEGER;
+      C_DATA_INTERFACE_TYPE : INTEGER;
+      C_BASEADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_HIGHADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_AXI4_BASEADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_AXI4_HIGHADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_HAS_AXIS_TID : INTEGER;
+      C_HAS_AXIS_TDEST : INTEGER;
+      C_HAS_AXIS_TUSER : INTEGER;
+      C_HAS_AXIS_TSTRB : INTEGER;
+      C_HAS_AXIS_TKEEP : INTEGER;
+      C_AXIS_TID_WIDTH : INTEGER;
+      C_AXIS_TDEST_WIDTH : INTEGER;
+      C_AXIS_TUSER_WIDTH : INTEGER;
+      C_USE_RX_CUT_THROUGH : INTEGER;
+      C_USE_TX_DATA : INTEGER;
+      C_USE_TX_CTRL : INTEGER;
+      C_USE_RX_DATA : INTEGER
+    );
+    PORT (
+      interrupt : OUT STD_LOGIC;
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      s_axi4_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_awlock : IN STD_LOGIC;
+      s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_awvalid : IN STD_LOGIC;
+      s_axi4_awready : OUT STD_LOGIC;
+      s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_wlast : IN STD_LOGIC;
+      s_axi4_wvalid : IN STD_LOGIC;
+      s_axi4_wready : OUT STD_LOGIC;
+      s_axi4_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_bvalid : OUT STD_LOGIC;
+      s_axi4_bready : IN STD_LOGIC;
+      s_axi4_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_arlock : IN STD_LOGIC;
+      s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi4_arvalid : IN STD_LOGIC;
+      s_axi4_arready : OUT STD_LOGIC;
+      s_axi4_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi4_rlast : OUT STD_LOGIC;
+      s_axi4_rvalid : OUT STD_LOGIC;
+      s_axi4_rready : IN STD_LOGIC;
+      mm2s_prmry_reset_out_n : OUT STD_LOGIC;
+      axi_str_txd_tvalid : OUT STD_LOGIC;
+      axi_str_txd_tready : IN STD_LOGIC;
+      axi_str_txd_tlast : OUT STD_LOGIC;
+      axi_str_txd_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txd_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      axi_str_txd_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txd_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txd_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txd_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
+      axi_str_txc_tvalid : OUT STD_LOGIC;
+      axi_str_txc_tready : IN STD_LOGIC;
+      axi_str_txc_tlast : OUT STD_LOGIC;
+      axi_str_txc_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txc_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      axi_str_txc_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txc_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txc_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_txc_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s2mm_prmry_reset_out_n : OUT STD_LOGIC;
+      axi_str_rxd_tvalid : IN STD_LOGIC;
+      axi_str_rxd_tready : OUT STD_LOGIC;
+      axi_str_rxd_tlast : IN STD_LOGIC;
+      axi_str_rxd_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_rxd_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      axi_str_rxd_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_rxd_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_rxd_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_str_rxd_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
+    );
+  END COMPONENT axi_fifo_mm_s;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF axi_str_txd_tvalid: SIGNAL IS "XIL_INTERFACENAME AXI_STR_TXD, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME rst_axi_str_txd, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 rst_axi_str_txd RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_" & 
+"THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME rst_s_axi, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 rst_s_axi RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME aclk_s_axi, ASSOCIATED_BUSIF S_AXI:S_AXI_FULL:AXI_STR_TXD:AXI_STR_TXC:AXI_STR_RXD, ASSOCIATED_RESET s_axi_aresetn:mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n:s2mm_prmry_reset_out_n, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_s_axi CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF interrupt: SIGNAL IS "XIL_INTERFACENAME interrupt_intf, SENSITIVITY LEVEL_HIGH, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_intf INTERRUPT";
+BEGIN
+  U0 : axi_fifo_mm_s
+    GENERIC MAP (
+      C_FAMILY => "artix7",
+      C_S_AXI_ID_WIDTH => 4,
+      C_S_AXI_ADDR_WIDTH => 32,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_S_AXI4_DATA_WIDTH => 32,
+      C_TX_FIFO_DEPTH => 512,
+      C_RX_FIFO_DEPTH => 512,
+      C_TX_CASCADE_HEIGHT => 0,
+      C_RX_CASCADE_HEIGHT => 0,
+      C_TX_FIFO_PF_THRESHOLD => 507,
+      C_TX_FIFO_PE_THRESHOLD => 5,
+      C_RX_FIFO_PF_THRESHOLD => 507,
+      C_RX_FIFO_PE_THRESHOLD => 5,
+      C_USE_TX_CUT_THROUGH => 0,
+      C_DATA_INTERFACE_TYPE => 0,
+      C_BASEADDR => X"40020000",
+      C_HIGHADDR => X"4002FFFF",
+      C_AXI4_BASEADDR => X"80001000",
+      C_AXI4_HIGHADDR => X"80002FFF",
+      C_HAS_AXIS_TID => 0,
+      C_HAS_AXIS_TDEST => 0,
+      C_HAS_AXIS_TUSER => 0,
+      C_HAS_AXIS_TSTRB => 0,
+      C_HAS_AXIS_TKEEP => 0,
+      C_AXIS_TID_WIDTH => 4,
+      C_AXIS_TDEST_WIDTH => 4,
+      C_AXIS_TUSER_WIDTH => 4,
+      C_USE_RX_CUT_THROUGH => 0,
+      C_USE_TX_DATA => 1,
+      C_USE_TX_CTRL => 0,
+      C_USE_RX_DATA => 0
+    )
+    PORT MAP (
+      interrupt => interrupt,
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi4_awlock => '0',
+      s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_awvalid => '0',
+      s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_wlast => '0',
+      s_axi4_wvalid => '0',
+      s_axi4_bready => '0',
+      s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi4_arlock => '0',
+      s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi4_arvalid => '0',
+      s_axi4_rready => '0',
+      mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
+      axi_str_txd_tvalid => axi_str_txd_tvalid,
+      axi_str_txd_tready => axi_str_txd_tready,
+      axi_str_txd_tlast => axi_str_txd_tlast,
+      axi_str_txd_tdata => axi_str_txd_tdata,
+      axi_str_txc_tready => '0',
+      axi_str_rxd_tvalid => '0',
+      axi_str_rxd_tlast => '0',
+      axi_str_rxd_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_str_rxd_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      axi_str_rxd_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_str_rxd_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_str_rxd_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_str_rxd_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4))
+    );
+END design_1_axi_fifo_mm_s_0_0_arch;

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_gpio_0_1/sim/design_1_axi_gpio_0_1.vhd

@@ -0,0 +1,207 @@
+-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 23
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_23;
+USE axi_gpio_v2_0_23.axi_gpio;
+
+ENTITY design_1_axi_gpio_0_1 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END design_1_axi_gpio_0_1;
+
+ARCHITECTURE design_1_axi_gpio_0_1_arch OF design_1_axi_gpio_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T" & 
+"HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "artix7",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 32,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 1,
+      C_ALL_OUTPUTS => 1,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"00000000",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 1,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      gpio_io_o => gpio_io_o,
+      gpio2_io_i => gpio2_io_i
+    );
+END design_1_axi_gpio_0_1_arch;

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_axixclk_0_0/sim/design_1_axixclk_0_0.v

@@ -0,0 +1,391 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:module_ref:axixclk:1.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+(* IP_DEFINITION_SOURCE = "module_ref" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_axixclk_0_0 (
+  S_AXI_ACLK,
+  S_AXI_ARESETN,
+  S_AXI_AWID,
+  S_AXI_AWADDR,
+  S_AXI_AWLEN,
+  S_AXI_AWSIZE,
+  S_AXI_AWBURST,
+  S_AXI_AWLOCK,
+  S_AXI_AWCACHE,
+  S_AXI_AWPROT,
+  S_AXI_AWQOS,
+  S_AXI_AWVALID,
+  S_AXI_AWREADY,
+  S_AXI_WDATA,
+  S_AXI_WSTRB,
+  S_AXI_WLAST,
+  S_AXI_WVALID,
+  S_AXI_WREADY,
+  S_AXI_BID,
+  S_AXI_BRESP,
+  S_AXI_BVALID,
+  S_AXI_BREADY,
+  S_AXI_ARID,
+  S_AXI_ARADDR,
+  S_AXI_ARLEN,
+  S_AXI_ARSIZE,
+  S_AXI_ARBURST,
+  S_AXI_ARLOCK,
+  S_AXI_ARCACHE,
+  S_AXI_ARPROT,
+  S_AXI_ARQOS,
+  S_AXI_ARVALID,
+  S_AXI_ARREADY,
+  S_AXI_RID,
+  S_AXI_RDATA,
+  S_AXI_RRESP,
+  S_AXI_RLAST,
+  S_AXI_RVALID,
+  S_AXI_RREADY,
+  M_AXI_ACLK,
+  M_AXI_ARESETN,
+  M_AXI_AWID,
+  M_AXI_AWADDR,
+  M_AXI_AWLEN,
+  M_AXI_AWSIZE,
+  M_AXI_AWBURST,
+  M_AXI_AWLOCK,
+  M_AXI_AWCACHE,
+  M_AXI_AWPROT,
+  M_AXI_AWQOS,
+  M_AXI_AWVALID,
+  M_AXI_AWREADY,
+  M_AXI_WDATA,
+  M_AXI_WSTRB,
+  M_AXI_WLAST,
+  M_AXI_WVALID,
+  M_AXI_WREADY,
+  M_AXI_BID,
+  M_AXI_BRESP,
+  M_AXI_BVALID,
+  M_AXI_BREADY,
+  M_AXI_ARID,
+  M_AXI_ARADDR,
+  M_AXI_ARLEN,
+  M_AXI_ARSIZE,
+  M_AXI_ARBURST,
+  M_AXI_ARLOCK,
+  M_AXI_ARCACHE,
+  M_AXI_ARPROT,
+  M_AXI_ARQOS,
+  M_AXI_ARVALID,
+  M_AXI_ARREADY,
+  M_AXI_RID,
+  M_AXI_RDATA,
+  M_AXI_RRESP,
+  M_AXI_RLAST,
+  M_AXI_RVALID,
+  M_AXI_RREADY
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *)
+input wire S_AXI_ACLK;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *)
+input wire S_AXI_ARESETN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [0 : 0] S_AXI_AWID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [29 : 0] S_AXI_AWADDR;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] S_AXI_AWLEN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] S_AXI_AWSIZE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] S_AXI_AWBURST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire S_AXI_AWLOCK;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] S_AXI_AWCACHE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] S_AXI_AWPROT;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] S_AXI_AWQOS;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire S_AXI_AWVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire S_AXI_AWREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [255 : 0] S_AXI_WDATA;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [31 : 0] S_AXI_WSTRB;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire S_AXI_WLAST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire S_AXI_WVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire S_AXI_WREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [0 : 0] S_AXI_BID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] S_AXI_BRESP;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire S_AXI_BVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire S_AXI_BREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [0 : 0] S_AXI_ARID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [29 : 0] S_AXI_ARADDR;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] S_AXI_ARLEN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] S_AXI_ARSIZE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] S_AXI_ARBURST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire S_AXI_ARLOCK;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] S_AXI_ARCACHE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] S_AXI_ARPROT;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] S_AXI_ARQOS;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire S_AXI_ARVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire S_AXI_ARREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [0 : 0] S_AXI_RID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [255 : 0] S_AXI_RDATA;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] S_AXI_RRESP;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire S_AXI_RLAST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire S_AXI_RVALID;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
+HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire S_AXI_RREADY;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_ACLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK" *)
+input wire M_AXI_ACLK;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXI_ARESETN RST" *)
+output wire M_AXI_ARESETN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
+output wire [0 : 0] M_AXI_AWID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [29 : 0] M_AXI_AWADDR;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] M_AXI_AWLEN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] M_AXI_AWSIZE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] M_AXI_AWBURST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire M_AXI_AWLOCK;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] M_AXI_AWCACHE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] M_AXI_AWPROT;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] M_AXI_AWQOS;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire M_AXI_AWVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire M_AXI_AWREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [255 : 0] M_AXI_WDATA;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [31 : 0] M_AXI_WSTRB;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire M_AXI_WLAST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire M_AXI_WVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire M_AXI_WREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
+input wire [0 : 0] M_AXI_BID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] M_AXI_BRESP;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire M_AXI_BVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire M_AXI_BREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
+output wire [0 : 0] M_AXI_ARID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [29 : 0] M_AXI_ARADDR;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] M_AXI_ARLEN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] M_AXI_ARSIZE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] M_AXI_ARBURST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire M_AXI_ARLOCK;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] M_AXI_ARCACHE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] M_AXI_ARPROT;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] M_AXI_ARQOS;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire M_AXI_ARVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire M_AXI_ARREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
+input wire [0 : 0] M_AXI_RID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [255 : 0] M_AXI_RDATA;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] M_AXI_RRESP;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire M_AXI_RLAST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire M_AXI_RVALID;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_WRITE_\
+THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire M_AXI_RREADY;
+
+  axixclk #(
+    .C_S_AXI_ID_WIDTH(1),
+    .C_S_AXI_DATA_WIDTH(256),
+    .C_S_AXI_ADDR_WIDTH(30),
+    .OPT_WRITE_ONLY(1'B0),
+    .OPT_READ_ONLY(1'B0),
+    .XCLOCK_FFS(2),
+    .LGFIFO(5)
+  ) inst (
+    .S_AXI_ACLK(S_AXI_ACLK),
+    .S_AXI_ARESETN(S_AXI_ARESETN),
+    .S_AXI_AWID(S_AXI_AWID),
+    .S_AXI_AWADDR(S_AXI_AWADDR),
+    .S_AXI_AWLEN(S_AXI_AWLEN),
+    .S_AXI_AWSIZE(S_AXI_AWSIZE),
+    .S_AXI_AWBURST(S_AXI_AWBURST),
+    .S_AXI_AWLOCK(S_AXI_AWLOCK),
+    .S_AXI_AWCACHE(S_AXI_AWCACHE),
+    .S_AXI_AWPROT(S_AXI_AWPROT),
+    .S_AXI_AWQOS(S_AXI_AWQOS),
+    .S_AXI_AWVALID(S_AXI_AWVALID),
+    .S_AXI_AWREADY(S_AXI_AWREADY),
+    .S_AXI_WDATA(S_AXI_WDATA),
+    .S_AXI_WSTRB(S_AXI_WSTRB),
+    .S_AXI_WLAST(S_AXI_WLAST),
+    .S_AXI_WVALID(S_AXI_WVALID),
+    .S_AXI_WREADY(S_AXI_WREADY),
+    .S_AXI_BID(S_AXI_BID),
+    .S_AXI_BRESP(S_AXI_BRESP),
+    .S_AXI_BVALID(S_AXI_BVALID),
+    .S_AXI_BREADY(S_AXI_BREADY),
+    .S_AXI_ARID(S_AXI_ARID),
+    .S_AXI_ARADDR(S_AXI_ARADDR),
+    .S_AXI_ARLEN(S_AXI_ARLEN),
+    .S_AXI_ARSIZE(S_AXI_ARSIZE),
+    .S_AXI_ARBURST(S_AXI_ARBURST),
+    .S_AXI_ARLOCK(S_AXI_ARLOCK),
+    .S_AXI_ARCACHE(S_AXI_ARCACHE),
+    .S_AXI_ARPROT(S_AXI_ARPROT),
+    .S_AXI_ARQOS(S_AXI_ARQOS),
+    .S_AXI_ARVALID(S_AXI_ARVALID),
+    .S_AXI_ARREADY(S_AXI_ARREADY),
+    .S_AXI_RID(S_AXI_RID),
+    .S_AXI_RDATA(S_AXI_RDATA),
+    .S_AXI_RRESP(S_AXI_RRESP),
+    .S_AXI_RLAST(S_AXI_RLAST),
+    .S_AXI_RVALID(S_AXI_RVALID),
+    .S_AXI_RREADY(S_AXI_RREADY),
+    .M_AXI_ACLK(M_AXI_ACLK),
+    .M_AXI_ARESETN(M_AXI_ARESETN),
+    .M_AXI_AWID(M_AXI_AWID),
+    .M_AXI_AWADDR(M_AXI_AWADDR),
+    .M_AXI_AWLEN(M_AXI_AWLEN),
+    .M_AXI_AWSIZE(M_AXI_AWSIZE),
+    .M_AXI_AWBURST(M_AXI_AWBURST),
+    .M_AXI_AWLOCK(M_AXI_AWLOCK),
+    .M_AXI_AWCACHE(M_AXI_AWCACHE),
+    .M_AXI_AWPROT(M_AXI_AWPROT),
+    .M_AXI_AWQOS(M_AXI_AWQOS),
+    .M_AXI_AWVALID(M_AXI_AWVALID),
+    .M_AXI_AWREADY(M_AXI_AWREADY),
+    .M_AXI_WDATA(M_AXI_WDATA),
+    .M_AXI_WSTRB(M_AXI_WSTRB),
+    .M_AXI_WLAST(M_AXI_WLAST),
+    .M_AXI_WVALID(M_AXI_WVALID),
+    .M_AXI_WREADY(M_AXI_WREADY),
+    .M_AXI_BID(M_AXI_BID),
+    .M_AXI_BRESP(M_AXI_BRESP),
+    .M_AXI_BVALID(M_AXI_BVALID),
+    .M_AXI_BREADY(M_AXI_BREADY),
+    .M_AXI_ARID(M_AXI_ARID),
+    .M_AXI_ARADDR(M_AXI_ARADDR),
+    .M_AXI_ARLEN(M_AXI_ARLEN),
+    .M_AXI_ARSIZE(M_AXI_ARSIZE),
+    .M_AXI_ARBURST(M_AXI_ARBURST),
+    .M_AXI_ARLOCK(M_AXI_ARLOCK),
+    .M_AXI_ARCACHE(M_AXI_ARCACHE),
+    .M_AXI_ARPROT(M_AXI_ARPROT),
+    .M_AXI_ARQOS(M_AXI_ARQOS),
+    .M_AXI_ARVALID(M_AXI_ARVALID),
+    .M_AXI_ARREADY(M_AXI_ARREADY),
+    .M_AXI_RID(M_AXI_RID),
+    .M_AXI_RDATA(M_AXI_RDATA),
+    .M_AXI_RRESP(M_AXI_RRESP),
+    .M_AXI_RLAST(M_AXI_RLAST),
+    .M_AXI_RVALID(M_AXI_RVALID),
+    .M_AXI_RREADY(M_AXI_RREADY)
+  );
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v

@@ -0,0 +1,92 @@
+
+// file: design_1_clk_wiz_0_0.v
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__200.00000______0.000______50.0______109.241_____96.948
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________125.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "design_1_clk_wiz_0_0,clk_wiz_v6_0_5_0_0,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=8.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module design_1_clk_wiz_0_0 
+ (
+  // Clock out ports
+  output        clk_out1,
+  // Status and control signals
+  input         resetn,
+  output        locked,
+ // Clock in ports
+  input         clk_in1
+ );
+
+  design_1_clk_wiz_0_0_clk_wiz inst
+  (
+  // Clock out ports  
+  .clk_out1(clk_out1),
+  // Status and control signals               
+  .resetn(resetn), 
+  .locked(locked),
+ // Clock in ports
+  .clk_in1(clk_in1)
+  );
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v

@@ -0,0 +1,182 @@
+
+// file: design_1_clk_wiz_0_0.v
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__200.00000______0.000______50.0______109.241_____96.948
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________125.000____________0.010
+
+`timescale 1ps/1ps
+
+module design_1_clk_wiz_0_0_clk_wiz 
+
+ (// Clock in ports
+  // Clock out ports
+  output        clk_out1,
+  // Status and control signals
+  input         resetn,
+  output        locked,
+  input         clk_in1
+ );
+  // Input buffering
+  //------------------------------------
+wire clk_in1_design_1_clk_wiz_0_0;
+wire clk_in2_design_1_clk_wiz_0_0;
+  assign clk_in1_design_1_clk_wiz_0_0 = clk_in1;
+
+
+
+
+  // Clocking PRIMITIVE
+  //------------------------------------
+
+  // Instantiation of the MMCM PRIMITIVE
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+
+  wire        clk_out1_design_1_clk_wiz_0_0;
+  wire        clk_out2_design_1_clk_wiz_0_0;
+  wire        clk_out3_design_1_clk_wiz_0_0;
+  wire        clk_out4_design_1_clk_wiz_0_0;
+  wire        clk_out5_design_1_clk_wiz_0_0;
+  wire        clk_out6_design_1_clk_wiz_0_0;
+  wire        clk_out7_design_1_clk_wiz_0_0;
+
+  wire [15:0] do_unused;
+  wire        drdy_unused;
+  wire        psdone_unused;
+  wire        locked_int;
+  wire        clkfbout_design_1_clk_wiz_0_0;
+  wire        clkfbout_buf_design_1_clk_wiz_0_0;
+  wire        clkfboutb_unused;
+   wire clkout1_unused;
+   wire clkout2_unused;
+   wire clkout3_unused;
+   wire clkout4_unused;
+  wire        clkout5_unused;
+  wire        clkout6_unused;
+  wire        clkfbstopped_unused;
+  wire        clkinstopped_unused;
+  wire        reset_high;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("ZHOLD"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (8),
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (5),
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (8.000))
+  plle2_adv_inst
+    // Output clocks
+   (
+    .CLKFBOUT            (clkfbout_design_1_clk_wiz_0_0),
+    .CLKOUT0             (clk_out1_design_1_clk_wiz_0_0),
+    .CLKOUT1             (clkout1_unused),
+    .CLKOUT2             (clkout2_unused),
+    .CLKOUT3             (clkout3_unused),
+    .CLKOUT4             (clkout4_unused),
+    .CLKOUT5             (clkout5_unused),
+     // Input clock control
+    .CLKFBIN             (clkfbout_buf_design_1_clk_wiz_0_0),
+    .CLKIN1              (clk_in1_design_1_clk_wiz_0_0),
+    .CLKIN2              (1'b0),
+     // Tied to always select the primary input clock
+    .CLKINSEL            (1'b1),
+    // Ports for dynamic reconfiguration
+    .DADDR               (7'h0),
+    .DCLK                (1'b0),
+    .DEN                 (1'b0),
+    .DI                  (16'h0),
+    .DO                  (do_unused),
+    .DRDY                (drdy_unused),
+    .DWE                 (1'b0),
+    // Other control and status signals
+    .LOCKED              (locked_int),
+    .PWRDWN              (1'b0),
+    .RST                 (reset_high));
+  assign reset_high = ~resetn; 
+
+  assign locked = locked_int;
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+  //-----------------------------------
+
+  BUFG clkf_buf
+   (.O (clkfbout_buf_design_1_clk_wiz_0_0),
+    .I (clkfbout_design_1_clk_wiz_0_0));
+
+
+
+
+
+
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_design_1_clk_wiz_0_0));
+
+
+
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_util_ds_buf_0_0/sim/design_1_util_ds_buf_0_0.vhd

@@ -0,0 +1,239 @@
+-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:util_ds_buf:2.1
+-- IP Revision: 22
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_util_ds_buf_0_0 IS
+  PORT (
+    IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END design_1_util_ds_buf_0_0;
+
+ARCHITECTURE design_1_util_ds_buf_0_0_arch OF design_1_util_ds_buf_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_util_ds_buf_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT util_ds_buf IS
+    GENERIC (
+      C_BUF_TYPE : STRING;
+      C_SIZE : INTEGER;
+      C_BUFGCE_DIV : INTEGER;
+      C_BUFG_GT_SYNC : INTEGER;
+      C_SIM_DEVICE : STRING;
+      C_OBUFDS_GTE5_ADV : STD_LOGIC_VECTOR;
+      C_REFCLK_ICNTL_TX : STD_LOGIC_VECTOR
+    );
+    PORT (
+      IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUF_DS_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IOBUF_IO_IO : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFGCE_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_FABRIC_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE4_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE4_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE3_ADV_I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      RXRECCLK_SEL_GTE3_ADV : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      OBUFDS_GTE3_ADV_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE4_ADV_I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      RXRECCLK_SEL_GTE4_ADV : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      OBUFDS_GTE4_ADV_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE3_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE3_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_ADV_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_ADV_I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      IBUFDS_GTME5_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTME5_IB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTME5_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      IBUFDS_GTM_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTM_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTM_IB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTME5_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTME5_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_ADV_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_ADV_I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      OBUFDS_GTME5_ADV_CEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTME5_ADV_I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      BUFG_FABRIC_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE4_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE4_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE3_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE3_ADV_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE3_ADV_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE4_ADV_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE4_ADV_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE3_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_ADV_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTE5_ADV_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTME5_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTME5_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTM_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      IBUFDS_GTM_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTME5_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTME5_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_ADV_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTM_ADV_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTME5_ADV_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      OBUFDS_GTME5_ADV_OB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+    );
+  END COMPONENT util_ds_buf;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF IBUF_DS_ODIV2: SIGNAL IS "XIL_INTERFACENAME IBUF_DS_ODIV2, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_util_ds_buf_0_0_IBUF_DS_ODIV2, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF IBUF_DS_ODIV2: SIGNAL IS "xilinx.com:signal:clock:1.0 IBUF_DS_ODIV2 CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF IBUF_OUT: SIGNAL IS "XIL_INTERFACENAME IBUF_OUT, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_util_ds_buf_0_0_IBUF_OUT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF IBUF_OUT: SIGNAL IS "xilinx.com:signal:clock:1.0 IBUF_OUT CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF IBUF_DS_N: SIGNAL IS "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_N";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF IBUF_DS_P: SIGNAL IS "XIL_INTERFACENAME CLK_IN_D, BOARD.ASSOCIATED_PARAM DIFF_CLK_IN_BOARD_INTERFACE, CAN_DEBUG false, FREQ_HZ 100000000";
+  ATTRIBUTE X_INTERFACE_INFO OF IBUF_DS_P: SIGNAL IS "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_P";
+BEGIN
+  U0 : util_ds_buf
+    GENERIC MAP (
+      C_BUF_TYPE => "ibufdsgte2",
+      C_SIZE => 1,
+      C_BUFGCE_DIV => 1,
+      C_BUFG_GT_SYNC => 0,
+      C_SIM_DEVICE => "VERSAL_AI_CORE_ES1",
+      C_OBUFDS_GTE5_ADV => B"00",
+      C_REFCLK_ICNTL_TX => B"00000"
+    )
+    PORT MAP (
+      IBUF_DS_P => IBUF_DS_P,
+      IBUF_DS_N => IBUF_DS_N,
+      IBUF_DS_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      IBUF_OUT => IBUF_OUT,
+      IBUF_DS_ODIV2 => IBUF_DS_ODIV2,
+      OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFGCE_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_FABRIC_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE5_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE5_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE4_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE4_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE3_ADV_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      RXRECCLK_SEL_GTE3_ADV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      OBUFDS_GTE3_ADV_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE4_ADV_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      RXRECCLK_SEL_GTE4_ADV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      OBUFDS_GTE4_ADV_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE3_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE3_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE5_ADV_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTE5_ADV_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      IBUFDS_GTME5_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      IBUFDS_GTME5_IB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      IBUFDS_GTME5_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      IBUFDS_GTM_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      IBUFDS_GTM_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      IBUFDS_GTM_IB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTME5_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTME5_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTM_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTM_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTM_ADV_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTM_ADV_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      OBUFDS_GTME5_ADV_CEB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      OBUFDS_GTME5_ADV_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4))
+    );
+END design_1_util_ds_buf_0_0_arch;

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_util_ds_buf_0_0/util_ds_buf.vhd

@@ -0,0 +1,766 @@
+
+-------------------------------------------------------------------------------
+-- util_ds_buf.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+--  ***************************************************************************
+--  **  Copyright(C) 2007 by Xilinx, Inc. All rights reserved.               **
+--  **                                                                       **
+--  **  This text contains proprietary, confidential                         **
+--  **  information of Xilinx, Inc. , is distributed by                      **
+--  **  under license from Xilinx, Inc., and may be used,                    **
+--  **  copied and/or disclosed only pursuant to the terms                   **
+--  **  of a valid license agreement with Xilinx, Inc.                       **
+--  **                                                                       **
+--  **  Unmodified source code is guaranteed to place and route,             **
+--  **  function and run at speed according to the datasheet                 **
+--  **  specification. Source code is provided "as-is", with no              **
+--  **  obligation on the part of Xilinx to provide support.                 **
+--  **                                                                       **
+--  **  Xilinx Hotline support of source code IP shall only include          **
+--  **  standard level Xilinx Hotline support, and will only address         **
+--  **  issues and questions related to the standard released Netlist        **
+--  **  version of the core (and thus indirectly, the original core source). **
+--  **                                                                       **
+--  **  The Xilinx Support Hotline does not have access to source            **
+--  **  code and therefore cannot answer specific questions related          **
+--  **  to source HDL. The Xilinx Support Hotline will only be able          **
+--  **  to confirm the problem in the Netlist version of the core.           **
+--  **                                                                       **
+--  **  This copyright and support notice must be retained as part           **
+--  **  of this text at all times.                                           **
+--  ***************************************************************************
+--
+-------------------------------------------------------------------------------
+-- Filename:        util_ds_buf.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              util_ds_buf.vhd
+--
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity util_ds_buf is
+   generic (
+         C_BUF_TYPE          : string  := "IBUFDS";
+         C_SIZE              : integer := 1;
+         C_BUFGCE_DIV        : integer := 2;
+         C_BUFG_GT_SYNC      : integer := 0;
+         C_SIM_DEVICE        : string  := "VERSAL_AI_CORE_ES1";
+         C_OBUFDS_GTE5_ADV   : std_logic_vector(1 downto 0) := "00";
+         C_REFCLK_ICNTL_TX   : std_logic_vector(4 downto 0) := "00000"   
+      );
+
+   port (
+    -- ports for differential signaling input buffer
+           IBUF_DS_P       : in    std_logic_vector(C_SIZE-1 downto 0);
+           IBUF_DS_N       : in    std_logic_vector(C_SIZE-1 downto 0);
+           IBUF_OUT        : out   std_logic_vector(C_SIZE-1 downto 0);
+           IBUF_DS_ODIV2   : out   std_logic_vector(C_SIZE-1 downto 0);
+           IBUF_DS_CEB     : in    std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports for differential signaling output buffer
+           OBUF_IN         : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUF_DS_P       : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUF_DS_N       : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports for tri-state differential signaling io buffer
+           IOBUF_DS_P      : inout std_logic_vector(C_SIZE-1 downto 0);
+           IOBUF_DS_N      : inout std_logic_vector(C_SIZE-1 downto 0);
+           IOBUF_IO_T      : in    std_logic_vector(C_SIZE-1 downto 0);
+           IOBUF_IO_I      : in    std_logic_vector(C_SIZE-1 downto 0);
+           IOBUF_IO_O      : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports specific to io buffer inout 
+           IOBUF_IO_IO      : inout   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports for BUFG
+           BUFG_I          : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFG_O          : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports for BUFGCE
+           BUFGCE_I        : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFGCE_CE       : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFGCE_O        : out   std_logic_vector(C_SIZE-1 downto 0);
+           BUFGCE_CLR      : in    std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports for BUFH
+           BUFH_I          : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFH_O          : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports for BUFHCE
+           BUFHCE_I        : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFHCE_CE       : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFHCE_O        : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for BUFG_FABRIC 
+           BUFG_FABRIC_I   : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFG_FABRIC_O   : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTE5 
+           OBUFDS_GTE5_CEB : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE5_I   : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE5_O   : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE5_OB  : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTE5_ADV 
+           OBUFDS_GTE5_ADV_CEB : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE5_ADV_I   : in    std_logic_vector((4 * C_SIZE) - 1 downto 0);
+           OBUFDS_GTE5_ADV_O   : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE5_ADV_OB  : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTE3 
+           OBUFDS_GTE3_CEB : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE3_I   : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE3_O   : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE3_OB  : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTE3_ADV 
+           OBUFDS_GTE3_ADV_CEB   : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE3_ADV_I     : in    std_logic_vector((4 * C_SIZE) -1 downto 0);
+           OBUFDS_GTE3_ADV_O     : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE3_ADV_OB    : out   std_logic_vector(C_SIZE-1 downto 0);
+           RXRECCLK_SEL_GTE3_ADV : in    std_logic_vector((2 * C_SIZE) -1 downto 0);
+
+    -- port for OBUFDS_GTE4 
+           OBUFDS_GTE4_CEB       : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE4_I         : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE4_O         : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE4_OB        : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTE4_ADV 
+           OBUFDS_GTE4_ADV_CEB   : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE4_ADV_I     : in    std_logic_vector((4 * C_SIZE) -1 downto 0);
+           OBUFDS_GTE4_ADV_O     : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTE4_ADV_OB    : out   std_logic_vector(C_SIZE-1 downto 0);
+           RXRECCLK_SEL_GTE4_ADV : in    std_logic_vector((2 * C_SIZE) -1 downto 0);
+
+    -- port for IBUFDS_GTM 
+           IBUFDS_GTM_O           : out   std_logic_vector(C_SIZE-1 downto 0);
+           IBUFDS_GTM_ODIV2       : out   std_logic_vector(C_SIZE-1 downto 0);
+           IBUFDS_GTM_CEB         : in    std_logic_vector(C_SIZE-1 downto 0);
+           IBUFDS_GTM_I           : in    std_logic_vector(C_SIZE-1 downto 0);
+           IBUFDS_GTM_IB          : in    std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTM 
+           OBUFDS_GTM_O           : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTM_OB          : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTM_CEB         : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTM_I           : in    std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTM_ADV 
+           OBUFDS_GTM_ADV_CEB     : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTM_ADV_I       : in    std_logic_vector((4 * C_SIZE) -1 downto 0);
+           OBUFDS_GTM_ADV_O       : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTM_ADV_OB      : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for IBUFDS_GTME5
+           IBUFDS_GTME5_O        : out   std_logic_vector(C_SIZE-1 downto 0);
+           IBUFDS_GTME5_ODIV2    : out   std_logic_vector(C_SIZE-1 downto 0);  
+           IBUFDS_GTME5_CEB      : in    std_logic_vector(C_SIZE-1 downto 0);
+           IBUFDS_GTME5_I        : in    std_logic_vector(C_SIZE-1 downto 0);
+           IBUFDS_GTME5_IB       : in    std_logic_vector(C_SIZE-1 downto 0);
+
+    -- port for OBUFDS_GTME5 
+           OBUFDS_GTME5_CEB       : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTME5_I         : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTME5_O         : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTME5_OB        : out   std_logic_vector(C_SIZE-1 downto 0);
+
+
+    -- port for OBUFDS_GTME5_ADV 
+           OBUFDS_GTME5_ADV_CEB   : in    std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTME5_ADV_I     : in    std_logic_vector((4 * C_SIZE) -1 downto 0);
+           OBUFDS_GTME5_ADV_O     : out   std_logic_vector(C_SIZE-1 downto 0);
+           OBUFDS_GTME5_ADV_OB    : out   std_logic_vector(C_SIZE-1 downto 0);
+
+    -- ports for BUFG_GT
+           BUFG_GT_I              : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFG_GT_CE             : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFG_GT_CEMASK         : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFG_GT_CLR            : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFG_GT_CLRMASK        : in    std_logic_vector(C_SIZE-1 downto 0);
+           BUFG_GT_DIV            : in    std_logic_vector((3 * C_SIZE) - 1 downto 0);
+           BUFG_GT_O              : out   std_logic_vector(C_SIZE-1 downto 0)
+     );
+
+
+end util_ds_buf;
+
+architecture IMP of util_ds_buf is
+
+  -- function to return lower case character
+   function LowerCase_Char(char : character) return character is
+   begin
+    -- If char is not an upper case letter then return char
+      if char < 'A' or char > 'Z' then
+         return char;
+      end if;
+    -- Otherwise map char to its corresponding lower case character and
+    -- return that
+      case char is
+         when 'A'    => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
+         when 'E'    => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
+         when 'I'    => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
+         when 'M'    => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
+         when 'Q'    => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
+         when 'U'    => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
+         when 'Y'    => return 'y'; when 'Z' => return 'z';
+         when others => return char;
+      end case;
+   end LowerCase_Char;
+
+  -- function to return lower case string
+   function LowerCase_String (s : string) return string is
+      variable res : string(s'range);
+   begin
+      for I in s'range loop
+         res(I) := LowerCase_Char(s(I));
+      end loop;
+      return res;
+   end function LowerCase_String;
+
+   constant BUFFER_TYPE : string := LowerCase_String(C_BUF_TYPE);
+   constant BIT1       : bit := '0';
+   constant BIT2       : std_logic_vector (1 downto 0) := "00";
+   constant BIT3       : std_logic_vector (2 downto 0) := "010";
+
+
+begin
+
+  -- instantiate IBUFDS_GTE2
+   USE_IBUFDS_GTE2 : if (BUFFER_TYPE = "ibufdsgte2") generate
+      signal IBUF_OUT_P : std_logic_vector(C_SIZE-1 downto 0);
+      signal IBUF_OUT_N : std_logic_vector(C_SIZE-1 downto 0);
+   begin
+      GEN_IBUFDS_GTE2 : for i in 0 to C_SIZE-1 generate
+
+         IBUF_P_I : IBUF
+         port map (O => IBUF_OUT_P(i), I => IBUF_DS_P(i));
+         IBUF_N_I : IBUF
+         port map (O => IBUF_OUT_N(i), I => IBUF_DS_N(i));
+         IBUFDS_GTE2_I : IBUFDS_GTE2
+         port map (O => IBUF_OUT(i), ODIV2 => IBUF_DS_ODIV2(i), I => IBUF_OUT_P(i), IB => IBUF_OUT_N(i), CEB => '0');
+
+      end generate GEN_IBUFDS_GTE2;
+
+     -- tie-off other non-used outputs
+      OBUF_DS_P  <= (others => '0');
+      OBUF_DS_N  <= (others => '0');
+      IOBUF_IO_O <= (others => '0');
+      IOBUF_DS_P <= (others => '0');
+      IOBUF_DS_N <= (others => '0');
+
+   end generate USE_IBUFDS_GTE2;
+
+  -- instantiate IBUFDS_GTE3
+   USE_IBUFDS_GTE3 : if (BUFFER_TYPE = "ibufdsgte3") generate
+
+      GEN_IBUFDS_GTE3 : for i in 0 to C_SIZE-1 generate
+
+         IBUFDS_GTE3_I : IBUFDS_GTE3
+         port map (O => IBUF_OUT(i), ODIV2 => IBUF_DS_ODIV2(i), I => IBUF_DS_P(i), IB => IBUF_DS_N(i), CEB => '0');
+
+      end generate GEN_IBUFDS_GTE3;
+
+     -- tie-off other non-used outputs
+      OBUF_DS_P  <= (others => '0');
+      OBUF_DS_N  <= (others => '0');
+      IOBUF_IO_O <= (others => '0');
+      IOBUF_DS_P <= (others => '0');
+      IOBUF_DS_N <= (others => '0');
+
+   end generate USE_IBUFDS_GTE3;
+
+  -- instantiate IBUFDS_GTE4
+   USE_IBUFDS_GTE4 : if (BUFFER_TYPE = "ibufdsgte4") generate
+
+      GEN_IBUFDS_GTE4 : for i in 0 to C_SIZE-1 generate
+
+         IBUFDS_GTE4_I : IBUFDS_GTE4
+         port map (O => IBUF_OUT(i), ODIV2 => IBUF_DS_ODIV2(i), I => IBUF_DS_P(i), IB => IBUF_DS_N(i), CEB => '0');
+
+      end generate GEN_IBUFDS_GTE4;
+
+     -- tie-off other non-used outputs
+      OBUF_DS_P  <= (others => '0');
+      OBUF_DS_N  <= (others => '0');
+      IOBUF_IO_O <= (others => '0');
+      IOBUF_DS_P <= (others => '0');
+      IOBUF_DS_N <= (others => '0');
+
+   end generate USE_IBUFDS_GTE4;
+
+
+  -- instantiate IBUFDS
+   USE_IBUFDS : if (BUFFER_TYPE = "ibufds") generate
+
+      GEN_IBUFDS : for i in 0 to C_SIZE-1 generate
+
+         IBUFDS_I : IBUFDS
+         port map (O => IBUF_OUT(i), I => IBUF_DS_P(i), IB => IBUF_DS_N(i));
+
+      end generate GEN_IBUFDS;
+
+    -- tie-off other non-used outputs
+      IBUF_DS_ODIV2  <= (others => '0');
+      OBUF_DS_P      <= (others => '0');
+      OBUF_DS_N      <= (others => '0');
+      IOBUF_IO_O     <= (others => '0');
+      IOBUF_DS_P     <= (others => '0');
+      IOBUF_DS_N     <= (others => '0');
+
+   end generate USE_IBUFDS;
+
+  -- instantiate OBUFDS
+   USE_OBUFDS : if (BUFFER_TYPE = "obufds") generate
+
+      GEN_OBUFDS : for i in 0 to C_SIZE-1 generate
+
+         OBUFDS_I : OBUFDS
+         port map (O => OBUF_DS_P(i), OB => OBUF_DS_N(i), I => OBUF_IN(i));
+
+      end generate GEN_OBUFDS;
+
+    -- tie-off other non-used outputs
+      IBUF_OUT       <= (others => '0');
+      IBUF_DS_ODIV2  <= (others => '0');
+      IOBUF_IO_O     <= (others => '0');
+      IOBUF_DS_P     <= (others => '0');
+      IOBUF_DS_N     <= (others => '0');
+
+   end generate USE_OBUFDS;
+
+  -- instantiate IOBUFDS
+   USE_IOBUFDS : if (BUFFER_TYPE = "iobufds") generate
+
+      GEN_IOBUFDS : for i in 0 to C_SIZE-1 generate
+
+         IOBUFDS_I : IOBUFDS
+         port map (
+                O   => IOBUF_IO_O(i),
+                IO  => IOBUF_DS_P(i),
+                IOB => IOBUF_DS_N(i),
+                I   => IOBUF_IO_I(i),
+                T   => IOBUF_IO_T(i)
+             );
+
+      end generate GEN_IOBUFDS;
+
+    -- tie-off other non-used outputs
+      IBUF_OUT       <= (others => '0');
+      IBUF_DS_ODIV2  <= (others => '0');
+      OBUF_DS_P      <= (others => '0');
+      OBUF_DS_N      <= (others => '0');
+
+   end generate USE_IOBUFDS;
+
+
+  -- instantiate BUFG
+   USE_BUFG : if (BUFFER_TYPE = "bufg") generate
+
+      GEN_BUFG : for i in 0 to C_SIZE-1 generate
+
+         BUFG_U : BUFG
+         port map (
+                O   => BUFG_O(i),
+                I   => BUFG_I(i)
+             );
+
+      end generate GEN_BUFG;
+
+   end generate USE_BUFG;
+
+  -- instantiate BUFGCE
+   USE_BUFGCE : if (BUFFER_TYPE = "bufgce") generate
+
+      GEN_BUFGCE : for i in 0 to C_SIZE-1 generate
+
+         BUFGCE_U : BUFGCE
+         port map (
+                O   => BUFGCE_O(i),
+                I   => BUFGCE_I(i),
+                CE   => BUFGCE_CE(i)
+             );
+
+      end generate GEN_BUFGCE;
+
+   end generate USE_BUFGCE;
+
+
+  -- instantiate BUFH
+   USE_BUFH : if (BUFFER_TYPE = "bufh") generate
+
+      GEN_BUFH : for i in 0 to C_SIZE-1 generate
+
+         BUFH_U : BUFH
+         port map (
+                O   => BUFH_O(i),
+                I   => BUFH_I(i)
+             );
+
+      end generate GEN_BUFH;
+
+   end generate USE_BUFH;
+
+  -- instantiate BUFHCE
+   USE_BUFHCE : if (BUFFER_TYPE = "bufhce") generate
+
+      GEN_BUFHCE : for i in 0 to C_SIZE-1 generate
+
+         BUFHCE_U : BUFHCE
+         port map (
+                O   => BUFHCE_O(i),
+                I   => BUFHCE_I(i),
+                CE   => BUFHCE_CE(i)
+             );
+
+      end generate GEN_BUFHCE;
+
+   end generate USE_BUFHCE;
+
+
+ -- instantiate BUFG
+   USE_BUFG_GT_WITH_SYNC : if (BUFFER_TYPE = "bufg_gt" and C_BUFG_GT_SYNC = 1) generate
+        signal BUFG_GT_CESYNC : std_logic_vector(C_SIZE-1 downto 0);
+        signal BUFG_GT_CLRSYNC  : std_logic_vector(C_SIZE-1 downto 0);
+   begin
+       GEN_BUFG_GT_SYNC : for i in 0 to C_SIZE-1 generate
+            BUFG_GT_SYNC_U : BUFG_GT_SYNC
+             port map (
+                  CE         => BUFG_GT_CE(i),
+                  CESYNC     => BUFG_GT_CESYNC(i),
+                  CLR        => BUFG_GT_CLR(i),
+                  CLRSYNC    => BUFG_GT_CLRSYNC(i),
+                  CLK        => BUFG_GT_I(i)
+              );
+          
+        end generate GEN_BUFG_GT_SYNC;
+        
+        GEN_BUFG_GT : for i in 0 to C_SIZE-1 generate
+
+          BUFG_GT_U : BUFG_GT
+           port map (
+                  O          => BUFG_GT_O(i),
+                  CE         => BUFG_GT_CESYNC(i),
+                  CEMASK     => BUFG_GT_CEMASK(i),
+                  CLR        => BUFG_GT_CLRSYNC(i),
+                  CLRMASK    => BUFG_GT_CLRMASK(i),
+                  DIV        => BUFG_GT_DIV((3*i)+2 downto 3*i),
+                  I          => BUFG_GT_I(i)
+               );
+
+        end generate GEN_BUFG_GT;
+        
+  end generate USE_BUFG_GT_WITH_SYNC;
+
+  USE_BUFG_GT : if (BUFFER_TYPE = "bufg_gt" and C_BUFG_GT_SYNC = 0) generate
+      GEN_BUFG_GT : for i in 0 to C_SIZE-1 generate
+
+          BUFG_GT_U : BUFG_GT
+           port map (
+                  O          => BUFG_GT_O(i),
+                  CE         => BUFG_GT_CE(i),
+                  CEMASK     => BUFG_GT_CEMASK(i),
+                  CLR        => BUFG_GT_CLR(i),
+                  CLRMASK    => BUFG_GT_CLRMASK(i),
+                  DIV        => BUFG_GT_DIV((3*i)+2 downto 3*i),
+                  I          => BUFG_GT_I(i)
+               );
+
+        end generate GEN_BUFG_GT;
+   end generate USE_BUFG_GT;
+
+
+  -- OBUFDS_GTE3: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTE3 : if (BUFFER_TYPE = "obufds_gte3") generate
+    
+      GEN_OBUFDS_GTE3  : for i in 0 to C_SIZE-1 generate
+         OBUFDS_GTE3_U :  OBUFDS_GTE3
+
+        generic map (
+          REFCLK_EN_TX_PATH => BIT1, --'0', 
+          REFCLK_ICNTL_TX   => C_REFCLK_ICNTL_TX
+        )
+        port map (
+          O   => OBUFDS_GTE3_O(i), 
+          OB  => OBUFDS_GTE3_OB(i), 
+          CEB => OBUFDS_GTE3_CEB(i), 
+          I   => OBUFDS_GTE3_I(i) 
+        );
+
+         end generate GEN_OBUFDS_GTE3;
+       end generate USE_OBUFDS_GTE3;
+
+
+
+  -- End of OBUFDS_GTE3_inst instantiation
+
+
+  -- OBUFDS_GTE3_ADV: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTE3_ADV : if (BUFFER_TYPE = "obufds_gte3_adv") generate
+    
+      GEN_OBUFDS_GTE3_ADV : for i in 0 to C_SIZE-1 generate
+        OBUFDS_GTE3_U_ADV :  OBUFDS_GTE3_ADV
+
+        generic map (
+          REFCLK_EN_TX_PATH => BIT1, --'0', 
+          REFCLK_ICNTL_TX   => C_REFCLK_ICNTL_TX
+        )
+        port map (
+          O            => OBUFDS_GTE3_ADV_O(i), 
+          OB           => OBUFDS_GTE3_ADV_OB(i), 
+          CEB          => OBUFDS_GTE3_ADV_CEB(i), 
+          I            => OBUFDS_GTE3_ADV_I((4*i)+3 downto (4*i)),
+          RXRECCLK_SEL => RXRECCLK_SEL_GTE3_ADV((2*i)+1 downto (2*i)) 
+        );
+
+
+         end generate GEN_OBUFDS_GTE3_ADV;
+       end generate USE_OBUFDS_GTE3_ADV;
+
+
+  -- End of OBUFDS_GTE3_ADV_inst instantiation
+
+
+  -- OBUFDS_GTE4: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTE4 : if (BUFFER_TYPE = "obufds_gte4") generate
+    
+      GEN_OBUFDS_GTE4  : for i in 0 to C_SIZE-1 generate
+         OBUFDS_GTE4_U :  OBUFDS_GTE4
+
+        generic map (
+          REFCLK_EN_TX_PATH => BIT1, --'0', 
+          REFCLK_ICNTL_TX   => C_REFCLK_ICNTL_TX
+        )
+        port map (
+          O   => OBUFDS_GTE4_O(i), 
+          OB  => OBUFDS_GTE4_OB(i), 
+          CEB => OBUFDS_GTE4_CEB(i), 
+          I   => OBUFDS_GTE4_I(i) 
+        );
+
+         end generate GEN_OBUFDS_GTE4;
+       end generate USE_OBUFDS_GTE4;
+
+  -- End of OBUFDS_GTE4_inst instantiation
+
+  -- OBUFDS_GTE4_ADV: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTE4_ADV : if (BUFFER_TYPE = "obufds_gte4_adv") generate
+    
+      GEN_OBUFDS_GTE4_ADV  : for i in 0 to C_SIZE-1 generate
+         OBUFDS_GTE4_ADV_U :  OBUFDS_GTE4_ADV
+
+        generic map (
+          REFCLK_EN_TX_PATH => BIT1, --'0', 
+          REFCLK_ICNTL_TX   => C_REFCLK_ICNTL_TX
+        )
+        port map (
+          O            => OBUFDS_GTE4_ADV_O(i), 
+          OB           => OBUFDS_GTE4_ADV_OB(i), 
+          CEB          => OBUFDS_GTE4_ADV_CEB(i), 
+          I            => OBUFDS_GTE4_ADV_I((4*i)+3 downto (4*i)),
+          RXRECCLK_SEL => RXRECCLK_SEL_GTE4_ADV((2*i)+1 downto 2*i) 
+        );
+
+         end generate GEN_OBUFDS_GTE4_ADV;
+       end generate USE_OBUFDS_GTE4_ADV;
+
+  -- End of OBUFDS_GTE4_ADV_inst inOBUFDS_GTEstantiation
+
+
+
+  -- IBUFDS_GTME5: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_IBUFDS_GTME5 : if (BUFFER_TYPE = "ibufds_gtme5") generate
+    
+      GEN_IBUFDS_GTME5  : for i in 0 to C_SIZE-1 generate
+         IBUFDS_GTME5_U :  IBUFDS_GTME5
+
+        generic map (
+          REFCLK_CTL_DRV_SWING => BIT3, --"010",
+          REFCLK_EN_DRV        => BIT1, --'0',
+          REFCLK_EN_TX_PATH    => BIT1, --'0',
+          REFCLK_HROW_CK_SEL   => 0,
+          REFCLK_ICNTL_RX      => 0
+        )
+        port map (
+          O            => IBUFDS_GTME5_O(i), 
+          ODIV2        => IBUFDS_GTME5_ODIV2(i), 
+          IB           => IBUFDS_GTME5_IB(i), 
+          CEB          => IBUFDS_GTME5_CEB(i), 
+          I            => IBUFDS_GTME5_I(i)
+        );
+
+         end generate GEN_IBUFDS_GTME5;
+       end generate USE_IBUFDS_GTME5;
+
+  -- End of IBUFDS_GTME5_inst instantiation
+
+  -- IBUFDS_GTM: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_IBUFDS_GTM : if (BUFFER_TYPE = "ibufds_gtm") generate
+    
+      GEN_IBUFDS_GTM  : for i in 0 to C_SIZE-1 generate
+         IBUFDS_GTM_U :  IBUFDS_GTM
+
+        generic map (
+          REFCLK_EN_TX_PATH  => BIT1, --'0',
+          REFCLK_HROW_CK_SEL => 0,
+          REFCLK_ICNTL_RX    => 0
+        )
+        port map (
+          O            => IBUFDS_GTM_O(i), 
+          ODIV2        => IBUFDS_GTM_ODIV2(i), 
+          IB           => IBUFDS_GTM_IB(i), 
+          CEB          => IBUFDS_GTM_CEB(i), 
+          I            => IBUFDS_GTM_I(i)
+        );
+
+         end generate GEN_IBUFDS_GTM;
+       end generate USE_IBUFDS_GTM;
+
+  -- End of IBUFDS_GTM_inst instantiation
+
+
+  -- OBUFDS_GTM: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTM : if (BUFFER_TYPE = "obufds_gtm") generate
+    
+      GEN_OBUFDS_GTM  : for i in 0 to C_SIZE-1 generate
+         OBUFDS_GTM_U :  OBUFDS_GTM
+
+        generic map (
+          REFCLK_EN_TX_PATH  => BIT1 --'0'
+                 )
+        port map (
+          O            => OBUFDS_GTM_O(i), 
+          OB           => OBUFDS_GTM_OB(i), 
+          CEB          => OBUFDS_GTM_CEB(i), 
+          I            => OBUFDS_GTM_I(i)
+        );
+
+         end generate GEN_OBUFDS_GTM;
+       end generate USE_OBUFDS_GTM;
+
+
+  -- End of IBUFDS_GTM_inst instantiation
+
+  -- OBUFDS_GTM_ADV: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTM_ADV : if (BUFFER_TYPE = "obufds_gtm_adv") generate
+    
+      GEN_OBUFDS_GTM_ADV  : for i in 0 to C_SIZE-1 generate
+         OBUFDS_GTM_ADV_U :  OBUFDS_GTM_ADV
+
+        generic map (
+          REFCLK_EN_TX_PATH  => BIT1, --'0',
+          REFCLK_ICNTL_TX    => 0,
+          RXRECCLK_SEL       => BIT2  --"00"
+        )
+        port map (
+          O            => OBUFDS_GTM_ADV_O(i), 
+          OB           => OBUFDS_GTM_ADV_OB(i), 
+          CEB          => OBUFDS_GTM_ADV_CEB(i), 
+          I            => OBUFDS_GTM_ADV_I((4*i)+3 downto (4*i))
+        );
+
+         end generate GEN_OBUFDS_GTM_ADV;
+       end generate USE_OBUFDS_GTM_ADV;
+
+
+  -- End of OBUFDS_GTM_inst instantiation
+
+
+  -- OBUFDS_GTME5: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTME5 : if (BUFFER_TYPE = "obufds_gtme5") generate
+    
+      GEN_OBUFDS_GTME5  : for i in 0 to C_SIZE-1 generate
+         OBUFDS_GTME5_U :  OBUFDS_GTME5
+
+        generic map (
+          REFCLK_EN_TX_PATH  => BIT1 --'0'
+        )
+        port map (
+          O            => OBUFDS_GTME5_O(i), 
+          OB           => OBUFDS_GTME5_OB(i), 
+          CEB          => OBUFDS_GTME5_CEB(i), 
+          I            => OBUFDS_GTME5_I(i)
+        );
+
+         end generate GEN_OBUFDS_GTME5;
+       end generate USE_OBUFDS_GTME5;
+
+
+  -- End of OBUFDS_GTM_inst instantiation
+
+
+  -- OBUFDS_GTME5_ADV: Gigabit Transceiver Buffer
+  -- UltraScale
+  
+  USE_OBUFDS_GTME5_ADV : if (BUFFER_TYPE = "obufds_gtme5_adv") generate
+    
+      GEN_OBUFDS_GTME5_ADV  : for i in 0 to C_SIZE-1 generate
+         OBUFDS_GTME5_ADV_U : OBUFDS_GTME5_ADV
+
+        generic map (
+          REFCLK_EN_TX_PATH  => BIT1, --'0',
+          RXRECCLK_SEL       => BIT2  -- "00"   -- integer
+        )
+        port map (
+          O            => OBUFDS_GTME5_ADV_O(i), 
+          OB           => OBUFDS_GTME5_ADV_OB(i), 
+          CEB          => OBUFDS_GTME5_ADV_CEB(i), 
+          I            => OBUFDS_GTME5_ADV_I((4*i)+3 downto (4*i))
+        );
+
+         end generate GEN_OBUFDS_GTME5_ADV;
+       end generate USE_OBUFDS_GTME5_ADV;
+
+
+  -- End of OBUFDS_GTM_inst instantiation
+
+end IMP;

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_axi_basic_rx.v

@@ -0,0 +1,212 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_axi_basic_rx.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN to AXI RX module. Instantiates pipeline and null generator RX         //
+//  submodules.                                                               //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_rx                                                          //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_axi_basic_rx #(
+  parameter C_DATA_WIDTH  = 128,          // RX/TX interface data width
+  parameter C_FAMILY      = "X7",         // Targeted FPGA family
+  parameter C_ROOT_PORT   = "FALSE",      // PCIe block is in root port mode
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI RX
+  //-----------
+  output  [C_DATA_WIDTH-1:0] m_axis_rx_tdata,        // RX data to user
+  output                     m_axis_rx_tvalid,       // RX data is valid
+  input                      m_axis_rx_tready,       // RX ready for data
+  output    [KEEP_WIDTH-1:0] m_axis_rx_tkeep,        // RX strobe byte enables
+  output                     m_axis_rx_tlast,        // RX data is last
+  output              [21:0] m_axis_rx_tuser,        // RX user signals
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN RX
+  //-----------
+  input  [C_DATA_WIDTH-1:0] trn_rd,                  // RX data from block
+  input                     trn_rsof,                // RX start of packet
+  input                     trn_reof,                // RX end of packet
+  input                     trn_rsrc_rdy,            // RX source ready
+  output                    trn_rdst_rdy,            // RX destination ready
+  input                     trn_rsrc_dsc,            // RX source discontinue
+  input     [REM_WIDTH-1:0] trn_rrem,                // RX remainder
+  input                     trn_rerrfwd,             // RX error forward
+  input               [6:0] trn_rbar_hit,            // RX BAR hit
+  input                     trn_recrc_err,           // RX ECRC error
+
+  // System
+  //-----------
+  output              [2:0] np_counter,              // Non-posted counter
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+
+// Wires
+wire                  null_rx_tvalid;
+wire                  null_rx_tlast;
+wire [KEEP_WIDTH-1:0] null_rx_tkeep;
+wire                  null_rdst_rdy;
+wire            [4:0] null_is_eof;
+
+//---------------------------------------------//
+// RX Data Pipeline                            //
+//---------------------------------------------//
+
+design_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_FAMILY( C_FAMILY ),
+  .TCQ( TCQ ),
+
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+
+) rx_pipeline_inst (
+
+  // Outgoing AXI TX
+  //-----------
+  .m_axis_rx_tdata( m_axis_rx_tdata ),
+  .m_axis_rx_tvalid( m_axis_rx_tvalid ),
+  .m_axis_rx_tready( m_axis_rx_tready ),
+  .m_axis_rx_tkeep( m_axis_rx_tkeep ),
+  .m_axis_rx_tlast( m_axis_rx_tlast ),
+  .m_axis_rx_tuser( m_axis_rx_tuser ),
+
+  // Incoming TRN RX
+  //-----------
+  .trn_rd( trn_rd ),
+  .trn_rsof( trn_rsof ),
+  .trn_reof( trn_reof ),
+  .trn_rsrc_rdy( trn_rsrc_rdy ),
+  .trn_rdst_rdy( trn_rdst_rdy ),
+  .trn_rsrc_dsc( trn_rsrc_dsc ),
+  .trn_rrem( trn_rrem ),
+  .trn_rerrfwd( trn_rerrfwd ),
+  .trn_rbar_hit( trn_rbar_hit ),
+  .trn_recrc_err( trn_recrc_err ),
+
+  // Null Inputs
+  //-----------
+  .null_rx_tvalid( null_rx_tvalid ),
+  .null_rx_tlast( null_rx_tlast ),
+  .null_rx_tkeep( null_rx_tkeep ),
+  .null_rdst_rdy( null_rdst_rdy ),
+  .null_is_eof( null_is_eof ),
+
+  // System
+  //-----------
+  .np_counter( np_counter ),
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+
+ //---------------------------------------------//
+ // RX Null Packet Generator                    //
+ //---------------------------------------------//
+
+design_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .TCQ( TCQ ),
+
+  .KEEP_WIDTH( KEEP_WIDTH )
+
+ ) rx_null_gen_inst (
+
+  // Inputs
+  //-----------
+  .m_axis_rx_tdata( m_axis_rx_tdata ),
+  .m_axis_rx_tvalid( m_axis_rx_tvalid ),
+  .m_axis_rx_tready( m_axis_rx_tready ),
+  .m_axis_rx_tlast( m_axis_rx_tlast ),
+  .m_axis_rx_tuser( m_axis_rx_tuser ),
+
+  // Null Outputs
+  //-----------
+  .null_rx_tvalid( null_rx_tvalid ),
+  .null_rx_tlast( null_rx_tlast ),
+  .null_rx_tkeep( null_rx_tkeep ),
+  .null_rdst_rdy( null_rdst_rdy ),
+  .null_is_eof( null_is_eof ),
+
+  // System
+  //-----------
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+ );
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.v

@@ -0,0 +1,383 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN to AXI RX null generator. Generates null packets for use in           //
+//  discontinue situations.                                                   //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_rx                                                          //
+//        axi_basic_rx_null_gen                                               //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen # (
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8            // KEEP width
+  ) (
+
+  // AXI RX
+  //-----------
+  input      [C_DATA_WIDTH-1:0] m_axis_rx_tdata,     // RX data to user
+  input                         m_axis_rx_tvalid,    // RX data is valid
+  input                         m_axis_rx_tready,    // RX ready for data
+  input                         m_axis_rx_tlast,     // RX data is last
+  input                  [21:0] m_axis_rx_tuser,     // RX user signals
+
+  // Null Inputs
+  //-----------
+  output                        null_rx_tvalid,      // NULL generated tvalid
+  output                        null_rx_tlast,       // NULL generated tlast
+  output       [KEEP_WIDTH-1:0] null_rx_tkeep,       // NULL generated tkeep
+  output                        null_rdst_rdy,       // NULL generated rdst_rdy
+  output reg              [4:0] null_is_eof,         // NULL generated is_eof
+
+  // System
+  //-----------
+  input                         user_clk,            // user clock from block
+  input                         user_rst             // user reset from block
+);
+
+
+localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
+                                           (C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
+
+//----------------------------------------------------------------------------//
+// NULL packet generator state machine                                        //
+// This state machine shadows the AXI RX interface, tracking each packet as   //
+// it's passed to the AXI user. When a multi-cycle packet is detected, the    //
+// state machine automatically generates a "null" packet. In the event of a   //
+// discontinue, the RX pipeline can switch over to this null packet as        //
+// necessary.                                                                 //
+//----------------------------------------------------------------------------//
+
+// State machine variables and states
+localparam            IDLE      = 0;
+localparam            IN_PACKET = 1;
+reg                   cur_state;
+reg                   next_state;
+
+// Signals for tracking a packet on the AXI interface
+reg            [11:0] reg_pkt_len_counter;
+reg            [11:0] pkt_len_counter;
+wire           [11:0] pkt_len_counter_dec;
+wire                  pkt_done;
+
+// Calculate packet fields, which are needed to determine total packet length.
+wire           [11:0] new_pkt_len;
+wire            [9:0] payload_len;
+wire            [1:0] packet_fmt;
+wire                  packet_td;
+reg             [3:0] packet_overhead;
+
+// Misc.
+wire [KEEP_WIDTH-1:0] eof_tkeep;
+wire                  straddle_sof;
+wire                  eof;
+
+
+// Create signals to detect sof and eof situations. These signals vary depending
+// on data width.
+assign eof = m_axis_rx_tuser[21];
+generate
+  if(C_DATA_WIDTH == 128) begin : sof_eof_128
+    assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
+  end
+  else begin : sof_eof_64_32
+    assign straddle_sof = 1'b0;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Calculate the length of the packet being presented on the RX interface. To //
+// do so, we need the relevent packet fields that impact total packet length. //
+// These are:                                                                 //
+//   - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
+//   - Payload length: obtained from LENGTH field in 1st DWORD of header      //
+//   - TLP digest: obtained from TD field in 1st DWORD of header              //
+//   - Current data: the number of bytes that have already been presented     //
+//                   on the data interface                                    //
+//                                                                            //
+// packet length = header + payload + tlp digest - # of DWORDS already        //
+//                 transmitted                                                //
+//                                                                            //
+// packet_overhead is where we calculate everything except payload.           //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : len_calc_128
+    assign packet_fmt  = straddle_sof ?
+                                m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
+    assign packet_td   = straddle_sof ?
+                                      m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
+    assign payload_len = packet_fmt[1] ?
+         (straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
+
+    always @(*) begin
+      // In 128-bit mode, the amount of data currently on the interface
+      // depends on whether we're straddling or not. If so, 2 DWORDs have been
+      // seen. If not, 4 DWORDs.
+      case({packet_fmt[0], packet_td, straddle_sof})
+        //                        Header +  TD  - Data currently on interface
+        3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
+        3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
+        3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
+        3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
+        3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
+        3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
+        3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
+        3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
+      endcase
+    end
+assign new_pkt_len =
+         {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
+  end
+  else if(C_DATA_WIDTH == 64) begin : len_calc_64
+    assign packet_fmt  = m_axis_rx_tdata[30:29];
+    assign packet_td   = m_axis_rx_tdata[15];
+    assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
+
+    always @(*) begin
+      // 64-bit mode: no straddling, so always 2 DWORDs
+      case({packet_fmt[0], packet_td})
+        //                      Header +  TD  - Data currently on interface
+        2'b0_0: packet_overhead[1:0] = 2'b01 ;//4'd3 + 4'd0 - 4'd2; // 1
+        2'b0_1: packet_overhead[1:0] = 2'b10 ;//4'd3 + 4'd1 - 4'd2; // 2
+        2'b1_0: packet_overhead[1:0] = 2'b10 ;//4'd4 + 4'd0 - 4'd2; // 2 
+        2'b1_1: packet_overhead[1:0] = 2'b11 ;//4'd4 + 4'd1 - 4'd2; // 3
+      endcase
+    end
+assign new_pkt_len =
+         {{10{1'b0}}, packet_overhead[1:0]} + {2'b0, payload_len};
+  end
+  else begin : len_calc_32
+    assign packet_fmt  = m_axis_rx_tdata[30:29];
+    assign packet_td   = m_axis_rx_tdata[15];
+    assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
+
+    always @(*) begin
+      // 32-bit mode: no straddling, so always 1 DWORD
+      case({packet_fmt[0], packet_td})
+        //                      Header +  TD  - Data currently on interface
+        2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
+        2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
+        2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
+        2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
+      endcase
+    end
+assign new_pkt_len =
+         {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
+  end
+endgenerate
+
+// Now calculate actual packet length, adding the packet overhead and the
+// payload length. This is signed math, so sign-extend packet_overhead.
+// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
+//       behavior isn't supported in our block.
+//assign new_pkt_len =
+//         {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
+
+
+// Math signals needed in the state machine below. These are seperate wires to
+// help ensure synthesis tools sre smart about optimizing them.
+assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
+assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
+
+//----------------------------------------------------------------------------//
+// Null generator Mealy state machine. Determine outputs based on:            //
+//   1) current st                                                            //
+//   2) current inp                                                           //
+//----------------------------------------------------------------------------//
+always @(*) begin
+  case (cur_state)
+
+    // IDLE state: the interface is IDLE and we're waiting for a packet to
+    // start. If a packet starts, move to state IN_PACKET and begin tracking
+    // it as long as it's NOT a single cycle packet (indicated by assertion of
+    // eof at packet start)
+    IDLE: begin
+      if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
+        next_state = IN_PACKET;
+      end
+      else begin
+        next_state = IDLE;
+      end
+
+      pkt_len_counter = new_pkt_len;
+    end
+
+    // IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
+    // are in lock-step with the AXI interface decrementing our packet length
+    // tracking reg, and waiting for the packet to finish.
+    //
+    // * If packet finished and a new one starts, this is a straddle situation.
+    //   Next state is IN_PACKET (128-bit only).
+    // * If the current packet is done, next state is IDLE.
+    // * Otherwise, next state is IN_PACKET.
+    IN_PACKET: begin
+      // Straddle packet
+      if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
+        pkt_len_counter = new_pkt_len;
+        next_state = IN_PACKET;
+      end
+
+      // Current packet finished
+      else if(m_axis_rx_tready && pkt_done)
+      begin
+        pkt_len_counter = new_pkt_len;
+        next_state      = IDLE;
+      end
+
+      // Packet in progress
+      else begin
+        if(m_axis_rx_tready) begin
+          // Not throttled
+          pkt_len_counter = pkt_len_counter_dec;
+        end
+        else begin
+          // Throttled
+          pkt_len_counter = reg_pkt_len_counter;
+        end
+
+        next_state = IN_PACKET;
+      end
+    end
+
+    default: begin
+      pkt_len_counter = reg_pkt_len_counter;
+      next_state      = IDLE;
+    end
+  endcase
+end
+
+
+// Synchronous NULL packet generator state machine logic
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    cur_state           <= #TCQ IDLE;
+    reg_pkt_len_counter <= #TCQ 12'h0;
+  end
+  else begin
+    cur_state           <= #TCQ next_state;
+    reg_pkt_len_counter <= #TCQ pkt_len_counter;
+  end
+end
+
+
+// Generate tkeep/is_eof for an end-of-packet situation.
+generate
+  if(C_DATA_WIDTH == 128) begin : strb_calc_128
+    always @(*) begin
+      // Assign null_is_eof depending on how many DWORDs are left in the
+      // packet.
+      case(pkt_len_counter)
+        10'd1:   null_is_eof = 5'b10011;
+        10'd2:   null_is_eof = 5'b10111;
+        10'd3:   null_is_eof = 5'b11011;
+        10'd4:   null_is_eof = 5'b11111;
+        default: null_is_eof = 5'b00011;
+      endcase
+    end
+
+    // tkeep not used in 128-bit interface
+    assign eof_tkeep = {KEEP_WIDTH{1'b0}};
+  end
+  else if(C_DATA_WIDTH == 64) begin : strb_calc_64
+    always @(*) begin
+      // Assign null_is_eof depending on how many DWORDs are left in the
+      // packet.
+      case(pkt_len_counter)
+        10'd1:   null_is_eof = 5'b10011;
+        10'd2:   null_is_eof = 5'b10111;
+        default: null_is_eof = 5'b00011;
+      endcase
+    end
+
+    // Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
+    // the current packet.
+    assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
+  end
+  else begin : strb_calc_32
+    always @(*) begin
+      // is_eof is either on or off for 32-bit
+      if(pkt_len_counter == 12'd1) begin
+        null_is_eof = 5'b10011;
+      end
+      else begin
+        null_is_eof = 5'b00011;
+      end
+    end
+
+    // The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
+    assign eof_tkeep = 4'hF;
+  end
+endgenerate
+
+
+// Finally, use everything we've generated to calculate our NULL outputs
+assign null_rx_tvalid = 1'b1;
+assign null_rx_tlast  = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
+assign null_rx_tkeep  = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
+assign null_rdst_rdy  = null_rx_tlast;
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.v

@@ -0,0 +1,623 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI.  //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_rx                                                          //
+//        axi_basic_rx_pipeline                                               //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline #(
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter C_FAMILY     = "X7",          // Targeted FPGA family
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+
+  // AXI RX
+  //-----------
+  output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata,     // RX data to user
+  output reg                    m_axis_rx_tvalid,    // RX data is valid
+  input                         m_axis_rx_tready,    // RX ready for data
+  output       [KEEP_WIDTH-1:0] m_axis_rx_tkeep,     // RX strobe byte enables
+  output                        m_axis_rx_tlast,     // RX data is last
+  output reg             [21:0] m_axis_rx_tuser,     // RX user signals
+
+  // TRN RX
+  //-----------
+  input      [C_DATA_WIDTH-1:0] trn_rd,              // RX data from block
+  input                         trn_rsof,            // RX start of packet
+  input                         trn_reof,            // RX end of packet
+  input                         trn_rsrc_rdy,        // RX source ready
+  output reg                    trn_rdst_rdy,        // RX destination ready
+  input                         trn_rsrc_dsc,        // RX source discontinue
+  input         [REM_WIDTH-1:0] trn_rrem,            // RX remainder
+  input                         trn_rerrfwd,         // RX error forward
+  input                   [6:0] trn_rbar_hit,        // RX BAR hit
+  input                         trn_recrc_err,       // RX ECRC error
+
+  // Null Inputs
+  //-----------
+  input                         null_rx_tvalid,      // NULL generated tvalid
+  input                         null_rx_tlast,       // NULL generated tlast
+  input        [KEEP_WIDTH-1:0] null_rx_tkeep,       // NULL generated tkeep
+  input                         null_rdst_rdy,       // NULL generated rdst_rdy
+  input                   [4:0] null_is_eof,         // NULL generated is_eof
+
+  // System
+  //-----------
+  output                  [2:0] np_counter,          // Non-posted counter
+  input                         user_clk,            // user clock from block
+  input                         user_rst             // user reset from block
+);
+
+
+// Wires and regs for creating AXI signals
+wire              [4:0] is_sof;
+wire              [4:0] is_sof_prev;
+
+wire              [4:0] is_eof;
+wire              [4:0] is_eof_prev;
+
+reg    [KEEP_WIDTH-1:0] reg_tkeep;
+wire   [KEEP_WIDTH-1:0] tkeep;
+wire   [KEEP_WIDTH-1:0] tkeep_prev;
+
+reg                     reg_tlast;
+wire                    rsrc_rdy_filtered;
+
+// Wires and regs for previous value buffer
+wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
+reg  [C_DATA_WIDTH-1:0] trn_rd_prev;
+
+wire                    data_hold;
+reg                     data_prev;
+
+reg                     trn_reof_prev;
+reg     [REM_WIDTH-1:0] trn_rrem_prev;
+reg                     trn_rsrc_rdy_prev;
+reg                     trn_rsrc_dsc_prev;
+reg                     trn_rsof_prev;
+reg               [6:0] trn_rbar_hit_prev;
+reg                     trn_rerrfwd_prev;
+reg                     trn_recrc_err_prev;
+
+// Null packet handling signals
+reg                     null_mux_sel;
+reg                     trn_in_packet;
+wire                    dsc_flag;
+wire                    dsc_detect;
+reg                     reg_dsc_detect;
+reg                     trn_rsrc_dsc_d;
+
+
+// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
+assign rsrc_rdy_filtered = trn_rsrc_rdy &&
+                                 (trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
+
+//----------------------------------------------------------------------------//
+// Previous value buffer                                                      //
+// ---------------------                                                      //
+// We are inserting a pipeline stage in between TRN and AXI, which causes     //
+// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The    //
+// added cycle of latency in the path causes the user design to fall behind   //
+// the TRN interface whenever it throttles.                                   //
+//                                                                            //
+// To avoid loss of data, we must keep the previous value of all trn_r*       //
+// signals in case the user throttles.                                        //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_rd_prev        <= #TCQ {C_DATA_WIDTH{1'b0}};
+    trn_rsof_prev      <= #TCQ 1'b0;
+    trn_rrem_prev      <= #TCQ {REM_WIDTH{1'b0}};
+    trn_rsrc_rdy_prev  <= #TCQ 1'b0;
+    trn_rbar_hit_prev  <= #TCQ 7'h00;
+    trn_rerrfwd_prev   <= #TCQ 1'b0;
+    trn_recrc_err_prev <= #TCQ 1'b0;
+    trn_reof_prev      <= #TCQ 1'b0;
+    trn_rsrc_dsc_prev  <= #TCQ 1'b0;
+  end
+  else begin
+    // prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
+    // asserted, a new value is present on the interface.
+    if(trn_rdst_rdy) begin
+      trn_rd_prev        <= #TCQ trn_rd_DW_swapped;
+      trn_rsof_prev      <= #TCQ trn_rsof;
+      trn_rrem_prev      <= #TCQ trn_rrem;
+      trn_rbar_hit_prev  <= #TCQ trn_rbar_hit;
+      trn_rerrfwd_prev   <= #TCQ trn_rerrfwd;
+      trn_recrc_err_prev <= #TCQ trn_recrc_err;
+      trn_rsrc_rdy_prev  <= #TCQ rsrc_rdy_filtered;
+      trn_reof_prev      <= #TCQ trn_reof;
+      trn_rsrc_dsc_prev  <= #TCQ trn_rsrc_dsc || dsc_flag;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create TDATA                                                               //
+//----------------------------------------------------------------------------//
+
+// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
+// 128-bit:                 64-bit:                  32-bit:
+// TRN DW0 maps to AXI DW3  TRN DW0 maps to AXI DW1  TNR DW0 maps to AXI DW0
+// TRN DW1 maps to AXI DW2  TRN DW1 maps to AXI DW0
+// TRN DW2 maps to AXI DW1
+// TRN DW3 maps to AXI DW0
+generate
+  if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
+    assign trn_rd_DW_swapped = {trn_rd[31:0],
+                                trn_rd[63:32],
+                                trn_rd[95:64],
+                                trn_rd[127:96]};
+  end
+  else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
+    assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
+  end
+  else begin : rd_DW_swap_32
+    assign trn_rd_DW_swapped = trn_rd;
+  end
+endgenerate
+
+
+// Create special buffer which locks in the proper value of TDATA depending
+// on whether the user is throttling or not. This buffer has three states:
+//
+//       HOLD state: TDATA maintains its current value
+//                   - the user has throttled the PCIe block
+//   PREVIOUS state: the buffer provides the previous value on trn_rd
+//                   - the user has finished throttling, and is a little behind
+//                     the PCIe block
+//    CURRENT state: the buffer passes the current value on trn_rd
+//                   - the user is caught up and ready to receive the latest
+//                     data from the PCIe block
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
+  end
+  else begin
+    if(!data_hold) begin
+      // PREVIOUS state
+      if(data_prev) begin
+        m_axis_rx_tdata <= #TCQ trn_rd_prev;
+      end
+
+      // CURRENT state
+      else begin
+        m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
+      end
+    end
+    // else HOLD state
+  end
+end
+
+// Logic to instruct pipeline to hold its value
+assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
+
+// Logic to instruct pipeline to use previous bus values. Always use previous
+// value after holding a value.
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    data_prev <= #TCQ 1'b0;
+  end
+  else begin
+    data_prev <= #TCQ data_hold;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create TVALID, TLAST, tkeep, TUSER                                         //
+// -----------------------------------                                        //
+// Use the same strategy for these signals as for TDATA, except here we need  //
+// an extra provision for null packets.                                       //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    m_axis_rx_tvalid <= #TCQ 1'b0;
+    reg_tlast        <= #TCQ 1'b0;
+    reg_tkeep        <= #TCQ {KEEP_WIDTH{1'b1}};
+    m_axis_rx_tuser  <= #TCQ 22'h0;
+  end
+  else begin
+    if(!data_hold) begin
+      // If in a null packet, use null generated value
+      if(null_mux_sel) begin
+        m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
+        reg_tlast        <= #TCQ null_rx_tlast;
+        reg_tkeep        <= #TCQ null_rx_tkeep;
+        m_axis_rx_tuser  <= #TCQ {null_is_eof, 17'h0000};
+      end
+
+      // PREVIOUS state
+      else if(data_prev) begin
+        m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
+        reg_tlast        <= #TCQ trn_reof_prev;
+        reg_tkeep        <= #TCQ tkeep_prev;
+        m_axis_rx_tuser  <= #TCQ {is_eof_prev,          // TUSER bits [21:17]
+                                  2'b00,                // TUSER bits [16:15]
+                                  is_sof_prev,          // TUSER bits [14:10]
+                                  1'b0,                 // TUSER bit  [9]
+                                  trn_rbar_hit_prev,    // TUSER bits [8:2]
+                                  trn_rerrfwd_prev,     // TUSER bit  [1]
+                                  trn_recrc_err_prev};  // TUSER bit  [0]
+      end
+
+      // CURRENT state
+      else begin
+        m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
+        reg_tlast        <= #TCQ trn_reof;
+        reg_tkeep        <= #TCQ tkeep;
+        m_axis_rx_tuser  <= #TCQ {is_eof,               // TUSER bits [21:17]
+                                  2'b00,                // TUSER bits [16:15]
+                                  is_sof,               // TUSER bits [14:10]
+                                  1'b0,                 // TUSER bit  [9]
+                                  trn_rbar_hit,         // TUSER bits [8:2]
+                                  trn_rerrfwd,          // TUSER bit  [1]
+                                  trn_recrc_err};       // TUSER bit  [0]
+      end
+    end
+    // else HOLD state
+  end
+end
+
+// Hook up TLAST and tkeep depending on interface width
+generate
+  // For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
+  // is_data passed to user instead). reg_tlast is still used internally.
+  if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
+    assign m_axis_rx_tlast = 1'b0;
+    assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
+  end
+
+  // For 64/32-bit interface, pass TLAST to user.
+  else begin : tlast_tkeep_hookup_64_32
+    assign m_axis_rx_tlast = reg_tlast;
+    assign m_axis_rx_tkeep = reg_tkeep;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create tkeep                                                               //
+// ------------                                                               //
+// Convert RREM to STRB. Here, we are converting the encoding method for the  //
+// location of the EOF from TRN flavor (rrem) to AXI (tkeep).                 //
+//                                                                            //
+// NOTE: for each configuration, we need two values of tkeep, the current and //
+//       previous values. The need for these two values is described below.   //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
+    // TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
+    // instead.
+    assign tkeep      = 16'h0000;
+    assign tkeep_prev = 16'h0000;
+  end
+  else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
+    // 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
+    //  - tkeep has only two possible values here, 0xFF or 0x0F
+    assign tkeep      = trn_rrem      ? 8'hFF : 8'h0F;
+    assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
+  end
+  else begin : rrem_to_tkeep_32
+    // 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
+    //  - tkeep is always 0xF in this case, due to the nature of the PCIe block
+    assign tkeep      = 4'hF;
+    assign tkeep_prev = 4'hF;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create is_sof                                                              //
+// -------------                                                              //
+// is_sof is a signal to the user indicating the location of SOF in TDATA   . //
+// Due to inherent 64-bit alignment of packets from the block, the only       //
+// possible values are:                                                       //
+//                      Value                      Valid data widths          //
+//                      5'b11000 (sof @ byte 8)    128                        //
+//                      5'b10000 (sof @ byte 0)    128, 64, 32                //
+//                      5'b00000 (sof not present) 128, 64, 32                //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : is_sof_128
+    assign is_sof      = {(trn_rsof && !trn_rsrc_dsc), // bit 4:   enable
+                          (trn_rsof && !trn_rrem[1]),  // bit 3:   sof @ byte 8?
+                          3'b000};                     // bit 2-0: hardwired 0
+
+    assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
+                          (trn_rsof_prev && !trn_rrem_prev[1]),  // bit 3
+                          3'b000};                               // bit 2-0
+  end
+  else begin : is_sof_64_32
+    assign is_sof      = {(trn_rsof && !trn_rsrc_dsc), // bit 4:   enable
+                          4'b0000};                    // bit 3-0: hardwired 0
+
+    assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
+                          4'b0000};                              // bit 3-0
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create is_eof                                                              //
+// -------------                                                              //
+// is_eof is a signal to the user indicating the location of EOF in TDATA   . //
+// Due to DWORD granularity of packets from the block, the only               //
+// possible values are:                                                       //
+//                      Value                      Valid data widths          //
+//                      5'b11111 (eof @ byte 15)   128                        //
+//                      5'b11011 (eof @ byte 11)   128                        //
+//                      5'b10111 (eof @ byte 7)    128, 64                    //
+//                      5'b10011 (eof @ byte 3)`   128, 64, 32                //
+//                      5'b00011 (eof not present) 128, 64, 32                //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : is_eof_128
+    assign is_eof      = {trn_reof,      // bit 4:   enable
+                          trn_rrem,      // bit 3-2: encoded eof loc rom block
+                          2'b11};        // bit 1-0: hardwired 1
+
+    assign is_eof_prev = {trn_reof_prev, // bit 4:   enable
+                          trn_rrem_prev, // bit 3-2: encoded eof loc from block
+                          2'b11};        // bit 1-0: hardwired 1
+  end
+  else if(C_DATA_WIDTH == 64) begin : is_eof_64
+    assign is_eof      = {trn_reof,      // bit 4:   enable
+                          1'b0,          // bit 3:   hardwired 0
+                          trn_rrem,      // bit 2:   encoded eof loc from block
+                          2'b11};        // bit 1-0: hardwired 1
+
+    assign is_eof_prev = {trn_reof_prev, // bit 4:   enable
+                          1'b0,          // bit 3:   hardwired 0
+                          trn_rrem_prev, // bit 2:   encoded eof loc from block
+                          2'b11};        // bit 1-0: hardwired 1
+  end
+  else begin : is_eof_32
+    assign is_eof      = {trn_reof,      // bit 4:   enable
+                          4'b0011};      // bit 3-0: hardwired to byte 3
+
+    assign is_eof_prev = {trn_reof_prev, // bit 4:   enable
+                          4'b0011};      // bit 3-0: hardwired to byte 3
+  end
+endgenerate
+
+
+
+//----------------------------------------------------------------------------//
+// Create trn_rdst_rdy                                                        //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_rdst_rdy <= #TCQ 1'b0;
+  end
+  else begin
+    // If in a null packet, use null generated value
+    if(null_mux_sel && m_axis_rx_tready) begin
+      trn_rdst_rdy <= #TCQ null_rdst_rdy;
+    end
+
+    // If a discontinue needs to be serviced, throttle the block until we are
+    // ready to pad out the packet.
+    else if(dsc_flag) begin
+      trn_rdst_rdy <= #TCQ 1'b0;
+    end
+
+    // If in a packet, pass user back-pressure directly to block
+    else if(m_axis_rx_tvalid) begin
+      trn_rdst_rdy <= #TCQ m_axis_rx_tready;
+    end
+
+    // If idle, default to no back-pressure. We need to default to the
+    // "ready to accept data" state to make sure we catch the first
+    // clock of data of a new packet.
+    else begin
+      trn_rdst_rdy <= #TCQ 1'b1;
+    end
+  end
+end
+
+//----------------------------------------------------------------------------//
+// Create null_mux_sel                                                        //
+// null_mux_sel is the signal used to detect a discontinue situation and      //
+// mux in the null packet generated in rx_null_gen. Only mux in null data     //
+// when not at the beginningof a packet. SOF discontinues do not require      //
+// padding, as the whole packet is simply squashed instead.                   //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    null_mux_sel <= #TCQ 1'b0;
+  end
+  else begin
+    // NULL packet done
+    if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
+    begin
+      null_mux_sel <= #TCQ 1'b0;
+    end
+
+    // Discontinue detected and we're in packet, so switch to NULL packet
+    else if(dsc_flag && !data_hold) begin
+      null_mux_sel <= #TCQ 1'b1;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create discontinue tracking signals                                        //
+//----------------------------------------------------------------------------//
+// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
+// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_in_packet <= #TCQ 1'b0;
+  end
+  else begin
+    if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
+    begin
+      trn_in_packet <= #TCQ 1'b1;
+    end
+    else if(trn_rsrc_dsc) begin
+      trn_in_packet <= #TCQ 1'b0;
+    end
+    else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
+      trn_in_packet <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+// Create dsc_flag, which identifies and stores mid-packet discontinues that
+// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
+// to make sure we don't service the same dsc twice in the event that
+// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
+assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
+                         (!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    reg_dsc_detect <= #TCQ 1'b0;
+    trn_rsrc_dsc_d <= #TCQ 1'b0;
+  end
+  else begin
+    if(dsc_detect) begin
+      reg_dsc_detect <= #TCQ 1'b1;
+    end
+    else if(null_mux_sel) begin
+      reg_dsc_detect <= #TCQ 1'b0;
+    end
+
+    trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
+  end
+end
+
+assign dsc_flag = dsc_detect || reg_dsc_detect;
+
+
+
+//----------------------------------------------------------------------------//
+// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit     //
+// interface core how many NP packets have left the RX pipeline. The V6       //
+// 128-bit interface uses this count to perform rnp_ok modulation.            //
+//----------------------------------------------------------------------------//
+generate
+  if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
+    reg [2:0] reg_np_counter;
+
+    // Look for NP packets beginning on lower (i.e. unaligned) start
+    wire mrd_lower      = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
+    wire mrd_lk_lower   = (m_axis_rx_tdata[92:88] == 5'b00001);
+    wire io_rdwr_lower  = (m_axis_rx_tdata[92:88] == 5'b00010);
+    wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
+    wire atomic_lower   = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
+
+    wire np_pkt_lower = (mrd_lower      ||
+                         mrd_lk_lower   ||
+                         io_rdwr_lower  ||
+                         cfg_rdwr_lower ||
+                         atomic_lower) && m_axis_rx_tuser[13];
+
+    // Look for NP packets beginning on upper (i.e. aligned) start
+    wire mrd_upper      = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
+    wire mrd_lk_upper   = (m_axis_rx_tdata[28:24] == 5'b00001);
+    wire io_rdwr_upper  = (m_axis_rx_tdata[28:24] == 5'b00010);
+    wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
+    wire atomic_upper   = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
+
+    wire np_pkt_upper = (mrd_upper      ||
+                         mrd_lk_upper   ||
+                         io_rdwr_upper  ||
+                         cfg_rdwr_upper ||
+                         atomic_upper) && !m_axis_rx_tuser[13];
+
+    wire pkt_accepted =
+                    m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
+
+    // Increment counter whenever an NP packet leaves the RX pipeline
+    always @(posedge user_clk)  begin
+      if (user_rst) begin
+        reg_np_counter <= #TCQ 0;
+      end
+      else begin
+        if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
+        begin
+          reg_np_counter <= #TCQ reg_np_counter + 3'h1;
+        end
+      end
+    end
+
+    assign np_counter = reg_np_counter;
+  end
+  else begin : np_cntr_to_128_disabled
+    assign np_counter = 3'h0;
+  end
+endgenerate
+
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_axi_basic_top.v

@@ -0,0 +1,282 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_axi_basic_top.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules.       //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_axi_basic_top #(
+  parameter C_DATA_WIDTH  = 128,          // RX/TX interface data width
+  parameter C_FAMILY      = "X7",         // Targeted FPGA family
+  parameter C_ROOT_PORT   = "FALSE",      // PCIe block is in root port mode
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI TX
+  //-----------
+  input   [C_DATA_WIDTH-1:0] s_axis_tx_tdata,        // TX data from user
+  input                      s_axis_tx_tvalid,       // TX data is valid
+  output                     s_axis_tx_tready,       // TX ready for data
+  input     [KEEP_WIDTH-1:0] s_axis_tx_tkeep,        // TX strobe byte enables
+  input                      s_axis_tx_tlast,        // TX data is last
+  input                [3:0] s_axis_tx_tuser,        // TX user signals
+
+  // AXI RX
+  //-----------
+  output  [C_DATA_WIDTH-1:0] m_axis_rx_tdata,        // RX data to user
+  output                     m_axis_rx_tvalid,       // RX data is valid
+  input                      m_axis_rx_tready,       // RX ready for data
+  output    [KEEP_WIDTH-1:0] m_axis_rx_tkeep,        // RX strobe byte enables
+  output                     m_axis_rx_tlast,        // RX data is last
+  output              [21:0] m_axis_rx_tuser,        // RX user signals
+
+  // User Misc.
+  //-----------
+  input                      user_turnoff_ok,        // Turnoff OK from user
+  input                      user_tcfg_gnt,          // Send cfg OK from user
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN TX
+  //-----------
+  output [C_DATA_WIDTH-1:0] trn_td,                  // TX data from block
+  output                    trn_tsof,                // TX start of packet
+  output                    trn_teof,                // TX end of packet
+  output                    trn_tsrc_rdy,            // TX source ready
+  input                     trn_tdst_rdy,            // TX destination ready
+  output                    trn_tsrc_dsc,            // TX source discontinue
+  output    [REM_WIDTH-1:0] trn_trem,                // TX remainder
+  output                    trn_terrfwd,             // TX error forward
+  output                    trn_tstr,                // TX streaming enable
+  input               [5:0] trn_tbuf_av,             // TX buffers available
+  output                    trn_tecrc_gen,           // TX ECRC generate
+
+  // TRN RX
+  //-----------
+  input  [127:0] trn_rd,                  // RX data from block
+  input                     trn_rsof,                // RX start of packet
+  input                     trn_reof,                // RX end of packet
+  input                     trn_rsrc_rdy,            // RX source ready
+  output                    trn_rdst_rdy,            // RX destination ready
+  input                     trn_rsrc_dsc,            // RX source discontinue
+  input     [1:0] trn_rrem,                // RX remainder
+  input                     trn_rerrfwd,             // RX error forward
+  input               [6:0] trn_rbar_hit,            // RX BAR hit
+  input                     trn_recrc_err,           // RX ECRC error
+
+  // TRN Misc.
+  //-----------
+  input                     trn_tcfg_req,            // TX config request
+  output                    trn_tcfg_gnt,            // RX config grant
+  input                     trn_lnk_up,              // PCIe link up
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  input               [2:0] cfg_pcie_link_state,     // Encoded PCIe link state
+
+  // Virtex6 PM
+  //-----------
+  input                     cfg_pm_send_pme_to,      // PM send PME turnoff msg
+  input               [1:0] cfg_pmcsr_powerstate,    // PMCSR power state
+  input              [31:0] trn_rdllp_data,          // RX DLLP data
+  input                     trn_rdllp_src_rdy,       // RX DLLP source ready
+
+  // Virtex6/Spartan6 PM
+  //-----------
+  input                     cfg_to_turnoff,          // Turnoff request
+  output                    cfg_turnoff_ok,          // Turnoff grant
+
+  // System
+  //-----------
+  output              [2:0] np_counter,              // Non-posted counter
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+
+//---------------------------------------------//
+// RX Data Pipeline                            //
+//---------------------------------------------//
+
+design_1_xdma_0_0_pcie2_ip_axi_basic_rx #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_FAMILY( C_FAMILY ),
+
+  .TCQ( TCQ ),
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+) rx_inst (
+
+  // Outgoing AXI TX
+  //-----------
+  .m_axis_rx_tdata( m_axis_rx_tdata ),
+  .m_axis_rx_tvalid( m_axis_rx_tvalid ),
+  .m_axis_rx_tready( m_axis_rx_tready ),
+  .m_axis_rx_tkeep( m_axis_rx_tkeep ),
+  .m_axis_rx_tlast( m_axis_rx_tlast ),
+  .m_axis_rx_tuser( m_axis_rx_tuser ),
+
+  // Incoming TRN RX
+  //-----------
+  .trn_rd( trn_rd[C_DATA_WIDTH-1:0] ),
+  .trn_rsof( trn_rsof ),
+  .trn_reof( trn_reof ),
+  .trn_rsrc_rdy( trn_rsrc_rdy ),
+  .trn_rdst_rdy( trn_rdst_rdy ),
+  .trn_rsrc_dsc( trn_rsrc_dsc ),
+  .trn_rrem( trn_rrem[REM_WIDTH-1:0] ),
+  .trn_rerrfwd( trn_rerrfwd ),
+  .trn_rbar_hit( trn_rbar_hit ),
+  .trn_recrc_err( trn_recrc_err ),
+
+  // System
+  //-----------
+  .np_counter( np_counter ),
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+
+
+//---------------------------------------------//
+// TX Data Pipeline                            //
+//---------------------------------------------//
+
+design_1_xdma_0_0_pcie2_ip_axi_basic_tx #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_FAMILY( C_FAMILY ),
+  .C_ROOT_PORT( C_ROOT_PORT ),
+  .C_PM_PRIORITY( C_PM_PRIORITY ),
+
+  .TCQ( TCQ ),
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+) tx_inst (
+
+  // Incoming AXI RX
+  //-----------
+  .s_axis_tx_tdata( s_axis_tx_tdata ),
+  .s_axis_tx_tvalid( s_axis_tx_tvalid ),
+  .s_axis_tx_tready( s_axis_tx_tready ),
+  .s_axis_tx_tkeep( s_axis_tx_tkeep ),
+  .s_axis_tx_tlast( s_axis_tx_tlast ),
+  .s_axis_tx_tuser( s_axis_tx_tuser ),
+
+  // User Misc.
+  //-----------
+  .user_turnoff_ok( user_turnoff_ok ),
+  .user_tcfg_gnt( user_tcfg_gnt ),
+
+  // Outgoing TRN TX
+  //-----------
+  .trn_td( trn_td ),
+  .trn_tsof( trn_tsof ),
+  .trn_teof( trn_teof ),
+  .trn_tsrc_rdy( trn_tsrc_rdy ),
+  .trn_tdst_rdy( trn_tdst_rdy ),
+  .trn_tsrc_dsc( trn_tsrc_dsc ),
+  .trn_trem( trn_trem ),
+  .trn_terrfwd( trn_terrfwd ),
+  .trn_tstr( trn_tstr ),
+  .trn_tbuf_av( trn_tbuf_av ),
+  .trn_tecrc_gen( trn_tecrc_gen ),
+
+  // TRN Misc.
+  //-----------
+  .trn_tcfg_req( trn_tcfg_req ),
+  .trn_tcfg_gnt( trn_tcfg_gnt ),
+  .trn_lnk_up( trn_lnk_up ),
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  .cfg_pcie_link_state( cfg_pcie_link_state ),
+
+  // Virtex6 PM
+  //-----------
+  .cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
+  .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
+  .trn_rdllp_data( trn_rdllp_data ),
+  .trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
+
+  // Spartan6 PM
+  //-----------
+  .cfg_to_turnoff( cfg_to_turnoff ),
+  .cfg_turnoff_ok( cfg_turnoff_ok ),
+
+  // System
+  //-----------
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_axi_basic_tx.v

@@ -0,0 +1,260 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_axi_basic_tx.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  AXI to TRN TX module. Instantiates pipeline and throttle control TX       //
+//  submodules.                                                               //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_tx                                                          //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_axi_basic_tx #(
+  parameter C_DATA_WIDTH  = 128,          // RX/TX interface data width
+  parameter C_FAMILY      = "X7",         // Targeted FPGA family
+  parameter C_ROOT_PORT   = "FALSE",      // PCIe block is in root port mode
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI TX
+  //-----------
+  input   [C_DATA_WIDTH-1:0] s_axis_tx_tdata,        // TX data from user
+  input                      s_axis_tx_tvalid,       // TX data is valid
+  output                     s_axis_tx_tready,       // TX ready for data
+  input     [KEEP_WIDTH-1:0] s_axis_tx_tkeep,        // TX strobe byte enables
+  input                      s_axis_tx_tlast,        // TX data is last
+  input                [3:0] s_axis_tx_tuser,        // TX user signals
+
+  // User Misc.
+  //-----------
+  input                      user_turnoff_ok,        // Turnoff OK from user
+  input                      user_tcfg_gnt,          // Send cfg OK from user
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN TX
+  //-----------
+  output [C_DATA_WIDTH-1:0] trn_td,                  // TX data from block
+  output                    trn_tsof,                // TX start of packet
+  output                    trn_teof,                // TX end of packet
+  output                    trn_tsrc_rdy,            // TX source ready
+  input                     trn_tdst_rdy,            // TX destination ready
+  output                    trn_tsrc_dsc,            // TX source discontinue
+  output    [REM_WIDTH-1:0] trn_trem,                // TX remainder
+  output                    trn_terrfwd,             // TX error forward
+  output                    trn_tstr,                // TX streaming enable
+  input               [5:0] trn_tbuf_av,             // TX buffers available
+  output                    trn_tecrc_gen,           // TX ECRC generate
+
+  // TRN Misc.
+  //-----------
+  input                     trn_tcfg_req,            // TX config request
+  output                    trn_tcfg_gnt,            // RX config grant
+  input                     trn_lnk_up,              // PCIe link up
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  input               [2:0] cfg_pcie_link_state,     // Encoded PCIe link state
+
+  // Virtex6 PM
+  //-----------
+  input                     cfg_pm_send_pme_to,      // PM send PME turnoff msg
+  input               [1:0] cfg_pmcsr_powerstate,    // PMCSR power state
+  input              [31:0] trn_rdllp_data,          // RX DLLP data
+  input                     trn_rdllp_src_rdy,       // RX DLLP source ready
+
+  // Virtex6/Spartan6 PM
+  //-----------
+  input                     cfg_to_turnoff,          // Turnoff request
+  output                    cfg_turnoff_ok,          // Turnoff grant
+
+  // System
+  //-----------
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+
+wire tready_thrtl;
+
+//---------------------------------------------//
+// TX Data Pipeline                            //
+//---------------------------------------------//
+
+design_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_PM_PRIORITY( C_PM_PRIORITY ),
+  .TCQ( TCQ ),
+
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+) tx_pipeline_inst (
+
+  // Incoming AXI RX
+  //-----------
+  .s_axis_tx_tdata( s_axis_tx_tdata ),
+  .s_axis_tx_tready( s_axis_tx_tready ),
+  .s_axis_tx_tvalid( s_axis_tx_tvalid ),
+  .s_axis_tx_tkeep( s_axis_tx_tkeep ),
+  .s_axis_tx_tlast( s_axis_tx_tlast ),
+  .s_axis_tx_tuser( s_axis_tx_tuser ),
+
+  // Outgoing TRN TX
+  //-----------
+  .trn_td( trn_td ),
+  .trn_tsof( trn_tsof ),
+  .trn_teof( trn_teof ),
+  .trn_tsrc_rdy( trn_tsrc_rdy ),
+  .trn_tdst_rdy( trn_tdst_rdy ),
+  .trn_tsrc_dsc( trn_tsrc_dsc ),
+  .trn_trem( trn_trem ),
+  .trn_terrfwd( trn_terrfwd ),
+  .trn_tstr( trn_tstr ),
+  .trn_tecrc_gen( trn_tecrc_gen ),
+  .trn_lnk_up( trn_lnk_up ),
+
+  // System
+  //-----------
+  .tready_thrtl( tready_thrtl ),
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+
+//---------------------------------------------//
+// TX Throttle Controller                      //
+//---------------------------------------------//
+
+generate
+  if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
+design_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl #(
+      .C_DATA_WIDTH( C_DATA_WIDTH ),
+      .C_FAMILY( C_FAMILY ),
+      .C_ROOT_PORT( C_ROOT_PORT ),
+      .TCQ( TCQ )
+
+    ) tx_thrl_ctl_inst (
+
+      // Outgoing AXI TX
+      //-----------
+      .s_axis_tx_tdata( s_axis_tx_tdata ),
+      .s_axis_tx_tvalid( s_axis_tx_tvalid ),
+      .s_axis_tx_tuser( s_axis_tx_tuser ),
+      .s_axis_tx_tlast( s_axis_tx_tlast ),
+
+      // User Misc.
+      //-----------
+      .user_turnoff_ok( user_turnoff_ok ),
+      .user_tcfg_gnt( user_tcfg_gnt ),
+
+      // Incoming TRN RX
+      //-----------
+      .trn_tbuf_av( trn_tbuf_av ),
+      .trn_tdst_rdy( trn_tdst_rdy ),
+
+      // TRN Misc.
+      //-----------
+      .trn_tcfg_req( trn_tcfg_req ),
+      .trn_tcfg_gnt( trn_tcfg_gnt ),
+      .trn_lnk_up( trn_lnk_up ),
+
+      // 7 Seriesq/Virtex6 PM
+      //-----------
+      .cfg_pcie_link_state( cfg_pcie_link_state ),
+
+      // Virtex6 PM
+      //-----------
+      .cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
+      .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
+      .trn_rdllp_data( trn_rdllp_data ),
+      .trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
+
+      // Spartan6 PM
+      //-----------
+      .cfg_to_turnoff( cfg_to_turnoff ),
+      .cfg_turnoff_ok( cfg_turnoff_ok ),
+
+      // System
+      //-----------
+      .tready_thrtl( tready_thrtl ),
+      .user_clk( user_clk ),
+      .user_rst( user_rst )
+    );
+  end
+  else begin : thrtl_ctl_disabled
+    assign tready_thrtl   = 1'b0;
+
+    assign cfg_turnoff_ok = user_turnoff_ok;
+    assign trn_tcfg_gnt   = user_tcfg_gnt;
+  end
+endgenerate
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.v

@@ -0,0 +1,543 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to    //
+//  TRN.                                                                      //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_tx                                                          //
+//        axi_basic_tx_pipeline                                               //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline #(
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI TX
+  //-----------
+  input      [C_DATA_WIDTH-1:0] s_axis_tx_tdata,     // TX data from user
+  input                         s_axis_tx_tvalid,    // TX data is valid
+  output                        s_axis_tx_tready,    // TX ready for data
+  input        [KEEP_WIDTH-1:0] s_axis_tx_tkeep,     // TX strobe byte enables
+  input                         s_axis_tx_tlast,     // TX data is last
+  input                   [3:0] s_axis_tx_tuser,     // TX user signals
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN TX
+  //-----------
+  output     [C_DATA_WIDTH-1:0] trn_td,              // TX data from block
+  output                        trn_tsof,            // TX start of packet
+  output                        trn_teof,            // TX end of packet
+  output                        trn_tsrc_rdy,        // TX source ready
+  input                         trn_tdst_rdy,        // TX destination ready
+  output                        trn_tsrc_dsc,        // TX source discontinue
+  output        [REM_WIDTH-1:0] trn_trem,            // TX remainder
+  output                        trn_terrfwd,         // TX error forward
+  output                        trn_tstr,            // TX streaming enable
+  output                        trn_tecrc_gen,       // TX ECRC generate
+  input                         trn_lnk_up,          // PCIe link up
+
+  // System
+  //-----------
+  input                         tready_thrtl,        // TREADY from thrtl ctl
+  input                         user_clk,            // user clock from block
+  input                         user_rst             // user reset from block
+);
+
+
+// Input register stage
+reg  [C_DATA_WIDTH-1:0] reg_tdata;
+reg                     reg_tvalid;
+reg    [KEEP_WIDTH-1:0] reg_tkeep;
+reg               [3:0] reg_tuser;
+reg                     reg_tlast;
+reg                     reg_tready;
+
+// Pipeline utility signals
+reg                     trn_in_packet;
+reg                     axi_in_packet;
+reg                     flush_axi;
+wire                    disable_trn;
+reg                     reg_disable_trn;
+
+wire                    axi_beat_live  = s_axis_tx_tvalid && s_axis_tx_tready;
+wire                    axi_end_packet = axi_beat_live && s_axis_tx_tlast;
+
+
+//----------------------------------------------------------------------------//
+// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. //
+// 128-bit:                 64-bit:                  32-bit:                  //
+// TRN DW0 maps to AXI DW3  TRN DW0 maps to AXI DW1  TNR DW0 maps to AXI DW0  //
+// TRN DW1 maps to AXI DW2  TRN DW1 maps to AXI DW0                           //
+// TRN DW2 maps to AXI DW1                                                    //
+// TRN DW3 maps to AXI DW0                                                    //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : td_DW_swap_128
+    assign trn_td = {reg_tdata[31:0],
+                     reg_tdata[63:32],
+                     reg_tdata[95:64],
+                     reg_tdata[127:96]};
+  end
+  else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64
+    assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]};
+  end
+  else begin : td_DW_swap_32
+    assign trn_td = reg_tdata;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create trn_tsof. If we're not currently in a packet and TVALID goes high,  //
+// assert TSOF.                                                               //
+//----------------------------------------------------------------------------//
+assign trn_tsof = reg_tvalid && !trn_in_packet;
+
+
+//----------------------------------------------------------------------------//
+// Create trn_in_packet. This signal tracks if the TRN interface is currently //
+// in the middle of a packet, which is needed to generate trn_tsof            //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_in_packet <= #TCQ 1'b0;
+  end
+  else begin
+    if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin
+      trn_in_packet <= #TCQ 1'b1;
+    end
+    else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin
+      trn_in_packet <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create axi_in_packet. This signal tracks if the AXI interface is currently //
+// in the middle of a packet, which is needed in case the link goes down.     //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    axi_in_packet <= #TCQ 1'b0;
+  end
+  else begin
+    if(axi_beat_live && !s_axis_tx_tlast) begin
+      axi_in_packet <= #TCQ 1'b1;
+    end
+    else if(axi_beat_live) begin
+      axi_in_packet <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create disable_trn. This signal asserts when the link goes down and        //
+// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn  //
+// depends on C_PM_PRIORITY, as described below.                              //
+//----------------------------------------------------------------------------//
+generate
+  // In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time
+  // the link goes down until the the AXI interface is ready to accept packets
+  // again (via assertion of TREADY). By waiting for TREADY, we allow the
+  // previous value buffer to fill, so we're ready for any throttling by the
+  // user or the block.
+  if(C_PM_PRIORITY == "TRUE") begin : pm_priority_trn_flush
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_disable_trn    <= #TCQ 1'b1;
+      end
+      else begin
+        // When the link goes down, disable the TRN interface.
+        if(!trn_lnk_up)
+        begin
+          reg_disable_trn  <= #TCQ 1'b1;
+        end
+
+        // When the link comes back up and the AXI interface is ready, we can
+        // release the pipeline and return to normal operation.
+        else if(!flush_axi && s_axis_tx_tready) begin
+          reg_disable_trn <= #TCQ 1'b0;
+        end
+      end
+    end
+
+    assign disable_trn = reg_disable_trn;
+  end
+
+  // In the throttle-controlled pipeline, we don't have a previous value buffer.
+  // The throttle control mechanism handles TREADY, so all we need to do is
+  // detect when the link goes down and disable the TRN interface until the link
+  // comes back up and the AXI interface is finished flushing any packets.
+  else begin : thrtl_ctl_trn_flush
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_disable_trn    <= #TCQ 1'b0;
+      end
+      else begin
+        // If the link is down and AXI is in packet, disable TRN and look for
+        // the end of the packet
+        if(axi_in_packet && !trn_lnk_up && !axi_end_packet)
+        begin
+          reg_disable_trn  <= #TCQ 1'b1;
+        end
+
+        // AXI packet is ending, so we're done flushing
+        else if(axi_end_packet) begin
+          reg_disable_trn <= #TCQ 1'b0;
+        end
+      end
+    end
+
+    // Disable the TRN interface if link is down or we're still flushing the AXI
+    // interface.
+    assign disable_trn = reg_disable_trn || !trn_lnk_up;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Convert STRB to RREM. Here, we are converting the encoding method for the  //
+// location of the EOF from AXI (tkeep) to TRN flavor (rrem).                 //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128
+    //---------------------------------------//
+    // Conversion table:                     //
+    // trem    | tkeep                       //
+    // [1] [0] | [15:12] [11:8] [7:4] [3:0]  //
+    // ------------------------------------- //
+    //  1   1  |   D3      D2    D1    D0    //
+    //  1   0  |   --      D2    D1    D0    //
+    //  0   1  |   --      --    D1    D0    //
+    //  0   0  |   --      --    --    D0    //
+    //---------------------------------------//
+
+    wire   axi_DW_1    = reg_tkeep[7];
+    wire   axi_DW_2    = reg_tkeep[11];
+    wire   axi_DW_3    = reg_tkeep[15];
+    assign trn_trem[1] = axi_DW_2;
+    assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2);
+  end
+  else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64
+    assign trn_trem    = reg_tkeep[7];
+  end
+  else begin : tkeep_to_trem_32
+    assign trn_trem    = 1'b0;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create remaining TRN signals                                               //
+//----------------------------------------------------------------------------//
+assign trn_teof      = reg_tlast;
+assign trn_tecrc_gen = reg_tuser[0];
+assign trn_terrfwd   = reg_tuser[1];
+assign trn_tstr      = reg_tuser[2];
+assign trn_tsrc_dsc  = reg_tuser[3];
+
+
+//----------------------------------------------------------------------------//
+// Pipeline stage                                                             //
+//----------------------------------------------------------------------------//
+// We need one of two approaches for the pipeline stage depending on the
+// C_PM_PRIORITY parameter.
+generate
+  reg reg_tsrc_rdy;
+
+  // If set to FALSE, that means the user wants to use the TX packet boundary
+  // throttling feature. Since all Block throttling will now be predicted, we
+  // can use a simple straight-through pipeline.
+  if(C_PM_PRIORITY == "FALSE") begin : throttle_ctl_pipeline
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tdata        <= #TCQ {C_DATA_WIDTH{1'b0}};
+        reg_tvalid       <= #TCQ 1'b0;
+        reg_tkeep        <= #TCQ {KEEP_WIDTH{1'b0}};
+        reg_tlast        <= #TCQ 1'b0;
+        reg_tuser        <= #TCQ 4'h0;
+        reg_tsrc_rdy     <= #TCQ 1'b0;
+      end
+      else begin
+        reg_tdata        <= #TCQ s_axis_tx_tdata;
+        reg_tvalid       <= #TCQ s_axis_tx_tvalid;
+        reg_tkeep        <= #TCQ s_axis_tx_tkeep;
+        reg_tlast        <= #TCQ s_axis_tx_tlast;
+        reg_tuser        <= #TCQ s_axis_tx_tuser;
+
+        // Hold trn_tsrc_rdy low when flushing a packet.
+        reg_tsrc_rdy     <= #TCQ axi_beat_live && !disable_trn;
+      end
+    end
+
+    assign trn_tsrc_rdy = reg_tsrc_rdy;
+
+    // With TX packet boundary throttling, TREADY is pipelined in
+    // axi_basic_tx_thrtl_ctl and wired through here.
+    assign s_axis_tx_tready = tready_thrtl;
+  end
+
+  //**************************************************************************//
+
+  // If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM
+  // functionality intact isntead of TX packet boundary throttling. Now the
+  // Block could back-pressure at any time, which creates the standard problem
+  // of potential data loss due to the handshaking latency. Here we need a
+  // previous value buffer, just like the RX data path.
+  else begin : pm_prioity_pipeline
+    reg  [C_DATA_WIDTH-1:0] tdata_prev;
+    reg                     tvalid_prev;
+    reg    [KEEP_WIDTH-1:0] tkeep_prev;
+    reg                     tlast_prev;
+    reg               [3:0] tuser_prev;
+    reg                     reg_tdst_rdy;
+
+    wire                    data_hold;
+    reg                     data_prev;
+
+
+    //------------------------------------------------------------------------//
+    // Previous value buffer                                                  //
+    // ---------------------                                                  //
+    // We are inserting a pipeline stage in between AXI and TRN, which causes //
+    // some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready.    //
+    // The added cycle of latency in the path causes the Block to fall behind //
+    // the AXI interface whenever it throttles.                               //
+    //                                                                        //
+    // To avoid loss of data, we must keep the previous value of all          //
+    // s_axis_tx_* signals in case the Block throttles.                       //
+    //------------------------------------------------------------------------//
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        tdata_prev   <= #TCQ {C_DATA_WIDTH{1'b0}};
+        tvalid_prev  <= #TCQ 1'b0;
+        tkeep_prev   <= #TCQ {KEEP_WIDTH{1'b0}};
+        tlast_prev   <= #TCQ 1'b0;
+        tuser_prev   <= #TCQ 4'h 0;
+      end
+      else begin
+        // prev buffer works by checking s_axis_tx_tready. When
+        // s_axis_tx_tready is asserted, a new value is present on the
+        // interface.
+        if(!s_axis_tx_tready) begin
+          tdata_prev   <= #TCQ tdata_prev;
+          tvalid_prev  <= #TCQ tvalid_prev;
+          tkeep_prev   <= #TCQ tkeep_prev;
+          tlast_prev   <= #TCQ tlast_prev;
+          tuser_prev   <= #TCQ tuser_prev;
+        end
+        else begin
+          tdata_prev   <= #TCQ s_axis_tx_tdata;
+          tvalid_prev  <= #TCQ s_axis_tx_tvalid;
+          tkeep_prev   <= #TCQ s_axis_tx_tkeep;
+          tlast_prev   <= #TCQ s_axis_tx_tlast;
+          tuser_prev   <= #TCQ s_axis_tx_tuser;
+        end
+      end
+    end
+
+    // Create special buffer which locks in the proper value of TDATA depending
+    // on whether the user is throttling or not. This buffer has three states:
+    //
+    //       HOLD state: TDATA maintains its current value
+    //                   - the Block has throttled the PCIe block
+    //   PREVIOUS state: the buffer provides the previous value on TDATA
+    //                   - the Block has finished throttling, and is a little
+    //                     behind the user
+    //    CURRENT state: the buffer passes the current value on TDATA
+    //                   - the Block is caught up and ready to receive the
+    //                     latest data from the user
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tdata  <= #TCQ {C_DATA_WIDTH{1'b0}};
+        reg_tvalid <= #TCQ 1'b0;
+        reg_tkeep  <= #TCQ {KEEP_WIDTH{1'b0}};
+        reg_tlast  <= #TCQ 1'b0;
+        reg_tuser  <= #TCQ 4'h0;
+
+        reg_tdst_rdy <= #TCQ 1'b0;
+      end
+      else begin
+        reg_tdst_rdy <= #TCQ trn_tdst_rdy;
+
+        if(!data_hold) begin
+          // PREVIOUS state
+          if(data_prev) begin
+            reg_tdata  <= #TCQ tdata_prev;
+            reg_tvalid <= #TCQ tvalid_prev;
+            reg_tkeep  <= #TCQ tkeep_prev;
+            reg_tlast  <= #TCQ tlast_prev;
+            reg_tuser  <= #TCQ tuser_prev;
+          end
+
+          // CURRENT state
+          else begin
+            reg_tdata  <= #TCQ s_axis_tx_tdata;
+            reg_tvalid <= #TCQ s_axis_tx_tvalid;
+            reg_tkeep  <= #TCQ s_axis_tx_tkeep;
+            reg_tlast  <= #TCQ s_axis_tx_tlast;
+            reg_tuser  <= #TCQ s_axis_tx_tuser;
+          end
+        end
+        // else HOLD state
+      end
+    end
+
+
+    // Logic to instruct pipeline to hold its value
+    assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy;
+
+
+    // Logic to instruct pipeline to use previous bus values. Always use
+    // previous value after holding a value.
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        data_prev <= #TCQ 1'b0;
+      end
+      else begin
+        data_prev <= #TCQ data_hold;
+      end
+    end
+
+
+    //------------------------------------------------------------------------//
+    // Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low.  //
+    //------------------------------------------------------------------------//
+    assign trn_tsrc_rdy = reg_tvalid && !disable_trn;
+
+
+    //------------------------------------------------------------------------//
+    // Create TREADY                                                          //
+    //------------------------------------------------------------------------//
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tready <= #TCQ 1'b0;
+      end
+      else begin
+        // If the link went down and we need to flush a packet in flight, hold
+        // TREADY high
+        if(flush_axi && !axi_end_packet) begin
+          reg_tready <= #TCQ 1'b1;
+        end
+
+        // If the link is up, TREADY is as follows:
+        //   TREADY = 1 when trn_tsrc_rdy == 0
+        //      - While idle, keep the pipeline primed and ready for the next
+        //        packet
+        //
+        //   TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1
+        //      - While in packet, throttle pipeline based on state of TRN
+        else if(trn_lnk_up) begin
+          reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy;
+        end
+
+        // If the link is down and we're not flushing a packet, hold TREADY low
+        // wait for link to come back up
+        else begin
+          reg_tready <= #TCQ 1'b0;
+        end
+      end
+    end
+
+    assign s_axis_tx_tready = reg_tready;
+  end
+
+
+  //--------------------------------------------------------------------------//
+  // Create flush_axi. This signal detects if the link goes down while the    //
+  // AXI interface is in packet. In this situation, we need to flush the      //
+  // packet through the AXI interface and discard it.                         //
+  //--------------------------------------------------------------------------//
+  always @(posedge user_clk) begin
+    if(user_rst) begin
+      flush_axi    <= #TCQ 1'b0;
+    end
+    else begin
+      // If the AXI interface is in packet and the link goes down, purge it.
+      if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin
+        flush_axi <= #TCQ 1'b1;
+      end
+
+      // The packet is finished, so we're done flushing.
+      else if(axi_end_packet) begin
+        flush_axi <= #TCQ 1'b0;
+      end
+    end
+  end
+endgenerate
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.v

@@ -0,0 +1,784 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TX throttle controller. Anticipates back-pressure from PCIe block and     //
+//  preemptively back-pressures user design (packet boundary throttling).     //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_tx                                                          //
+//        axi_basic_tx_thrtl_ctl                                              //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl #(
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter C_FAMILY     = "X7",          // Targeted FPGA family
+  parameter C_ROOT_PORT  = "FALSE",       // PCIe block is in root port mode
+  parameter TCQ = 1                       // Clock to Q time
+  ) (
+
+  // AXI TX
+  //-----------
+  input  [C_DATA_WIDTH-1:0] s_axis_tx_tdata,         // TX data from user
+  input                     s_axis_tx_tvalid,        // TX data is valid
+  input               [3:0] s_axis_tx_tuser,         // TX user signals
+  input                     s_axis_tx_tlast,         // TX data is last
+
+  // User Misc.
+  //-----------
+  input                     user_turnoff_ok,         // Turnoff OK from user
+  input                     user_tcfg_gnt,           // Send cfg OK from user
+
+  // TRN TX
+  //-----------
+  input               [5:0] trn_tbuf_av,             // TX buffers available
+  input                     trn_tdst_rdy,            // TX destination ready
+
+  // TRN Misc.
+  //-----------
+  input                     trn_tcfg_req,            // TX config request
+  output                    trn_tcfg_gnt,            // TX config grant
+  input                     trn_lnk_up,              // PCIe link up
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  input               [2:0] cfg_pcie_link_state,     // Encoded PCIe link state
+
+  // Virtex6 PM
+  //-----------
+  input                     cfg_pm_send_pme_to,      // PM send PME turnoff msg
+  input               [1:0] cfg_pmcsr_powerstate,    // PMCSR power state
+  input              [31:0] trn_rdllp_data,          // RX DLLP data
+  input                     trn_rdllp_src_rdy,       // RX DLLP source ready
+
+  // Virtex6/Spartan6 PM
+  //-----------
+  input                     cfg_to_turnoff,          // Turnoff request
+  output reg                cfg_turnoff_ok,          // Turnoff grant
+
+  // System
+  //-----------
+  output reg                tready_thrtl,            // TREADY to pipeline
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+// Thrtl user when TBUF hits this val
+localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
+                                                   (C_DATA_WIDTH == 64) ? 1 : 0;
+
+// Pause user when TBUF hits this val
+localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
+
+// GAP pause time - the latency from the time a packet is accepted on the TRN
+// interface to the time trn_tbuf_av from the Block will decrement.
+localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
+
+// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
+localparam TCFG_LATENCY_TIME = 2'd2;
+
+// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
+localparam TCFG_GNT_PIPE_STAGES = 3;
+
+// Throttle condition registers and constants
+reg        lnk_up_thrtl;
+wire       lnk_up_trig;
+wire       lnk_up_exit;
+
+reg        tbuf_av_min_thrtl;
+wire       tbuf_av_min_trig;
+
+reg        tbuf_av_gap_thrtl;
+reg  [2:0] tbuf_gap_cnt;
+wire       tbuf_av_gap_trig;
+wire       tbuf_av_gap_exit;
+wire       gap_trig_tlast;
+wire       gap_trig_decr;
+wire       gap_trig_tcfg;
+reg  [5:0] tbuf_av_d;
+
+reg        tcfg_req_thrtl;
+reg  [1:0] tcfg_req_cnt;
+reg        trn_tdst_rdy_d;
+wire       tcfg_req_trig;
+wire       tcfg_req_exit;
+reg        tcfg_gnt_log;
+
+wire       pre_throttle;
+wire       reg_throttle;
+wire       exit_crit;
+reg        reg_tcfg_gnt;
+reg        trn_tcfg_req_d;
+reg        tcfg_gnt_pending;
+wire       wire_to_turnoff;
+reg        reg_turnoff_ok;
+
+reg        tready_thrtl_mux;
+
+localparam LINKSTATE_L0             = 3'b000;
+localparam LINKSTATE_PPM_L1         = 3'b001;
+localparam LINKSTATE_PPM_L1_TRANS   = 3'b101;
+localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
+localparam PM_ENTER_L1              = 8'h20;
+localparam POWERSTATE_D0            = 2'b00;
+
+reg        ppm_L1_thrtl;
+wire       ppm_L1_trig;
+wire       ppm_L1_exit;
+reg  [2:0] cfg_pcie_link_state_d;
+reg        trn_rdllp_src_rdy_d;
+
+reg        ppm_L23_thrtl;
+wire       ppm_L23_trig;
+reg        cfg_turnoff_ok_pending;
+
+reg        reg_tlast;
+
+// Throttle control state machine states and registers
+localparam IDLE       = 0;
+localparam THROTTLE   = 1;
+reg        cur_state;
+reg        next_state;
+
+reg        reg_axi_in_pkt;
+wire       axi_in_pkt;
+wire       axi_pkt_ending;
+wire       axi_throttled;
+wire       axi_thrtl_ok;
+wire       tx_ecrc_pause;
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: PCIe link is down                                         //
+//   - When to throttle: trn_lnk_up deasserted                                //
+//   - When to stop: trn_tdst_rdy assesrted                                   //
+//----------------------------------------------------------------------------//
+assign lnk_up_trig = !trn_lnk_up;
+assign lnk_up_exit = trn_tdst_rdy;
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    lnk_up_thrtl <= #TCQ 1'b1;
+  end
+  else begin
+    if(lnk_up_trig) begin
+      lnk_up_thrtl <= #TCQ 1'b1;
+    end
+    else if(lnk_up_exit) begin
+      lnk_up_thrtl <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Transmit buffers depleted                                 //
+//   - When to throttle: trn_tbuf_av falls to 0                               //
+//   - When to stop: trn_tbuf_av rises above 0 again                          //
+//----------------------------------------------------------------------------//
+assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    tbuf_av_min_thrtl <= #TCQ 1'b0;
+  end
+  else begin
+    if(tbuf_av_min_trig) begin
+      tbuf_av_min_thrtl <= #TCQ 1'b1;
+    end
+
+    // The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
+    else begin
+      tbuf_av_min_thrtl <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Transmit buffers getting low                              //
+//   - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP  //
+//   - When to stop: after TBUF_GAP_TIME cycles elapse                        //
+//                                                                            //
+// If we're about to run out of transmit buffers, throttle the user for a     //
+// few clock cycles to give the PCIe block time to catch up. This is          //
+// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe   //
+// Block transmit path.                                                       //
+//----------------------------------------------------------------------------//
+
+// Detect two different scenarios for buffers getting low:
+// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
+//    we need to pause and let that packet "soak in"
+assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
+                            s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
+
+// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
+//    pause and make sure no other packets are about to soak in and cause the
+//    buffer availability to drop further.
+assign gap_trig_decr  = (trn_tbuf_av == (TBUF_AV_GAP)) &&
+                                                 (tbuf_av_d == (TBUF_AV_GAP+1));
+
+assign gap_trig_tcfg  = (tcfg_req_thrtl && tcfg_req_exit);
+assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
+assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    tbuf_av_gap_thrtl <= #TCQ 1'b0;
+    tbuf_gap_cnt      <= #TCQ 3'h0;
+    tbuf_av_d         <= #TCQ 6'h00;
+  end
+  else begin
+    if(tbuf_av_gap_trig) begin
+      tbuf_av_gap_thrtl <= #TCQ 1'b1;
+    end
+    else if(tbuf_av_gap_exit) begin
+      tbuf_av_gap_thrtl <= #TCQ 1'b0;
+    end
+
+    // tbuf gap counter:
+    // This logic controls the length of the throttle condition when tbufs are
+    // getting low.
+    if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
+      if(tbuf_gap_cnt > 0) begin
+        tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
+      end
+    end
+    else begin
+      tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
+    end
+
+    tbuf_av_d <= #TCQ trn_tbuf_av;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Block needs to send a CFG response                        //
+//   - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted              //
+//   - When to stop: after trn_tdst_rdy transitions to unasserted             //
+//                                                                            //
+// If the block needs to send a response to a CFG packet, this will cause     //
+// the subsequent deassertion of trn_tdst_rdy. When the user design permits,  //
+// grant permission to the block to service request and throttle the user.    //
+//----------------------------------------------------------------------------//
+assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
+assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
+                                                                   trn_tdst_rdy;
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    tcfg_req_thrtl   <= #TCQ 1'b0;
+    trn_tcfg_req_d   <= #TCQ 1'b0;
+    trn_tdst_rdy_d   <= #TCQ 1'b1;
+    reg_tcfg_gnt     <= #TCQ 1'b0;
+    tcfg_req_cnt     <= #TCQ 2'd0;
+    tcfg_gnt_pending <= #TCQ 1'b0;
+  end
+  else begin
+    if(tcfg_req_trig) begin
+      tcfg_req_thrtl <= #TCQ 1'b1;
+    end
+    else if(tcfg_req_exit) begin
+      tcfg_req_thrtl <= #TCQ 1'b0;
+    end
+
+    // We need to wait the appropriate amount of time for the tcfg_gnt to
+    // "sink in" to the PCIe block. After that, we know that the PCIe block will
+    // not reassert trn_tdst_rdy until the CFG request has been serviced. If a
+    // new request is being service (tcfg_gnt_log == 1), then reset the timer.
+    if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
+      tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
+    end
+    else begin
+      if(tcfg_req_cnt > 0) begin
+        tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
+      end
+    end
+
+    // Make sure tcfg_gnt_log pulses once for one clock cycle for every
+    // cfg packet request.
+    if(trn_tcfg_req && !trn_tcfg_req_d) begin
+      tcfg_gnt_pending <= #TCQ 1'b1;
+    end
+    else if(tcfg_gnt_log) begin
+      tcfg_gnt_pending <= #TCQ 1'b0;
+    end
+
+    trn_tcfg_req_d <= #TCQ trn_tcfg_req;
+    trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
+    reg_tcfg_gnt   <= #TCQ user_tcfg_gnt;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Block needs to transition to low power state PPM L1       //
+//   - When to throttle: appropriate low power state signal asserted          //
+//     (architecture dependent)                                               //
+//   - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT    //
+//     dependent)                                                             //
+//                                                                            //
+// If the block needs to transition to PM state PPM L1, we need to finish     //
+// up what we're doing and throttle immediately.                              //
+//----------------------------------------------------------------------------//
+generate
+  // PPM L1 signals for 7 Series in RC mode
+  if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
+    assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
+                           (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
+  end
+
+  // PPM L1 signals for 7 Series in EP mode
+  else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
+    assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
+                           (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
+  end
+
+  // PPM L1 signals for V6 in RC mode
+  else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
+    assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
+                                      trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
+  end
+
+  // PPM L1 signals for V6 in EP mode
+  else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
+    assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
+  end
+
+  // PPM L1 detection not supported for S6
+  else begin : s6_L1_thrtl
+    assign ppm_L1_trig = 1'b0;
+    assign ppm_L1_exit = 1'b1;
+  end
+endgenerate
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    ppm_L1_thrtl          <= #TCQ 1'b0;
+    cfg_pcie_link_state_d <= #TCQ 3'b0;
+    trn_rdllp_src_rdy_d   <= #TCQ 1'b0;
+  end
+  else begin
+    if(ppm_L1_trig) begin
+      ppm_L1_thrtl <= #TCQ 1'b1;
+    end
+    else if(ppm_L1_exit) begin
+      ppm_L1_thrtl <= #TCQ 1'b0;
+    end
+    cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
+    trn_rdllp_src_rdy_d   <= #TCQ trn_rdllp_src_rdy;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Block needs to transition to low power state PPM L2/3     //
+//   - When to throttle: appropriate PM signal indicates a transition to      //
+//     L2/3 is pending or in progress (family and role dependent)             //
+//   - When to stop: never (the only path out of L2/3 is a full reset)        //
+//                                                                            //
+// If the block needs to transition to PM state PPM L2/3, we need to finish   //
+// up what we're doing and throttle when the user gives permission.           //
+//----------------------------------------------------------------------------//
+generate
+  // PPM L2/3 signals for 7 Series in RC mode
+  if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
+    assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
+    assign wire_to_turnoff = 1'b0;
+  end
+
+  // PPM L2/3 signals for V6 in RC mode
+  else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
+    assign ppm_L23_trig = cfg_pm_send_pme_to;
+    assign wire_to_turnoff = 1'b0;
+  end
+
+  // PPM L2/3 signals in EP mode
+  else begin : L23_thrtl_ep
+    assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
+
+    // PPM L2/3 signals for 7 Series in EP mode
+    // For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
+    // outstanding, so we need a "sticky" register that grabs the request.
+    if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
+      reg reg_to_turnoff;
+
+      always @(posedge user_clk) begin
+        if(user_rst) begin
+          reg_to_turnoff <= #TCQ 1'b0;
+        end
+        else begin
+          if(cfg_to_turnoff) begin
+            reg_to_turnoff <= #TCQ 1'b1;
+          end
+        end
+      end
+
+      assign wire_to_turnoff = reg_to_turnoff;
+    end
+
+    // PPM L2/3 signals for V6/S6 in EP mode
+    // In V6 and S6, the to_turnoff signal asserts and remains asserted until
+    // turnoff_ok is asserted, so a sticky reg is not necessary.
+    else begin : v6_s6_L23_thrtl_ep
+      assign wire_to_turnoff = cfg_to_turnoff;
+    end
+
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_turnoff_ok <= #TCQ 1'b0;
+      end
+      else begin
+        reg_turnoff_ok <= #TCQ user_turnoff_ok;
+      end
+    end
+  end
+endgenerate
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    ppm_L23_thrtl   <= #TCQ 1'b0;
+    cfg_turnoff_ok_pending <= #TCQ 1'b0;
+  end
+  else begin
+    if(ppm_L23_trig) begin
+      ppm_L23_thrtl <= #TCQ 1'b1;
+    end
+
+    // Make sure cfg_turnoff_ok pulses once for one clock cycle for every
+    // turnoff request.
+    if(ppm_L23_trig && !ppm_L23_thrtl) begin
+      cfg_turnoff_ok_pending <= #TCQ 1'b1;
+    end
+    else if(cfg_turnoff_ok) begin
+      cfg_turnoff_ok_pending <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create axi_thrtl_ok. This signal determines if it's OK to throttle the     //
+// user design on the AXI interface. Since TREADY is registered, this signal  //
+// needs to assert on the cycle ~before~ we actually intend to throttle.      //
+// The only time it's OK to throttle when TVALID is asserted is on the first  //
+// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the         //
+// is true:                                                                   //
+//    1) The user is not in a packet and is not starting one                  //
+//    2) The user is just finishing a packet                                  //
+//    3) We're already throttled, so it's OK to continue throttling           //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    reg_axi_in_pkt <= #TCQ 1'b0;
+  end
+  else begin
+    if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
+      reg_axi_in_pkt <= #TCQ 1'b0;
+    end
+    else if(tready_thrtl && s_axis_tx_tvalid) begin
+      reg_axi_in_pkt <= #TCQ 1'b1;
+    end
+  end
+end
+
+assign axi_in_pkt     = s_axis_tx_tvalid || reg_axi_in_pkt;
+assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
+assign axi_throttled  = !tready_thrtl;
+assign axi_thrtl_ok   = !axi_in_pkt || axi_pkt_ending || axi_throttled;
+
+
+//----------------------------------------------------------------------------//
+// Throttle CTL State Machine:                                                //
+// Throttle user design when a throttle trigger (or triggers) occur.          //
+// Keep user throttled until all exit criteria have been met.                 //
+//----------------------------------------------------------------------------//
+
+// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
+// we're seeking one
+assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
+                                || tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
+
+
+// Registered throttle signals. Used to control throttle state machine
+assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
+                             || tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
+
+assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
+                          && !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
+
+always @(*) begin
+  case(cur_state)
+    // IDLE: in this state we're waiting for a trigger event to occur. As
+    // soon as an event occurs and the user isn't transmitting a packet, we
+    // throttle the PCIe block and the user and next state is THROTTLE.
+    IDLE: begin
+      if(reg_throttle && axi_thrtl_ok) begin
+        // Throttle user
+        tready_thrtl_mux = 1'b0;
+        next_state       = THROTTLE;
+
+        // Assert appropriate grant signal depending on the throttle type.
+        if(tcfg_req_thrtl) begin
+          tcfg_gnt_log   = 1'b1;   // For cfg request, grant the request
+          cfg_turnoff_ok = 1'b0;   //
+        end
+        else if(ppm_L23_thrtl) begin
+          tcfg_gnt_log   = 1'b0;   //
+          cfg_turnoff_ok = 1'b1;   // For PM request, permit transition
+        end
+        else begin
+          tcfg_gnt_log   = 1'b0;   // Otherwise do nothing
+          cfg_turnoff_ok = 1'b0;   //
+        end
+      end
+
+      // If there's not throttle event, do nothing
+      else begin
+        // Throttle user as soon as possible
+        tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
+        next_state       = IDLE;
+
+        tcfg_gnt_log     = 1'b0;
+        cfg_turnoff_ok   = 1'b0;
+      end
+    end
+
+    // THROTTLE: in this state the user is throttle and we're waiting for
+    // exit criteria, which tells us that the throttle event is over. When
+    // the exit criteria is satisfied, de-throttle the user and next state
+    // is IDLE.
+    THROTTLE: begin
+      if(exit_crit) begin
+        // Dethrottle user
+        tready_thrtl_mux = !pre_throttle;
+        next_state       = IDLE;
+      end
+      else begin
+        // Throttle user
+        tready_thrtl_mux = 1'b0;
+        next_state       = THROTTLE;
+      end
+
+      // Assert appropriate grant signal depending on the throttle type.
+      if(tcfg_req_thrtl && tcfg_gnt_pending) begin
+        tcfg_gnt_log   = 1'b1;   // For cfg request, grant the request
+        cfg_turnoff_ok = 1'b0;   //
+      end
+      else if(cfg_turnoff_ok_pending) begin
+        tcfg_gnt_log   = 1'b0;   //
+        cfg_turnoff_ok = 1'b1;   // For PM request, permit transition
+      end
+      else begin
+        tcfg_gnt_log   = 1'b0;   // Otherwise do nothing
+        cfg_turnoff_ok = 1'b0;   //
+      end
+    end
+
+    default: begin
+      tready_thrtl_mux = 1'b0;
+      next_state       = IDLE;
+      tcfg_gnt_log     = 1'b0;
+      cfg_turnoff_ok   = 1'b0;
+    end
+  endcase
+end
+
+// Synchronous logic
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    // Throttle user by default until link comes up
+    cur_state        <= #TCQ THROTTLE;
+
+    reg_tlast        <= #TCQ 1'b0;
+
+    tready_thrtl     <= #TCQ 1'b0;
+  end
+  else begin
+    cur_state        <= #TCQ next_state;
+
+    tready_thrtl     <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
+    reg_tlast        <= #TCQ s_axis_tx_tlast;
+  end
+end
+
+// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
+// is asserted at SOF. In this case, the Block needs an extra data beat to
+// calculate the ECRC, but only if the following conditions are met:
+//  1) there is no empty DWORDS at the end of the packet
+//     (i.e. packet length % C_DATA_WIDTH == 0)
+//
+//  2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
+//     TLP header
+//
+// If both conditions are met, the Block will stall the TRN interface for one
+// data beat after EOF. We need to predict this stall and preemptively stall the
+// User for one beat.
+generate
+  if(C_FAMILY == "X7") begin : ecrc_pause_enabled
+    wire        tx_ecrc_pkt;
+    reg         reg_tx_ecrc_pkt;
+
+    wire  [1:0] packet_fmt;
+    wire        packet_td;
+    wire  [2:0] header_len;
+    wire  [9:0] payload_len;
+    wire [13:0] packet_len;
+    wire        pause_needed;
+
+    // Grab necessary packet fields
+    assign packet_fmt  = s_axis_tx_tdata[30:29];
+    assign packet_td   = s_axis_tx_tdata[15];
+
+    // Calculate total packet length
+    assign header_len  = packet_fmt[0] ? 3'd4 : 3'd3;
+    assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
+    assign packet_len  = {10'h000, header_len} + {4'h0, payload_len};
+
+
+    // Determine if packet a ECRC pause is needed
+    if(C_DATA_WIDTH == 128) begin : packet_len_check_128
+      assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
+    end
+    else begin : packet_len_check_64
+      assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
+    end
+
+
+    // Create flag to alert TX pipeline to insert a stall
+    assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
+                            tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
+
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tx_ecrc_pkt <= #TCQ 1'b0;
+      end
+      else begin
+        if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
+          reg_tx_ecrc_pkt <= #TCQ 1'b1;
+        end
+        else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
+          reg_tx_ecrc_pkt <= #TCQ 1'b0;
+        end
+      end
+    end
+
+
+    // Insert the stall now
+    assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
+                           s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
+
+  end
+  else begin : ecrc_pause_disabled
+    assign tx_ecrc_pause = 1'b0;
+  end
+endgenerate
+
+
+// Logic for 128-bit single cycle bug fix.
+// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
+// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
+// from AXI Basic causes the packet to be dropped. The packet drop occurs
+// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
+// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
+// prediction just as we do, it ignores the value of trn_tdst_rdy, and
+// ultimately drops the packet when transmitting the packet to the block.
+generate
+  if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
+    genvar stage;
+    reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
+
+    // Create a configurable depth FF delay pipeline
+    for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
+    begin : tcfg_gnt_pipeline_stage
+
+      always @(posedge user_clk) begin
+        if(user_rst) begin
+          tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
+        end
+        else begin
+          // For stage 0, insert the actual tcfg_gnt signal from logic
+          if(stage == 0) begin
+            tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
+          end
+
+          // For stages 1+, chain together
+          else begin
+            tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
+          end
+        end
+      end
+
+      // tcfg_gnt output to block assigned the last pipeline stage
+      assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
+    end
+  end
+  else begin : tcfg_gnt_no_pipeline
+
+    // For all other architectures, no pipeline delay needed for tcfg_gnt
+    assign trn_tcfg_gnt = tcfg_gnt_log;
+  end
+endgenerate
+
+endmodule

Firmware/Artix7_PCIe/dso_top_fpga_module_unsigned/dso_top.ip_user_files/bd/design_1/ip/design_1_xdma_0_0/ip_0/source/design_1_xdma_0_0_pcie2_ip_gt_common.v

@@ -0,0 +1,166 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : design_1_xdma_0_0_pcie2_ip_gt_common.v
+// Version    : 3.3
+`timescale 1ns / 1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xdma_0_0_pcie2_ip_gt_common #(
+
+parameter PCIE_SIM_MODE    = "FALSE",   // PCIe sim mode
+parameter PCIE_GT_DEVICE   = "GTX",     // PCIe GT device
+parameter PCIE_USE_MODE    = "2.1",     // PCIe use mode
+parameter PCIE_PLL_SEL     = "CPLL",    // PCIe PLL select for Gen1/Gen2 only
+parameter PCIE_REFCLK_FREQ = 0          // PCIe reference clock frequency
+)
+
+(
+input                   CPLLPDREFCLK,
+input               	PIPE_CLK,
+input               	QPLL_QPLLPD,
+input               	QPLL_QPLLRESET,
+input               	QPLL_DRP_CLK,
+input               	QPLL_DRP_RST_N,
+input               	QPLL_DRP_OVRD,
+input               	QPLL_DRP_GEN3,
+input               	QPLL_DRP_START,
+output      [5:0]  	QPLL_DRP_CRSCODE,
+output      [8:0]  	QPLL_DRP_FSM,
+output                  QPLL_DRP_DONE,
+output                  QPLL_DRP_RESET,
+output                  QPLL_QPLLLOCK,
+output                  QPLL_QPLLOUTCLK,
+output                  QPLL_QPLLOUTREFCLK
+);
+
+    //---------- QPLL DRP Module Output --------------------
+
+wire        [7:0]  qpll_drp_addr;
+wire               qpll_drp_en;
+wire        [15:0] qpll_drp_di;
+wire               qpll_drp_we;
+
+   //---------- QPLL Wrapper Output -----------------------
+
+wire        [15:0] qpll_drp_do;
+wire               qpll_drp_rdy;
+
+   //---------- QPLL Resets -----------------------
+
+
+        //---------- QPLL DRP Module ---------------------------------------
+
+design_1_xdma_0_0_pcie2_ip_qpll_drp #
+        (
+
+	        .PCIE_GT_DEVICE                 (PCIE_GT_DEVICE),               // PCIe GT device
+	        .PCIE_USE_MODE                  (PCIE_USE_MODE),                // PCIe use mode
+	        .PCIE_PLL_SEL                   (PCIE_PLL_SEL),                 // PCIe PLL select for Gen1/Gen2 only
+	        .PCIE_REFCLK_FREQ               (PCIE_REFCLK_FREQ)              // PCIe reference clock frequency
+
+        )
+        qpll_drp_i
+        (
+
+        //---------- Input -------------------------
+	    .DRP_CLK                        (QPLL_DRP_CLK),
+            .DRP_RST_N                      (!QPLL_DRP_RST_N),
+            .DRP_OVRD                       (QPLL_DRP_OVRD),
+            .DRP_GEN3                       (&QPLL_DRP_GEN3),
+            .DRP_QPLLLOCK                   (QPLL_QPLLLOCK),
+            .DRP_START                      (QPLL_DRP_START),
+            .DRP_DO                         (qpll_drp_do),
+            .DRP_RDY                        (qpll_drp_rdy),
+																													     
+        //----------           Output ------------------------
+            .DRP_ADDR                       (qpll_drp_addr),
+            .DRP_EN                         (qpll_drp_en),
+            .DRP_DI                         (qpll_drp_di),
+            .DRP_WE                         (qpll_drp_we),
+            .DRP_DONE                       (QPLL_DRP_DONE),
+            .DRP_QPLLRESET                  (QPLL_DRP_RESET),
+            .DRP_CRSCODE                    (QPLL_DRP_CRSCODE),
+            .DRP_FSM                        (QPLL_DRP_FSM)
+        );
+
+
+        //---------- QPLL Wrapper ------------------------------------------
+design_1_xdma_0_0_pcie2_ip_qpll_wrapper #
+        (
+	        .PCIE_SIM_MODE                  (PCIE_SIM_MODE),                // PCIe sim mode
+	        .PCIE_GT_DEVICE                 (PCIE_GT_DEVICE),               // PCIe GT device
+	        .PCIE_USE_MODE                  (PCIE_USE_MODE),                // PCIe use mode
+	        .PCIE_PLL_SEL                   (PCIE_PLL_SEL),                 // PCIe PLL select for Gen1/Gen2 only
+	        .PCIE_REFCLK_FREQ               (PCIE_REFCLK_FREQ)              // PCIe reference clock frequency
+        )
+        qpll_wrapper_i
+        (
+        //---------- QPLL Clock Ports --------------
+            .QPLL_CPLLPDREFCLK              (CPLLPDREFCLK),
+            .QPLL_GTGREFCLK                 (PIPE_CLK),
+            .QPLL_QPLLLOCKDETCLK            (1'd0),
+            .QPLL_QPLLOUTCLK                (QPLL_QPLLOUTCLK),
+            .QPLL_QPLLOUTREFCLK             (QPLL_QPLLOUTREFCLK),
+            .QPLL_QPLLLOCK                  (QPLL_QPLLLOCK),
+        //---------- QPLL Reset Ports --------------
+            .QPLL_QPLLPD                    (QPLL_QPLLPD),
+            .QPLL_QPLLRESET                 (QPLL_QPLLRESET),
+        //---------- QPLL DRP Ports ----------------
+            .QPLL_DRPCLK                    (QPLL_DRP_CLK),
+            .QPLL_DRPADDR                   (qpll_drp_addr),
+            .QPLL_DRPEN                     (qpll_drp_en),
+            .QPLL_DRPDI                     (qpll_drp_di),
+            .QPLL_DRPWE                     (qpll_drp_we),
+            .QPLL_DRPDO                     (qpll_drp_do),
+            .QPLL_DRPRDY                    (qpll_drp_rdy)			
+        );
+  
+endmodule