diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bd b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bd index 8f9da87..9d0dfbe 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bd +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bd @@ -1643,24 +1643,6 @@ } }, "interface_nets": { - "Conn2": { - "interface_ports": [ - "M00_AXI_0", - "axi_crossbar_0/M00_AXI" - ] - }, - "S00_AXI_1": { - "interface_ports": [ - "S00_AXI", - "axi_crossbar_0/S00_AXI" - ] - }, - "S01_AXI_1": { - "interface_ports": [ - "S01_AXI", - "axi_crossbar_0/S01_AXI" - ] - }, "Conn3": { "interface_ports": [ "S_AXI_0", @@ -1672,6 +1654,24 @@ "DDR3", "mig_7series_0/DDR3" ] + }, + "S01_AXI_1": { + "interface_ports": [ + "S01_AXI", + "axi_crossbar_0/S01_AXI" + ] + }, + "Conn2": { + "interface_ports": [ + "M00_AXI_0", + "axi_crossbar_0/M00_AXI" + ] + }, + "S00_AXI_1": { + "interface_ports": [ + "S00_AXI", + "axi_crossbar_0/S00_AXI" + ] } }, "nets": { @@ -1819,10 +1819,10 @@ } }, "interface_nets": { - "S_AXIS_S2MM_1": { + "Conn2": { "interface_ports": [ - "S_AXIS_S2MM", - "axi_datamover_0/S_AXIS_S2MM" + "S_AXIS_S2MM_CMD", + "axi_datamover_0/S_AXIS_S2MM_CMD" ] }, "Conn3": { @@ -1831,10 +1831,10 @@ "axi_datamover_0/M_AXI_S2MM" ] }, - "Conn2": { + "S_AXIS_S2MM_1": { "interface_ports": [ - "S_AXIS_S2MM_CMD", - "axi_datamover_0/S_AXIS_S2MM_CMD" + "S_AXIS_S2MM", + "axi_datamover_0/S_AXIS_S2MM" ] } }, @@ -2928,6 +2928,15 @@ "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2", "xci_name": "design_1_axi_fifo_mm_s_0_0", "parameters": { + "C_TX_FIFO_DEPTH": { + "value": "4096" + }, + "C_TX_FIFO_PE_THRESHOLD": { + "value": "5" + }, + "C_TX_FIFO_PF_THRESHOLD": { + "value": "4091" + }, "C_USE_RX_DATA": { "value": "0" }, @@ -2956,6 +2965,18 @@ } }, "interface_nets": { + "S00_AXI_1": { + "interface_ports": [ + "S00_AXI", + "axi_crossbar_0/S00_AXI" + ] + }, + "Conn1": { + "interface_ports": [ + "AXI_STR_TXD_0", + "axi_fifo_mm_s_0/AXI_STR_TXD" + ] + }, "axi_crossbar_0_M00_AXI": { "interface_ports": [ "axi_crossbar_0/M00_AXI", @@ -2967,18 +2988,6 @@ "axi_crossbar_0/M01_AXI", "axi_gpio_0/S_AXI" ] - }, - "Conn1": { - "interface_ports": [ - "AXI_STR_TXD_0", - "axi_fifo_mm_s_0/AXI_STR_TXD" - ] - }, - "S00_AXI_1": { - "interface_ports": [ - "S00_AXI", - "axi_crossbar_0/S00_AXI" - ] } }, "nets": { @@ -3202,30 +3211,30 @@ } }, "interface_nets": { - "PCIe_M_AXI_LITE": { - "interface_ports": [ - "M_AXI_LITE", - "xdma_0/M_AXI_LITE" - ] - }, "xdma_0_M_AXI1": { "interface_ports": [ "xdma_0/M_AXI", "axi_dwidth_converter_0/S_AXI" ] }, - "xdma_0_pcie_mgt": { - "interface_ports": [ - "pcie_mgt", - "xdma_0/pcie_mgt" - ] - }, "CLK_IN_D_0_1": { "interface_ports": [ "pcie", "util_ds_buf_0/CLK_IN_D" ] }, + "PCIe_M_AXI_LITE": { + "interface_ports": [ + "M_AXI_LITE", + "xdma_0/M_AXI_LITE" + ] + }, + "xdma_0_pcie_mgt": { + "interface_ports": [ + "pcie_mgt", + "xdma_0/pcie_mgt" + ] + }, "xdma_0_M_AXI": { "interface_ports": [ "M_AXI", @@ -3264,40 +3273,10 @@ } }, "interface_nets": { - "xdma_0_pcie_mgt": { + "S_AXI_0_1": { "interface_ports": [ - "pcie_mgt", - "PCIe/pcie_mgt" - ] - }, - "AXI_LITE_IO_AXI_STR_TXD_0": { - "interface_ports": [ - "AXI_STR_TXD_0", - "AXI_LITE_IO/AXI_STR_TXD_0" - ] - }, - "S_AXIS_S2MM_0_1": { - "interface_ports": [ - "S_AXIS_S2MM", - "Datamover/S_AXIS_S2MM" - ] - }, - "CLK_IN_D_0_1": { - "interface_ports": [ - "pcie", - "PCIe/pcie" - ] - }, - "xdma_0_M_AXI": { - "interface_ports": [ - "PCIe/M_AXI", - "Memory/S00_AXI" - ] - }, - "S_AXIS_S2MM_CMD_0_1": { - "interface_ports": [ - "S_AXIS_S2MM_CMD", - "Datamover/S_AXIS_S2MM_CMD" + "S_AXI_0", + "Memory/S_AXI_0" ] }, "Memory_M00_AXI_0": { @@ -3306,10 +3285,40 @@ "Memory/M00_AXI_0" ] }, - "Datamover_M_AXI_S2MM": { + "xdma_0_M_AXI": { "interface_ports": [ - "Datamover/M_AXI_S2MM", - "Memory/S01_AXI" + "PCIe/M_AXI", + "Memory/S00_AXI" + ] + }, + "xdma_0_pcie_mgt": { + "interface_ports": [ + "pcie_mgt", + "PCIe/pcie_mgt" + ] + }, + "S_AXIS_S2MM_0_1": { + "interface_ports": [ + "S_AXIS_S2MM", + "Datamover/S_AXIS_S2MM" + ] + }, + "S_AXIS_S2MM_CMD_0_1": { + "interface_ports": [ + "S_AXIS_S2MM_CMD", + "Datamover/S_AXIS_S2MM_CMD" + ] + }, + "AXI_LITE_IO_AXI_STR_TXD_0": { + "interface_ports": [ + "AXI_STR_TXD_0", + "AXI_LITE_IO/AXI_STR_TXD_0" + ] + }, + "CLK_IN_D_0_1": { + "interface_ports": [ + "pcie", + "PCIe/pcie" ] }, "PCIe_M_AXI_LITE": { @@ -3318,10 +3327,10 @@ "AXI_LITE_IO/S00_AXI" ] }, - "S_AXI_0_1": { + "Datamover_M_AXI_S2MM": { "interface_ports": [ - "S_AXI_0", - "Memory/S_AXI_0" + "Datamover/M_AXI_S2MM", + "Memory/S01_AXI" ] }, "Memory_DDR3_0": { diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bxml b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bxml index 70ff69e..0d8edaf 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bxml +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bxml @@ -2,14 +2,14 @@ Composite Fileset - - - - + + + + - + @@ -25,7 +25,7 @@ - + @@ -49,7 +49,7 @@ - + @@ -73,7 +73,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -89,7 +89,7 @@ - + @@ -97,7 +97,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -124,7 +124,7 @@ - + diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v index 985d655..6554ed4 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v @@ -1,7 +1,7 @@ //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 -//Date : Sun Feb 13 11:02:18 2022 +//Date : Wed May 11 18:45:19 2022 //Host : DESKTOP-J72MK93 running 64-bit major release (build 9200) //Command : generate_target design_1_wrapper.bd //Design : design_1_wrapper diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh index 9ec29da..93ad84a 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh @@ -1,5 +1,5 @@  - + @@ -65,279 +65,14 @@ - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -540,16 +275,6 @@ - - - - - - - - - - @@ -595,6 +320,21 @@ + + + + + + + + + + + + + + + @@ -615,6 +355,266 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2542,11 +2542,11 @@ - + - + diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl index c623d45..95cbe5c 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl @@ -1308,6 +1308,9 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } { # Create instance: axi_fifo_mm_s_0, and set properties set axi_fifo_mm_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_fifo_mm_s:4.2 axi_fifo_mm_s_0 ] set_property -dict [ list \ + CONFIG.C_TX_FIFO_DEPTH {4096} \ + CONFIG.C_TX_FIFO_PE_THRESHOLD {5} \ + CONFIG.C_TX_FIFO_PF_THRESHOLD {4091} \ CONFIG.C_USE_RX_DATA {0} \ CONFIG.C_USE_TX_CTRL {0} \ ] $axi_fifo_mm_s_0 diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.dcp b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.dcp index ac95baf..766b515 100644 Binary files a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.dcp and b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.dcp differ diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci index a89f85c..05f2851 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci @@ -145,9 +145,9 @@ 32 4 0 - 512 + 4096 5 - 507 + 4091 0 0 0 @@ -183,9 +183,9 @@ 4 AXI4LITE 0 - 512 + 4096 5 - 507 + 4091 false 0 0 @@ -269,6 +269,9 @@ + + + diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xml b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xml index 61e5d35..0608972 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xml +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xml @@ -2729,7 +2729,7 @@ If the number of packets received is one, then this register returns the value o outputProductCRC - 9:0b3eebe4 + 9:98214153 @@ -2743,11 +2743,11 @@ If the number of packets received is one, then this register returns the value o GENtimestamp - Fri Jan 21 02:05:28 UTC 2022 + Wed May 11 22:45:19 UTC 2022 outputProductCRC - 9:0b3eebe4 + 9:98214153 @@ -2763,11 +2763,11 @@ If the number of packets received is one, then this register returns the value o GENtimestamp - Fri Jan 21 02:05:28 UTC 2022 + Wed May 11 22:45:19 UTC 2022 outputProductCRC - 9:0b3eebe4 + 9:98214153 @@ -2798,7 +2798,7 @@ If the number of packets received is one, then this register returns the value o outputProductCRC - 9:ec828180 + 9:a28c6e28 @@ -2814,11 +2814,11 @@ If the number of packets received is one, then this register returns the value o GENtimestamp - Fri Jan 21 02:05:28 UTC 2022 + Wed May 11 22:45:19 UTC 2022 outputProductCRC - 9:ec828180 + 9:a28c6e28 @@ -2832,11 +2832,11 @@ If the number of packets received is one, then this register returns the value o GENtimestamp - Fri Jan 21 03:00:03 UTC 2022 + Wed May 11 22:46:03 UTC 2022 outputProductCRC - 9:0b3eebe4 + 9:98214153 @@ -4989,7 +4989,7 @@ If the number of packets received is one, then this register returns the value o C_TX_FIFO_DEPTH Tx Fifo Depth - 512 + 4096 C_RX_FIFO_DEPTH @@ -5009,7 +5009,7 @@ If the number of packets received is one, then this register returns the value o C_TX_FIFO_PF_THRESHOLD Tx PF Threshold - 507 + 4091 C_TX_FIFO_PE_THRESHOLD @@ -5439,12 +5439,12 @@ If the number of packets received is one, then this register returns the value o C_TX_FIFO_PE_THRESHOLD Transmit Fifo Programable Empty Threshold - 5 + 5 C_TX_FIFO_PF_THRESHOLD Transmit Fifo Programable Full Threshold - 507 + 4091 C_RX_FIFO_DEPTH @@ -5454,7 +5454,7 @@ If the number of packets received is one, then this register returns the value o C_TX_FIFO_DEPTH Transmit Fifo Depth - 512 + 4096 C_HIGHADDR @@ -5643,6 +5643,9 @@ If the number of packets received is one, then this register returns the value o + + + diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v index 78c34e0..30d2049 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 -// Date : Thu Jan 20 22:00:03 2022 +// Date : Wed May 11 18:46:03 2022 // Host : DESKTOP-J72MK93 running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -// c:/Users/Aleksa/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v +// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_Rev2/dso_top_Rev2.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v // Design : design_1_axi_fifo_mm_s_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -142,9 +142,9 @@ module design_1_axi_fifo_mm_s_0_0 (* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_ID_WIDTH = "4" *) (* C_TX_CASCADE_HEIGHT = "0" *) - (* C_TX_FIFO_DEPTH = "512" *) + (* C_TX_FIFO_DEPTH = "4096" *) (* C_TX_FIFO_PE_THRESHOLD = "5" *) - (* C_TX_FIFO_PF_THRESHOLD = "507" *) + (* C_TX_FIFO_PF_THRESHOLD = "4091" *) (* C_USE_RX_CUT_THROUGH = "0" *) (* C_USE_RX_DATA = "0" *) (* C_USE_TX_CTRL = "0" *) @@ -244,26 +244,25 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 , \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 , Bus_RNW_reg_reg_0, - \s_axi_wdata[25] , + \s_axi_wdata[27] , + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 , \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 , - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 , - sig_tx_channel_reset_reg, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3 , + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1 , + E, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 , - sig_txd_sb_wr_en, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 , D, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 , - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 , - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1 , - Bus_RNW_reg_reg_1, - E, + sig_tx_channel_reset_reg, + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1 , + \s_axi_wdata[31] , cs_ce_clr, start2, s_axi_aclk, s_axi_wdata, - \sig_register_array_reg[0][6] , - sig_txd_sb_wr_en_reg, + axi_str_txd_tvalid, + axi_str_txd_tlast, + IP2Bus_Error1_in, sig_str_rst_reg, \sig_ip2bus_data_reg[10] , Q, @@ -273,34 +272,32 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder \sig_ip2bus_data_reg[6] , \sig_ip2bus_data_reg[4] , \sig_ip2bus_data_reg[3] , - sig_txd_sb_wr_en_reg_0, - IP2Bus_Error1_in, + IP2Bus_Error_reg, sig_Bus2IP_RNW, \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0 ); output sig_Bus2IP_CS; output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ; output \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ; output Bus_RNW_reg_reg_0; - output \s_axi_wdata[25] ; + output \s_axi_wdata[27] ; + output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ; output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ; - output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 ; - output sig_tx_channel_reset_reg; - output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3 ; + output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1 ; + output [0:0]E; output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ; - output sig_txd_sb_wr_en; output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ; output [6:0]D; output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ; - output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ; - output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1 ; - output [12:0]Bus_RNW_reg_reg_1; - output [0:0]E; + output sig_tx_channel_reset_reg; + output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1 ; + output [12:0]\s_axi_wdata[31] ; input cs_ce_clr; input start2; input s_axi_aclk; input [12:0]s_axi_wdata; - input \sig_register_array_reg[0][6] ; - input sig_txd_sb_wr_en_reg; + input axi_str_txd_tvalid; + input axi_str_txd_tlast; + input IP2Bus_Error1_in; input sig_str_rst_reg; input \sig_ip2bus_data_reg[10] ; input [6:0]Q; @@ -310,21 +307,17 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder input \sig_ip2bus_data_reg[6] ; input \sig_ip2bus_data_reg[4] ; input \sig_ip2bus_data_reg[3] ; - input sig_txd_sb_wr_en_reg_0; - input IP2Bus_Error1_in; + input IP2Bus_Error_reg; input sig_Bus2IP_RNW; input [3:0]\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0 ; wire Bus_RNW_reg_i_1_n_0; wire Bus_RNW_reg_reg_0; - wire [12:0]Bus_RNW_reg_reg_1; wire [6:0]D; wire [0:0]E; wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ; wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ; wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ; - wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 ; - wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3 ; wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg ; wire \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg ; wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ; @@ -332,10 +325,11 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ; wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ; wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ; + wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1 ; wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ; - wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ; - wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1 ; wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ; + wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ; + wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1 ; wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ; wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ; wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ; @@ -343,7 +337,10 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder wire \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg ; wire [3:0]\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0 ; wire IP2Bus_Error1_in; + wire IP2Bus_Error_reg; wire [6:0]Q; + wire axi_str_txd_tlast; + wire axi_str_txd_tvalid; wire ce_expnd_i_0; wire ce_expnd_i_1; wire ce_expnd_i_10; @@ -360,7 +357,8 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder wire cs_ce_clr; wire s_axi_aclk; wire [12:0]s_axi_wdata; - wire \s_axi_wdata[25] ; + wire \s_axi_wdata[27] ; + wire [12:0]\s_axi_wdata[31] ; wire sig_Bus2IP_CS; wire sig_Bus2IP_RNW; wire \sig_ip2bus_data[3]_i_2_n_0 ; @@ -373,18 +371,15 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder wire \sig_ip2bus_data_reg[9] ; wire \sig_register_array[1][0]_i_3_n_0 ; wire \sig_register_array[1][0]_i_4_n_0 ; - wire \sig_register_array_reg[0][6] ; + wire \sig_register_array[1][0]_i_5_n_0 ; + wire \sig_register_array[1][0]_i_6_n_0 ; wire sig_str_rst_i_3_n_0; wire sig_str_rst_reg; wire sig_tx_channel_reset_reg; - wire sig_txd_sb_wr_en; - wire sig_txd_sb_wr_en_reg; - wire sig_txd_sb_wr_en_reg_0; + wire \sig_txd_wr_data[31]_i_4_n_0 ; wire \sig_txd_wr_data[31]_i_5_n_0 ; - wire sig_txd_wr_en_i_3_n_0; wire start2; - (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'hB8)) Bus_RNW_reg_i_1 @@ -521,14 +516,14 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder .D(start2), .Q(sig_Bus2IP_CS), .R(cs_ce_clr)); - (* SOFT_HLUTNM = "soft_lutpair41" *) - LUT4 #( - .INIT(16'hFBFF)) + LUT5 #( + .INIT(32'hFFFFFBFF)) \sig_ip2bus_data[0]_i_2 - (.I0(\sig_register_array[1][0]_i_3_n_0 ), + (.I0(\sig_register_array[1][0]_i_5_n_0 ), .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(\sig_register_array[1][0]_i_4_n_0 ), + .I2(\sig_register_array[1][0]_i_3_n_0 ), .I3(Bus_RNW_reg_reg_0), + .I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), .O(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 )); LUT4 #( .INIT(16'h4F44)) @@ -539,15 +534,15 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder .I3(Q[0]), .O(D[0])); LUT6 #( - .INIT(64'hFFFFFFFBFFFFFFFF)) - \sig_ip2bus_data[22]_i_2 - (.I0(sig_str_rst_i_3_n_0), - .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), - .I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), - .I4(\sig_register_array[1][0]_i_4_n_0 ), - .I5(Bus_RNW_reg_reg_0), - .O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 )); + .INIT(64'hFFFFFFFFFFEFFFFF)) + \sig_ip2bus_data[19]_i_2 + (.I0(\sig_register_array[1][0]_i_6_n_0 ), + .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + .I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), + .I3(\sig_register_array[1][0]_i_3_n_0 ), + .I4(Bus_RNW_reg_reg_0), + .I5(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), + .O(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 )); LUT4 #( .INIT(16'h4F44)) \sig_ip2bus_data[3]_i_1 @@ -556,15 +551,15 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder .I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ), .I3(Q[6]), .O(D[6])); - (* SOFT_HLUTNM = "soft_lutpair38" *) - LUT5 #( - .INIT(32'hFFEFFFFF)) + LUT6 #( + .INIT(64'hFFFFFFEFFFFFFFFF)) \sig_ip2bus_data[3]_i_2 - (.I0(\sig_register_array[1][0]_i_3_n_0 ), + (.I0(\sig_register_array[1][0]_i_5_n_0 ), .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), .I2(Bus_RNW_reg_reg_0), - .I3(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), - .I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), + .I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), + .I4(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), + .I5(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), .O(\sig_ip2bus_data[3]_i_2_n_0 )); LUT4 #( .INIT(16'h4F44)) @@ -606,238 +601,229 @@ module design_1_axi_fifo_mm_s_0_0_address_decoder .I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ), .I3(Q[1]), .O(D[1])); - LUT4 #( - .INIT(16'hFFEF)) + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT5 #( + .INIT(32'hFFFFFFEF)) \sig_register_array[0][3]_i_2 (.I0(sig_str_rst_i_3_n_0), .I1(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), - .I3(\sig_register_array_reg[0][6] ), - .O(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 )); + .I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), + .I4(IP2Bus_Error1_in), + .O(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) LUT2 #( .INIT(4'hB)) \sig_register_array[0][4]_i_2 - (.I0(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ), - .I1(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 ), - .O(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3 )); - LUT6 #( - .INIT(64'hAEAEAEAEAEAEFFAE)) - \sig_register_array[0][6]_i_2 - (.I0(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ), - .I1(s_axi_wdata[6]), - .I2(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 ), - .I3(sig_tx_channel_reset_reg), - .I4(\sig_register_array_reg[0][6] ), - .I5(sig_txd_sb_wr_en_reg), - .O(\s_axi_wdata[25] )); - LUT6 #( - .INIT(64'hF0F0F0F0F0F0F0F4)) - \sig_register_array[1][0]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + (.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ), + .I1(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ), + .O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT5 #( + .INIT(32'hFFAEAEAE)) + \sig_register_array[0][4]_i_3 + (.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ), + .I1(s_axi_wdata[8]), .I2(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ), + .I3(axi_str_txd_tvalid), + .I4(axi_str_txd_tlast), + .O(\s_axi_wdata[27] )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAAB)) + \sig_register_array[1][0]_i_1 + (.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ), + .I1(IP2Bus_Error1_in), + .I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), .I3(\sig_register_array[1][0]_i_3_n_0 ), - .I4(IP2Bus_Error1_in), - .I5(\sig_register_array[1][0]_i_4_n_0 ), + .I4(\sig_register_array[1][0]_i_4_n_0 ), + .I5(\sig_register_array[1][0]_i_5_n_0 ), .O(E)); - (* SOFT_HLUTNM = "soft_lutpair41" *) - LUT3 #( - .INIT(8'h40)) + LUT2 #( + .INIT(4'h2)) \sig_register_array[1][0]_i_2 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[12]), - .O(Bus_RNW_reg_reg_1[12])); - LUT3 #( - .INIT(8'hFE)) - \sig_register_array[1][0]_i_3 - (.I0(sig_str_rst_i_3_n_0), - .I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), - .I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), - .O(\sig_register_array[1][0]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair38" *) + (.I0(s_axi_wdata[12]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [12])); + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'hE)) - \sig_register_array[1][0]_i_4 + \sig_register_array[1][0]_i_3 (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), .I1(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), + .O(\sig_register_array[1][0]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'hB)) + \sig_register_array[1][0]_i_4 + (.I0(Bus_RNW_reg_reg_0), + .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), .O(\sig_register_array[1][0]_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair47" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][10]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[2]), - .O(Bus_RNW_reg_reg_1[2])); - (* SOFT_HLUTNM = "soft_lutpair47" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][11]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[1]), - .O(Bus_RNW_reg_reg_1[1])); - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][12]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[0]), - .O(Bus_RNW_reg_reg_1[0])); - (* SOFT_HLUTNM = "soft_lutpair42" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][1]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[11]), - .O(Bus_RNW_reg_reg_1[11])); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][2]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[10]), - .O(Bus_RNW_reg_reg_1[10])); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][3]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[9]), - .O(Bus_RNW_reg_reg_1[9])); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][4]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[8]), - .O(Bus_RNW_reg_reg_1[8])); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][5]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[7]), - .O(Bus_RNW_reg_reg_1[7])); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][6]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[6]), - .O(Bus_RNW_reg_reg_1[6])); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][7]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[5]), - .O(Bus_RNW_reg_reg_1[5])); - (* SOFT_HLUTNM = "soft_lutpair46" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][8]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[4]), - .O(Bus_RNW_reg_reg_1[4])); - (* SOFT_HLUTNM = "soft_lutpair46" *) - LUT3 #( - .INIT(8'h40)) - \sig_register_array[1][9]_i_1 - (.I0(Bus_RNW_reg_reg_0), - .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I2(s_axi_wdata[3]), - .O(Bus_RNW_reg_reg_1[3])); - LUT6 #( - .INIT(64'h0000000000000400)) - sig_str_rst_i_1 - (.I0(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ), - .I1(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), - .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), - .I3(sig_str_rst_reg), - .I4(sig_str_rst_i_3_n_0), - .I5(IP2Bus_Error1_in), - .O(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 )); - (* SOFT_HLUTNM = "soft_lutpair39" *) + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'hE)) + \sig_register_array[1][0]_i_5 + (.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), + .I1(\sig_register_array[1][0]_i_6_n_0 ), + .O(\sig_register_array[1][0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'hFE)) - sig_str_rst_i_3 + \sig_register_array[1][0]_i_6 (.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ), - .I1(\sig_txd_wr_data[31]_i_5_n_0 ), + .I1(\sig_txd_wr_data[31]_i_4_n_0 ), .I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), - .O(sig_str_rst_i_3_n_0)); - LUT6 #( - .INIT(64'h0000000000000400)) - sig_tx_channel_reset_i_2 - (.I0(\sig_register_array[1][0]_i_4_n_0 ), - .I1(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), - .I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ), - .I3(sig_str_rst_reg), - .I4(\sig_register_array_reg[0][6] ), - .I5(\sig_txd_wr_data[31]_i_5_n_0 ), - .O(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 )); - LUT3 #( - .INIT(8'h08)) - sig_txd_sb_wr_en_i_1 - (.I0(sig_tx_channel_reset_reg), - .I1(sig_txd_sb_wr_en_reg), - .I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ), - .O(sig_txd_sb_wr_en)); - (* SOFT_HLUTNM = "soft_lutpair39" *) - LUT5 #( - .INIT(32'h00000010)) - \sig_txd_wr_data[31]_i_2 - (.I0(sig_txd_sb_wr_en_reg_0), + .O(\sig_register_array[1][0]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][10]_i_1 + (.I0(s_axi_wdata[2]), .I1(\sig_register_array[1][0]_i_4_n_0 ), - .I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ), - .I3(\sig_txd_wr_data[31]_i_5_n_0 ), - .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), - .O(sig_tx_channel_reset_reg)); - (* SOFT_HLUTNM = "soft_lutpair40" *) + .O(\s_axi_wdata[31] [2])); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][11]_i_1 + (.I0(s_axi_wdata[1]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [1])); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][12]_i_1 + (.I0(s_axi_wdata[0]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [0])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][1]_i_1 + (.I0(s_axi_wdata[11]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [11])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][2]_i_1 + (.I0(s_axi_wdata[10]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [10])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][3]_i_1 + (.I0(s_axi_wdata[9]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [9])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][4]_i_1 + (.I0(s_axi_wdata[8]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [8])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][5]_i_1 + (.I0(s_axi_wdata[7]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [7])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][6]_i_1 + (.I0(s_axi_wdata[6]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [6])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][7]_i_1 + (.I0(s_axi_wdata[5]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [5])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][8]_i_1 + (.I0(s_axi_wdata[4]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [4])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h2)) + \sig_register_array[1][9]_i_1 + (.I0(s_axi_wdata[3]), + .I1(\sig_register_array[1][0]_i_4_n_0 ), + .O(\s_axi_wdata[31] [3])); + LUT6 #( + .INIT(64'h0000000000000100)) + sig_str_rst_i_1 + (.I0(sig_str_rst_reg), + .I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), + .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), + .I3(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), + .I4(sig_str_rst_i_3_n_0), + .I5(IP2Bus_Error1_in), + .O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT4 #( .INIT(16'hFFFE)) - \sig_txd_wr_data[31]_i_4 - (.I0(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + sig_str_rst_i_3 + (.I0(\sig_register_array[1][0]_i_6_n_0 ), .I1(Bus_RNW_reg_reg_0), - .I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), + .I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), .I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), - .O(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 )); + .O(sig_str_rst_i_3_n_0)); + LUT6 #( + .INIT(64'h0000000000000010)) + sig_tx_channel_reset_i_2 + (.I0(sig_str_rst_reg), + .I1(IP2Bus_Error1_in), + .I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), + .I3(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ), + .I4(\sig_txd_wr_data[31]_i_5_n_0 ), + .I5(\sig_txd_wr_data[31]_i_4_n_0 ), + .O(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT5 #( + .INIT(32'h00000100)) + \sig_txd_wr_data[31]_i_3 + (.I0(\sig_txd_wr_data[31]_i_4_n_0 ), + .I1(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), + .I2(IP2Bus_Error_reg), + .I3(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ), + .I4(\sig_txd_wr_data[31]_i_5_n_0 ), + .O(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) - \sig_txd_wr_data[31]_i_5 + \sig_txd_wr_data[31]_i_4 (.I0(\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg ), .I1(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg ), .I2(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ), .I3(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg ), .I4(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ), .I5(\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg ), - .O(\sig_txd_wr_data[31]_i_5_n_0 )); + .O(\sig_txd_wr_data[31]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) LUT5 #( .INIT(32'hFFFFFFFE)) + \sig_txd_wr_data[31]_i_5 + (.I0(Bus_RNW_reg_reg_0), + .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + .I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), + .I3(\sig_register_array[1][0]_i_3_n_0 ), + .I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), + .O(\sig_txd_wr_data[31]_i_5_n_0 )); + LUT4 #( + .INIT(16'hFFEF)) sig_txd_wr_en_i_2 (.I0(sig_str_rst_i_3_n_0), - .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), - .I2(sig_txd_wr_en_i_3_n_0), - .I3(sig_txd_sb_wr_en_reg_0), - .I4(\sig_register_array[1][0]_i_4_n_0 ), - .O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1 )); - (* SOFT_HLUTNM = "soft_lutpair40" *) - LUT3 #( - .INIT(8'hEF)) - sig_txd_wr_en_i_3 - (.I0(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), - .I1(Bus_RNW_reg_reg_0), + .I1(IP2Bus_Error_reg), .I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ), - .O(sig_txd_wr_en_i_3_n_0)); + .I3(\sig_register_array[1][0]_i_3_n_0 ), + .O(sig_tx_channel_reset_reg)); endmodule (* C_AXI4_BASEADDR = "-2147479552" *) (* C_AXI4_HIGHADDR = "-2147471361" *) (* C_AXIS_TDEST_WIDTH = "4" *) @@ -847,8 +833,8 @@ endmodule (* C_HAS_AXIS_TUSER = "0" *) (* C_HIGHADDR = "1073938431" *) (* C_RX_CASCADE_HEIGHT = "0" *) (* C_RX_FIFO_DEPTH = "512" *) (* C_RX_FIFO_PE_THRESHOLD = "5" *) (* C_RX_FIFO_PF_THRESHOLD = "507" *) (* C_S_AXI4_DATA_WIDTH = "32" *) (* C_S_AXI_ADDR_WIDTH = "32" *) (* C_S_AXI_DATA_WIDTH = "32" *) -(* C_S_AXI_ID_WIDTH = "4" *) (* C_TX_CASCADE_HEIGHT = "0" *) (* C_TX_FIFO_DEPTH = "512" *) -(* C_TX_FIFO_PE_THRESHOLD = "5" *) (* C_TX_FIFO_PF_THRESHOLD = "507" *) (* C_USE_RX_CUT_THROUGH = "0" *) +(* C_S_AXI_ID_WIDTH = "4" *) (* C_TX_CASCADE_HEIGHT = "0" *) (* C_TX_FIFO_DEPTH = "4096" *) +(* C_TX_FIFO_PE_THRESHOLD = "5" *) (* C_TX_FIFO_PF_THRESHOLD = "4091" *) (* C_USE_RX_CUT_THROUGH = "0" *) (* C_USE_RX_DATA = "0" *) (* C_USE_TX_CTRL = "0" *) (* C_USE_TX_CUT_THROUGH = "0" *) (* C_USE_TX_DATA = "1" *) (* ORIG_REF_NAME = "axi_fifo_mm_s" *) module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s @@ -1026,9 +1012,9 @@ module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s wire \ ; wire \ ; wire COMP_IPIC2AXI_S_n_39; - wire COMP_IPIC2AXI_S_n_41; - wire COMP_IPIC2AXI_S_n_44; + wire COMP_IPIC2AXI_S_n_43; wire COMP_IPIC2AXI_S_n_45; + wire COMP_IPIC2AXI_S_n_46; wire COMP_IPIC2AXI_S_n_47; wire COMP_IPIC2AXI_S_n_48; wire COMP_IPIC2AXI_S_n_49; @@ -1041,19 +1027,16 @@ module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s wire COMP_IPIC2AXI_S_n_56; wire COMP_IPIC2AXI_S_n_57; wire COMP_IPIC2AXI_S_n_58; - wire COMP_IPIC2AXI_S_n_59; - wire COMP_IPIC2AXI_S_n_60; wire COMP_IPIF_n_10; wire COMP_IPIF_n_11; wire COMP_IPIF_n_12; wire COMP_IPIF_n_13; wire COMP_IPIF_n_14; - wire COMP_IPIF_n_16; + wire COMP_IPIF_n_15; + wire COMP_IPIF_n_23; wire COMP_IPIF_n_24; wire COMP_IPIF_n_25; - wire COMP_IPIF_n_26; - wire COMP_IPIF_n_27; - wire COMP_IPIF_n_41; + wire COMP_IPIF_n_39; wire COMP_IPIF_n_8; wire COMP_IPIF_n_9; wire IP2Bus_Error1_in; @@ -1091,7 +1074,6 @@ module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s wire [0:30]sig_ip2bus_data; wire [3:10]sig_ip2bus_data_1; wire [0:12]\sig_register_array[1]_0 ; - wire sig_txd_sb_wr_en; assign axi_str_rxd_tready = \ ; assign axi_str_txc_tdata[31] = \ ; @@ -1228,10 +1210,7 @@ module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; - assign s_axi_rdata[12] = \ ; - assign s_axi_rdata[11] = \ ; - assign s_axi_rdata[10] = \ ; - assign s_axi_rdata[9:1] = \^s_axi_rdata [9:1]; + assign s_axi_rdata[12:1] = \^s_axi_rdata [12:1]; assign s_axi_rdata[0] = \ ; assign s_axi_rresp[1] = \^s_axi_rresp [1]; assign s_axi_rresp[0] = \ ; @@ -1239,17 +1218,16 @@ module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s design_1_axi_fifo_mm_s_0_0_ipic2axi_s COMP_IPIC2AXI_S (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), .D({sig_ip2bus_data_1[3],sig_ip2bus_data_1[4],sig_ip2bus_data_1[6],sig_ip2bus_data_1[7],sig_ip2bus_data_1[8],sig_ip2bus_data_1[9],sig_ip2bus_data_1[10]}), - .E(COMP_IPIF_n_41), + .E(COMP_IPIF_n_12), .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ), .\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ), .IP2Bus_Error1_in(IP2Bus_Error1_in), - .IP2Bus_Error_reg_0(COMP_IPIF_n_26), + .IP2Bus_Error_reg_0(COMP_IPIF_n_24), .IP2Bus_RdAck_reg_0(s_axi_arready), .IP2Bus_RdAck_reg_1(COMP_IPIF_n_13), .IP2Bus_WrAck_reg_0(s_axi_awready), - .IP2Bus_WrAck_reg_1(COMP_IPIF_n_27), - .IPIC_STATE_reg_0(COMP_IPIC2AXI_S_n_41), - .Q({COMP_IPIC2AXI_S_n_47,COMP_IPIC2AXI_S_n_48,COMP_IPIC2AXI_S_n_49,COMP_IPIC2AXI_S_n_50,COMP_IPIC2AXI_S_n_51,COMP_IPIC2AXI_S_n_52,COMP_IPIC2AXI_S_n_53}), + .IP2Bus_WrAck_reg_1(COMP_IPIF_n_39), + .Q({COMP_IPIC2AXI_S_n_45,COMP_IPIC2AXI_S_n_46,COMP_IPIC2AXI_S_n_47,COMP_IPIC2AXI_S_n_48,COMP_IPIC2AXI_S_n_49,COMP_IPIC2AXI_S_n_50,COMP_IPIC2AXI_S_n_51}), .axi_str_txd_tdata(axi_str_txd_tdata), .axi_str_txd_tlast(axi_str_txd_tlast), .axi_str_txd_tready(axi_str_txd_tready), @@ -1261,52 +1239,50 @@ module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s .s_axi_aclk(s_axi_aclk), .s_axi_aresetn(s_axi_aresetn), .s_axi_wdata(s_axi_wdata), - .s_axi_wdata_0_sp_1(COMP_IPIC2AXI_S_n_45), - .s_axi_wdata_7_sp_1(COMP_IPIC2AXI_S_n_44), + .s_axi_wdata_7_sp_1(COMP_IPIC2AXI_S_n_43), .sig_Bus2IP_CS(sig_Bus2IP_CS), .sig_Bus2IP_Reset(sig_Bus2IP_Reset), - .\sig_ip2bus_data_reg[0]_0 ({sig_ip2bus_data[0],sig_ip2bus_data[1],sig_ip2bus_data[2],sig_ip2bus_data[3],sig_ip2bus_data[4],sig_ip2bus_data[5],sig_ip2bus_data[6],sig_ip2bus_data[7],sig_ip2bus_data[8],sig_ip2bus_data[9],sig_ip2bus_data[10],sig_ip2bus_data[11],sig_ip2bus_data[12],sig_ip2bus_data[22],sig_ip2bus_data[23],sig_ip2bus_data[24],sig_ip2bus_data[25],sig_ip2bus_data[26],sig_ip2bus_data[27],sig_ip2bus_data[28],sig_ip2bus_data[29],sig_ip2bus_data[30]}), - .\sig_ip2bus_data_reg[12]_0 (COMP_IPIF_n_24), - .\sig_ip2bus_data_reg[22]_0 (COMP_IPIF_n_25), - .\sig_register_array_reg[0][10]_0 (COMP_IPIC2AXI_S_n_57), - .\sig_register_array_reg[0][3]_0 (COMP_IPIC2AXI_S_n_55), + .\sig_ip2bus_data_reg[0]_0 ({sig_ip2bus_data[0],sig_ip2bus_data[1],sig_ip2bus_data[2],sig_ip2bus_data[3],sig_ip2bus_data[4],sig_ip2bus_data[5],sig_ip2bus_data[6],sig_ip2bus_data[7],sig_ip2bus_data[8],sig_ip2bus_data[9],sig_ip2bus_data[10],sig_ip2bus_data[11],sig_ip2bus_data[12],sig_ip2bus_data[19],sig_ip2bus_data[20],sig_ip2bus_data[21],sig_ip2bus_data[22],sig_ip2bus_data[23],sig_ip2bus_data[24],sig_ip2bus_data[25],sig_ip2bus_data[26],sig_ip2bus_data[27],sig_ip2bus_data[28],sig_ip2bus_data[29],sig_ip2bus_data[30]}), + .\sig_ip2bus_data_reg[12]_0 (COMP_IPIF_n_23), + .\sig_ip2bus_data_reg[19]_0 (COMP_IPIF_n_15), + .\sig_register_array_reg[0][10]_0 (COMP_IPIC2AXI_S_n_52), + .\sig_register_array_reg[0][3]_0 (COMP_IPIC2AXI_S_n_53), .\sig_register_array_reg[0][3]_1 (COMP_IPIF_n_10), - .\sig_register_array_reg[0][4]_0 (COMP_IPIC2AXI_S_n_54), - .\sig_register_array_reg[0][4]_1 (COMP_IPIF_n_12), - .\sig_register_array_reg[0][6]_0 (COMP_IPIC2AXI_S_n_56), - .\sig_register_array_reg[0][6]_1 (COMP_IPIF_n_8), - .\sig_register_array_reg[0][7]_0 (COMP_IPIC2AXI_S_n_58), - .\sig_register_array_reg[0][8]_0 (COMP_IPIC2AXI_S_n_60), - .\sig_register_array_reg[0][9]_0 (COMP_IPIC2AXI_S_n_59), + .\sig_register_array_reg[0][4]_0 (COMP_IPIC2AXI_S_n_55), + .\sig_register_array_reg[0][4]_1 (COMP_IPIF_n_11), + .\sig_register_array_reg[0][4]_2 (COMP_IPIF_n_8), + .\sig_register_array_reg[0][6]_0 (COMP_IPIC2AXI_S_n_57), + .\sig_register_array_reg[0][7]_0 (COMP_IPIC2AXI_S_n_54), + .\sig_register_array_reg[0][8]_0 (COMP_IPIC2AXI_S_n_56), + .\sig_register_array_reg[0][9]_0 (COMP_IPIC2AXI_S_n_58), .\sig_register_array_reg[1][0]_0 ({\sig_register_array[1]_0 [0],\sig_register_array[1]_0 [1],\sig_register_array[1]_0 [2],\sig_register_array[1]_0 [3],\sig_register_array[1]_0 [4],\sig_register_array[1]_0 [5],\sig_register_array[1]_0 [6],\sig_register_array[1]_0 [7],\sig_register_array[1]_0 [8],\sig_register_array[1]_0 [9],\sig_register_array[1]_0 [10],\sig_register_array[1]_0 [11],\sig_register_array[1]_0 [12]}), .sig_str_rst_reg_0(mm2s_prmry_reset_out_n), .sig_str_rst_reg_1(COMP_IPIF_n_9), .sig_tx_channel_reset_reg_0(COMP_IPIC2AXI_S_n_39), .sig_tx_channel_reset_reg_1(COMP_IPIF_n_14), - .sig_txd_sb_wr_en(sig_txd_sb_wr_en), - .\sig_txd_wr_data_reg[0]_0 (COMP_IPIF_n_16), - .\sig_txd_wr_data_reg[0]_1 (COMP_IPIF_n_11)); + .sig_txd_sb_wr_en_reg_0(COMP_IPIF_n_25)); design_1_axi_fifo_mm_s_0_0_axi_lite_ipif COMP_IPIF (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), - .Bus_RNW_reg_reg({\sig_register_array[1]_0 [0],\sig_register_array[1]_0 [1],\sig_register_array[1]_0 [2],\sig_register_array[1]_0 [3],\sig_register_array[1]_0 [4],\sig_register_array[1]_0 [5],\sig_register_array[1]_0 [6],\sig_register_array[1]_0 [7],\sig_register_array[1]_0 [8],\sig_register_array[1]_0 [9],\sig_register_array[1]_0 [10],\sig_register_array[1]_0 [11],\sig_register_array[1]_0 [12]}), .D({sig_ip2bus_data_1[3],sig_ip2bus_data_1[4],sig_ip2bus_data_1[6],sig_ip2bus_data_1[7],sig_ip2bus_data_1[8],sig_ip2bus_data_1[9],sig_ip2bus_data_1[10]}), - .E(COMP_IPIF_n_41), + .E(COMP_IPIF_n_12), .\FSM_onehot_state_reg[2] (s_axi_awready), .\FSM_onehot_state_reg[3] (s_axi_arready), .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ), - .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] (COMP_IPIF_n_9), - .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 (COMP_IPIF_n_10), - .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 (COMP_IPIF_n_12), - .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (COMP_IPIF_n_16), - .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (COMP_IPIF_n_24), + .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] (COMP_IPIF_n_10), + .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (COMP_IPIF_n_15), + .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (COMP_IPIF_n_23), .\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (COMP_IPIF_n_14), - .\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] (COMP_IPIF_n_25), - .\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 (COMP_IPIF_n_26), + .\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 (COMP_IPIF_n_25), + .\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (COMP_IPIF_n_9), + .\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (COMP_IPIF_n_11), .\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ), .IP2Bus_Error1_in(IP2Bus_Error1_in), - .Q({COMP_IPIC2AXI_S_n_47,COMP_IPIC2AXI_S_n_48,COMP_IPIC2AXI_S_n_49,COMP_IPIC2AXI_S_n_50,COMP_IPIC2AXI_S_n_51,COMP_IPIC2AXI_S_n_52,COMP_IPIC2AXI_S_n_53}), + .IP2Bus_Error_reg(COMP_IPIC2AXI_S_n_39), + .Q({COMP_IPIC2AXI_S_n_45,COMP_IPIC2AXI_S_n_46,COMP_IPIC2AXI_S_n_47,COMP_IPIC2AXI_S_n_48,COMP_IPIC2AXI_S_n_49,COMP_IPIC2AXI_S_n_50,COMP_IPIC2AXI_S_n_51}), + .axi_str_txd_tlast(axi_str_txd_tlast), + .axi_str_txd_tvalid(axi_str_txd_tvalid), .bus2ip_rnw_i_reg(COMP_IPIF_n_13), - .bus2ip_rnw_i_reg_0(COMP_IPIF_n_27), + .bus2ip_rnw_i_reg_0(COMP_IPIF_n_39), .cs_ce_clr(\I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr ), .p_1_in(p_1_in), .s_axi_aclk(s_axi_aclk), @@ -1317,29 +1293,26 @@ module design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s .s_axi_bready(s_axi_bready), .s_axi_bresp(\^s_axi_bresp ), .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata({\^s_axi_rdata [31:19],\^s_axi_rdata [9:1]}), - .\s_axi_rdata_i_reg[31] ({sig_ip2bus_data[0],sig_ip2bus_data[1],sig_ip2bus_data[2],sig_ip2bus_data[3],sig_ip2bus_data[4],sig_ip2bus_data[5],sig_ip2bus_data[6],sig_ip2bus_data[7],sig_ip2bus_data[8],sig_ip2bus_data[9],sig_ip2bus_data[10],sig_ip2bus_data[11],sig_ip2bus_data[12],sig_ip2bus_data[22],sig_ip2bus_data[23],sig_ip2bus_data[24],sig_ip2bus_data[25],sig_ip2bus_data[26],sig_ip2bus_data[27],sig_ip2bus_data[28],sig_ip2bus_data[29],sig_ip2bus_data[30]}), + .s_axi_rdata({\^s_axi_rdata [31:19],\^s_axi_rdata [12:1]}), + .\s_axi_rdata_i_reg[31] ({sig_ip2bus_data[0],sig_ip2bus_data[1],sig_ip2bus_data[2],sig_ip2bus_data[3],sig_ip2bus_data[4],sig_ip2bus_data[5],sig_ip2bus_data[6],sig_ip2bus_data[7],sig_ip2bus_data[8],sig_ip2bus_data[9],sig_ip2bus_data[10],sig_ip2bus_data[11],sig_ip2bus_data[12],sig_ip2bus_data[19],sig_ip2bus_data[20],sig_ip2bus_data[21],sig_ip2bus_data[22],sig_ip2bus_data[23],sig_ip2bus_data[24],sig_ip2bus_data[25],sig_ip2bus_data[26],sig_ip2bus_data[27],sig_ip2bus_data[28],sig_ip2bus_data[29],sig_ip2bus_data[30]}), .s_axi_rready(s_axi_rready), .s_axi_rresp(\^s_axi_rresp ), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata[31:19]), - .\s_axi_wdata[25] (COMP_IPIF_n_8), + .\s_axi_wdata[27] (COMP_IPIF_n_8), + .\s_axi_wdata[31] ({\sig_register_array[1]_0 [0],\sig_register_array[1]_0 [1],\sig_register_array[1]_0 [2],\sig_register_array[1]_0 [3],\sig_register_array[1]_0 [4],\sig_register_array[1]_0 [5],\sig_register_array[1]_0 [6],\sig_register_array[1]_0 [7],\sig_register_array[1]_0 [8],\sig_register_array[1]_0 [9],\sig_register_array[1]_0 [10],\sig_register_array[1]_0 [11],\sig_register_array[1]_0 [12]}), .s_axi_wvalid(s_axi_wvalid), .sig_Bus2IP_CS(sig_Bus2IP_CS), .sig_Bus2IP_Reset(sig_Bus2IP_Reset), - .\sig_ip2bus_data_reg[10] (COMP_IPIC2AXI_S_n_57), - .\sig_ip2bus_data_reg[3] (COMP_IPIC2AXI_S_n_55), - .\sig_ip2bus_data_reg[4] (COMP_IPIC2AXI_S_n_54), - .\sig_ip2bus_data_reg[6] (COMP_IPIC2AXI_S_n_56), - .\sig_ip2bus_data_reg[7] (COMP_IPIC2AXI_S_n_58), - .\sig_ip2bus_data_reg[8] (COMP_IPIC2AXI_S_n_60), - .\sig_ip2bus_data_reg[9] (COMP_IPIC2AXI_S_n_59), - .\sig_register_array_reg[0][6] (COMP_IPIC2AXI_S_n_41), - .sig_str_rst_reg(COMP_IPIC2AXI_S_n_44), - .sig_tx_channel_reset_reg(COMP_IPIF_n_11), - .sig_txd_sb_wr_en(sig_txd_sb_wr_en), - .sig_txd_sb_wr_en_reg(COMP_IPIC2AXI_S_n_45), - .sig_txd_sb_wr_en_reg_0(COMP_IPIC2AXI_S_n_39)); + .\sig_ip2bus_data_reg[10] (COMP_IPIC2AXI_S_n_52), + .\sig_ip2bus_data_reg[3] (COMP_IPIC2AXI_S_n_53), + .\sig_ip2bus_data_reg[4] (COMP_IPIC2AXI_S_n_55), + .\sig_ip2bus_data_reg[6] (COMP_IPIC2AXI_S_n_57), + .\sig_ip2bus_data_reg[7] (COMP_IPIC2AXI_S_n_54), + .\sig_ip2bus_data_reg[8] (COMP_IPIC2AXI_S_n_56), + .\sig_ip2bus_data_reg[9] (COMP_IPIC2AXI_S_n_58), + .sig_str_rst_reg(COMP_IPIC2AXI_S_n_43), + .sig_tx_channel_reset_reg(COMP_IPIF_n_24)); GND GND (.G(\ )); VCC VCC @@ -1356,22 +1329,20 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif s_axi_rvalid, s_axi_bvalid, s_axi_bresp, - \s_axi_wdata[25] , + \s_axi_wdata[27] , + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] , \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] , - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 , - sig_tx_channel_reset_reg, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 , + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 , + E, bus2ip_rnw_i_reg, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] , - sig_txd_sb_wr_en, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] , D, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 , - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] , - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 , + sig_tx_channel_reset_reg, + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 , + \s_axi_wdata[31] , bus2ip_rnw_i_reg_0, - Bus_RNW_reg_reg, - E, s_axi_rdata, sig_Bus2IP_Reset, s_axi_aclk, @@ -1383,8 +1354,8 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif s_axi_wvalid, s_axi_awvalid, s_axi_wdata, - \sig_register_array_reg[0][6] , - sig_txd_sb_wr_en_reg, + axi_str_txd_tvalid, + axi_str_txd_tlast, IP2Bus_Error1_in, sig_str_rst_reg, \sig_ip2bus_data_reg[10] , @@ -1395,7 +1366,7 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif \sig_ip2bus_data_reg[6] , \sig_ip2bus_data_reg[4] , \sig_ip2bus_data_reg[3] , - sig_txd_sb_wr_en_reg_0, + IP2Bus_Error_reg, s_axi_rready, s_axi_bready, s_axi_araddr, @@ -1409,23 +1380,21 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif output s_axi_rvalid; output s_axi_bvalid; output [0:0]s_axi_bresp; - output \s_axi_wdata[25] ; + output \s_axi_wdata[27] ; + output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ; output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] ; - output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ; - output sig_tx_channel_reset_reg; - output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ; + output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ; + output [0:0]E; output bus2ip_rnw_i_reg; output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ; - output sig_txd_sb_wr_en; output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ; output [6:0]D; output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ; - output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ; - output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ; + output sig_tx_channel_reset_reg; + output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ; + output [12:0]\s_axi_wdata[31] ; output bus2ip_rnw_i_reg_0; - output [12:0]Bus_RNW_reg_reg; - output [0:0]E; - output [21:0]s_axi_rdata; + output [24:0]s_axi_rdata; input sig_Bus2IP_Reset; input s_axi_aclk; input cs_ce_clr; @@ -1436,8 +1405,8 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif input s_axi_wvalid; input s_axi_awvalid; input [12:0]s_axi_wdata; - input \sig_register_array_reg[0][6] ; - input sig_txd_sb_wr_en_reg; + input axi_str_txd_tvalid; + input axi_str_txd_tlast; input IP2Bus_Error1_in; input sig_str_rst_reg; input \sig_ip2bus_data_reg[10] ; @@ -1448,31 +1417,32 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif input \sig_ip2bus_data_reg[6] ; input \sig_ip2bus_data_reg[4] ; input \sig_ip2bus_data_reg[3] ; - input sig_txd_sb_wr_en_reg_0; + input IP2Bus_Error_reg; input s_axi_rready; input s_axi_bready; input [3:0]s_axi_araddr; input [3:0]s_axi_awaddr; - input [21:0]\s_axi_rdata_i_reg[31] ; + input [24:0]\s_axi_rdata_i_reg[31] ; wire Bus_RNW_reg; - wire [12:0]Bus_RNW_reg_reg; wire [6:0]D; wire [0:0]E; wire \FSM_onehot_state_reg[2] ; wire \FSM_onehot_state_reg[3] ; wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ; wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] ; - wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ; - wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ; wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ; wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ; wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ; - wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ; - wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ; + wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ; + wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ; + wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ; wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ; wire IP2Bus_Error1_in; + wire IP2Bus_Error_reg; wire [6:0]Q; + wire axi_str_txd_tlast; + wire axi_str_txd_tvalid; wire bus2ip_rnw_i_reg; wire bus2ip_rnw_i_reg_0; wire cs_ce_clr; @@ -1485,13 +1455,14 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif wire s_axi_bready; wire [0:0]s_axi_bresp; wire s_axi_bvalid; - wire [21:0]s_axi_rdata; - wire [21:0]\s_axi_rdata_i_reg[31] ; + wire [24:0]s_axi_rdata; + wire [24:0]\s_axi_rdata_i_reg[31] ; wire s_axi_rready; wire [0:0]s_axi_rresp; wire s_axi_rvalid; wire [12:0]s_axi_wdata; - wire \s_axi_wdata[25] ; + wire \s_axi_wdata[27] ; + wire [12:0]\s_axi_wdata[31] ; wire s_axi_wvalid; wire sig_Bus2IP_CS; wire sig_Bus2IP_Reset; @@ -1502,32 +1473,29 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif wire \sig_ip2bus_data_reg[7] ; wire \sig_ip2bus_data_reg[8] ; wire \sig_ip2bus_data_reg[9] ; - wire \sig_register_array_reg[0][6] ; wire sig_str_rst_reg; wire sig_tx_channel_reset_reg; - wire sig_txd_sb_wr_en; - wire sig_txd_sb_wr_en_reg; - wire sig_txd_sb_wr_en_reg_0; design_1_axi_fifo_mm_s_0_0_slave_attachment I_SLAVE_ATTACHMENT (.Bus_RNW_reg_reg(Bus_RNW_reg), - .Bus_RNW_reg_reg_0(Bus_RNW_reg_reg), .D(D), .E(E), .\FSM_onehot_state_reg[2]_0 (\FSM_onehot_state_reg[2] ), .\FSM_onehot_state_reg[3]_0 (\FSM_onehot_state_reg[3] ), .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ), .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] ), - .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), - .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ), .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ), .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ), .\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ), - .\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ), - .\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ), + .\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ), + .\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ), + .\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ), .\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ), .IP2Bus_Error1_in(IP2Bus_Error1_in), + .IP2Bus_Error_reg(IP2Bus_Error_reg), .Q(Q), + .axi_str_txd_tlast(axi_str_txd_tlast), + .axi_str_txd_tvalid(axi_str_txd_tvalid), .bus2ip_rnw_i_reg_0(bus2ip_rnw_i_reg), .bus2ip_rnw_i_reg_1(bus2ip_rnw_i_reg_0), .cs_ce_clr(cs_ce_clr), @@ -1546,7 +1514,8 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif .s_axi_rresp(s_axi_rresp), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), - .\s_axi_wdata[25] (\s_axi_wdata[25] ), + .\s_axi_wdata[27] (\s_axi_wdata[27] ), + .\s_axi_wdata[31] (\s_axi_wdata[31] ), .s_axi_wvalid(s_axi_wvalid), .sig_Bus2IP_CS(sig_Bus2IP_CS), .sig_Bus2IP_Reset(sig_Bus2IP_Reset), @@ -1557,12 +1526,8 @@ module design_1_axi_fifo_mm_s_0_0_axi_lite_ipif .\sig_ip2bus_data_reg[7] (\sig_ip2bus_data_reg[7] ), .\sig_ip2bus_data_reg[8] (\sig_ip2bus_data_reg[8] ), .\sig_ip2bus_data_reg[9] (\sig_ip2bus_data_reg[9] ), - .\sig_register_array_reg[0][6] (\sig_register_array_reg[0][6] ), .sig_str_rst_reg(sig_str_rst_reg), - .sig_tx_channel_reset_reg(sig_tx_channel_reset_reg), - .sig_txd_sb_wr_en(sig_txd_sb_wr_en), - .sig_txd_sb_wr_en_reg(sig_txd_sb_wr_en_reg), - .sig_txd_sb_wr_en_reg_0(sig_txd_sb_wr_en_reg_0)); + .sig_tx_channel_reset_reg(sig_tx_channel_reset_reg)); endmodule (* ORIG_REF_NAME = "axis_fg" *) @@ -1574,71 +1539,63 @@ module design_1_axi_fifo_mm_s_0_0_axis_fg wr_data_count_axis, prog_empty_axis, s_aresetn, - \gen_wr_a.gen_word_narrow.mem_reg , sig_txd_wr_en, - \gwdc.wr_data_count_i_reg[9] , - D, + \gwdc.wr_data_count_i_reg[12] , + S, + DI, + \gwdc.wr_data_count_i_reg[7] , + \gwdc.wr_data_count_i_reg[3] , + \gwdc.wr_data_count_i_reg[0] , \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg , \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg , IP2Bus_Error_reg, - E, s_axi_aclk, Q, - \gen_wr_a.gen_word_narrow.mem_reg_0 , + \gen_wr_a.gen_word_narrow.mem_reg_5 , axi_str_txd_tready, start_wr, txd_wr_en, - \sig_register_array_reg[0][4] , - \sig_register_array_reg[0][4]_0 , - s_axi_wdata, IP2Bus_Error_reg_0, sig_txd_prog_full_d1, sig_txd_prog_empty_d1, - \gen_wr_a.gen_word_narrow.mem_reg_1 , + \gen_wr_a.gen_word_narrow.mem_reg_3 , p_1_in, s_axi_aresetn, IP2Bus_Error_reg_1, Axi_Str_RxD_AReset, - mm2s_prmry_reset_out_n, - \sig_txd_wr_data_reg[0] , - \sig_txd_wr_data_reg[0]_0 , - \sig_txd_wr_data_reg[0]_1 ); + mm2s_prmry_reset_out_n); output axi_str_txd_tvalid; output [31:0]axi_str_txd_tdata; output axi_str_txd_tlast; output prog_full_axis; - output [0:0]wr_data_count_axis; + output [10:0]wr_data_count_axis; output prog_empty_axis; output s_aresetn; - output \gen_wr_a.gen_word_narrow.mem_reg ; output sig_txd_wr_en; - output \gwdc.wr_data_count_i_reg[9] ; - output [7:0]D; + output \gwdc.wr_data_count_i_reg[12] ; + output [0:0]S; + output [3:0]DI; + output [3:0]\gwdc.wr_data_count_i_reg[7] ; + output [2:0]\gwdc.wr_data_count_i_reg[3] ; + output [0:0]\gwdc.wr_data_count_i_reg[0] ; output \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ; output \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg ; output IP2Bus_Error_reg; - output [0:0]E; input s_axi_aclk; input [31:0]Q; - input \gen_wr_a.gen_word_narrow.mem_reg_0 ; + input \gen_wr_a.gen_word_narrow.mem_reg_5 ; input axi_str_txd_tready; input start_wr; input txd_wr_en; - input \sig_register_array_reg[0][4] ; - input \sig_register_array_reg[0][4]_0 ; - input [0:0]s_axi_wdata; input IP2Bus_Error_reg_0; input sig_txd_prog_full_d1; input sig_txd_prog_empty_d1; - input [1:0]\gen_wr_a.gen_word_narrow.mem_reg_1 ; + input [1:0]\gen_wr_a.gen_word_narrow.mem_reg_3 ; input [0:0]p_1_in; input s_axi_aresetn; input IP2Bus_Error_reg_1; input Axi_Str_RxD_AReset; input mm2s_prmry_reset_out_n; - input \sig_txd_wr_data_reg[0] ; - input \sig_txd_wr_data_reg[0]_0 ; - input \sig_txd_wr_data_reg[0]_1 ; wire Axi_Str_RxD_AReset; wire COMP_FIFO_i_2_n_0; @@ -1662,23 +1619,24 @@ module design_1_axi_fifo_mm_s_0_0_axis_fg wire COMP_FIFO_n_52; wire COMP_FIFO_n_53; wire COMP_FIFO_n_54; - wire [7:0]D; - wire [0:0]E; + wire [3:0]DI; wire IP2Bus_Error_reg; wire IP2Bus_Error_reg_0; wire IP2Bus_Error_reg_1; wire [31:0]Q; + wire [0:0]S; wire [31:0]axi_str_txd_tdata; wire axi_str_txd_tlast; wire axi_str_txd_tready; wire axi_str_txd_tvalid; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ; - wire \gen_wr_a.gen_word_narrow.mem_reg ; - wire \gen_wr_a.gen_word_narrow.mem_reg_0 ; - wire [1:0]\gen_wr_a.gen_word_narrow.mem_reg_1 ; - wire \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 ; - wire \gwdc.wr_data_count_i_reg[9] ; + wire [1:0]\gen_wr_a.gen_word_narrow.mem_reg_3 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_5 ; + wire [0:0]\gwdc.wr_data_count_i_reg[0] ; + wire \gwdc.wr_data_count_i_reg[12] ; + wire [2:0]\gwdc.wr_data_count_i_reg[3] ; + wire [3:0]\gwdc.wr_data_count_i_reg[7] ; wire [2:1]input_tstrb; wire input_tvalid; wire mm2s_prmry_reset_out_n; @@ -1688,25 +1646,21 @@ module design_1_axi_fifo_mm_s_0_0_axis_fg wire s_aresetn; wire s_axi_aclk; wire s_axi_aresetn; - wire [0:0]s_axi_wdata; wire s_axis_tready_i; - wire \sig_register_array_reg[0][4] ; - wire \sig_register_array_reg[0][4]_0 ; - wire [9:0]sig_txd_occupancy; + wire \sig_register_array[0][3]_i_4_n_0 ; + wire \sig_register_array[0][3]_i_5_n_0 ; + wire [12:0]sig_txd_occupancy; wire sig_txd_prog_empty_d1; wire sig_txd_prog_full_d1; - wire \sig_txd_wr_data_reg[0] ; - wire \sig_txd_wr_data_reg[0]_0 ; - wire \sig_txd_wr_data_reg[0]_1 ; wire sig_txd_wr_en; wire start_wr; wire txd_wr_en; - wire [0:0]wr_data_count_axis; + wire [10:0]wr_data_count_axis; wire NLW_COMP_FIFO_almost_empty_axis_UNCONNECTED; wire NLW_COMP_FIFO_almost_full_axis_UNCONNECTED; wire NLW_COMP_FIFO_dbiterr_axis_UNCONNECTED; wire NLW_COMP_FIFO_sbiterr_axis_UNCONNECTED; - wire [9:0]NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED; + wire [12:0]NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED; (* AXIS_DATA_WIDTH = "53" *) (* AXIS_FINAL_DATA_WIDTH = "53" *) @@ -1719,18 +1673,18 @@ module design_1_axi_fifo_mm_s_0_0_axis_fg (* EN_ALMOST_EMPTY_INT = "1'b1" *) (* EN_ALMOST_FULL_INT = "1'b1" *) (* EN_DATA_VALID_INT = "1'b1" *) - (* FIFO_DEPTH = "512" *) + (* FIFO_DEPTH = "4096" *) (* FIFO_MEMORY_TYPE = "BRAM" *) - (* LOG_DEPTH_AXIS = "9" *) + (* LOG_DEPTH_AXIS = "12" *) (* PACKET_FIFO = "true" *) (* PKT_SIZE_LT8 = "1'b0" *) (* PROG_EMPTY_THRESH = "5" *) - (* PROG_FULL_THRESH = "507" *) + (* PROG_FULL_THRESH = "4091" *) (* P_COMMON_CLOCK = "1" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_PKT_MODE = "1" *) - (* RD_DATA_COUNT_WIDTH = "10" *) + (* RD_DATA_COUNT_WIDTH = "13" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* TDATA_OFFSET = "32" *) @@ -1746,7 +1700,7 @@ module design_1_axi_fifo_mm_s_0_0_axis_fg (* TUSER_WIDTH = "4" *) (* USE_ADV_FEATURES = "1606" *) (* USE_ADV_FEATURES_INT = "826617925" *) - (* WR_DATA_COUNT_WIDTH = "10" *) + (* WR_DATA_COUNT_WIDTH = "13" *) (* XPM_MODULE = "TRUE" *) design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis COMP_FIFO (.almost_empty_axis(NLW_COMP_FIFO_almost_empty_axis_UNCONNECTED), @@ -1766,135 +1720,123 @@ module design_1_axi_fifo_mm_s_0_0_axis_fg .m_axis_tvalid(axi_str_txd_tvalid), .prog_empty_axis(prog_empty_axis), .prog_full_axis(prog_full_axis), - .rd_data_count_axis(NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED[9:0]), + .rd_data_count_axis(NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED[12:0]), .s_aclk(s_axi_aclk), .s_aresetn(s_aresetn), .s_axis_tdata(Q), .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}), .s_axis_tid({1'b0,1'b0,1'b0,1'b0}), .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}), - .s_axis_tlast(\gen_wr_a.gen_word_narrow.mem_reg_0 ), + .s_axis_tlast(\gen_wr_a.gen_word_narrow.mem_reg_5 ), .s_axis_tready(s_axis_tready_i), .s_axis_tstrb({COMP_FIFO_i_2_n_0,input_tstrb,1'b1}), .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), .s_axis_tvalid(input_tvalid), .sbiterr_axis(NLW_COMP_FIFO_sbiterr_axis_UNCONNECTED), - .wr_data_count_axis({sig_txd_occupancy[9:2],wr_data_count_axis,sig_txd_occupancy[0]})); + .wr_data_count_axis({sig_txd_occupancy[12],wr_data_count_axis,sig_txd_occupancy[0]})); LUT3 #( .INIT(8'hA8)) COMP_FIFO_i_1 (.I0(start_wr), .I1(txd_wr_en), - .I2(\gen_wr_a.gen_word_narrow.mem_reg_0 ), + .I2(\gen_wr_a.gen_word_narrow.mem_reg_5 ), .O(input_tvalid)); LUT3 #( .INIT(8'h1F)) COMP_FIFO_i_2 - (.I0(\gen_wr_a.gen_word_narrow.mem_reg_1 [0]), - .I1(\gen_wr_a.gen_word_narrow.mem_reg_1 [1]), - .I2(\gen_wr_a.gen_word_narrow.mem_reg_0 ), + (.I0(\gen_wr_a.gen_word_narrow.mem_reg_3 [0]), + .I1(\gen_wr_a.gen_word_narrow.mem_reg_3 [1]), + .I2(\gen_wr_a.gen_word_narrow.mem_reg_5 ), .O(COMP_FIFO_i_2_n_0)); LUT3 #( .INIT(8'h9F)) COMP_FIFO_i_3 - (.I0(\gen_wr_a.gen_word_narrow.mem_reg_1 [0]), - .I1(\gen_wr_a.gen_word_narrow.mem_reg_1 [1]), - .I2(\gen_wr_a.gen_word_narrow.mem_reg_0 ), + (.I0(\gen_wr_a.gen_word_narrow.mem_reg_3 [0]), + .I1(\gen_wr_a.gen_word_narrow.mem_reg_3 [1]), + .I2(\gen_wr_a.gen_word_narrow.mem_reg_5 ), .O(input_tstrb[2])); LUT3 #( .INIT(8'hDF)) COMP_FIFO_i_4 - (.I0(\gen_wr_a.gen_word_narrow.mem_reg_1 [0]), - .I1(\gen_wr_a.gen_word_narrow.mem_reg_1 [1]), - .I2(\gen_wr_a.gen_word_narrow.mem_reg_0 ), + (.I0(\gen_wr_a.gen_word_narrow.mem_reg_3 [0]), + .I1(\gen_wr_a.gen_word_narrow.mem_reg_3 [1]), + .I2(\gen_wr_a.gen_word_narrow.mem_reg_5 ), .O(input_tstrb[1])); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( - .INIT(32'h00AA03AA)) + .INIT(32'h00AA30AA)) IP2Bus_Error_i_1 (.I0(p_1_in), .I1(IP2Bus_Error_reg_0), - .I2(\gwdc.wr_data_count_i_reg[9] ), + .I2(\gwdc.wr_data_count_i_reg[12] ), .I3(s_axi_aresetn), .I4(IP2Bus_Error_reg_1), .O(IP2Bus_Error_reg)); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT2 #( - .INIT(4'h9)) - \gfifo_gen.gmm2s.vacancy_i[2]_i_1 - (.I0(wr_data_count_axis), - .I1(sig_txd_occupancy[2]), - .O(D[0])); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT3 #( - .INIT(8'h95)) - \gfifo_gen.gmm2s.vacancy_i[3]_i_1 - (.I0(sig_txd_occupancy[3]), - .I1(wr_data_count_axis), - .I2(sig_txd_occupancy[2]), - .O(D[1])); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT4 #( - .INIT(16'h9555)) - \gfifo_gen.gmm2s.vacancy_i[4]_i_1 - (.I0(sig_txd_occupancy[4]), - .I1(sig_txd_occupancy[3]), - .I2(sig_txd_occupancy[2]), - .I3(wr_data_count_axis), - .O(D[2])); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT2 #( - .INIT(4'h9)) - \gfifo_gen.gmm2s.vacancy_i[5]_i_1 - (.I0(\gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 ), - .I1(sig_txd_occupancy[5]), - .O(D[3])); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT3 #( - .INIT(8'h87)) - \gfifo_gen.gmm2s.vacancy_i[6]_i_1 - (.I0(sig_txd_occupancy[5]), - .I1(\gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 ), - .I2(sig_txd_occupancy[6]), - .O(D[4])); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT4 #( - .INIT(16'h870F)) - \gfifo_gen.gmm2s.vacancy_i[7]_i_1 - (.I0(sig_txd_occupancy[5]), - .I1(\gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 ), - .I2(sig_txd_occupancy[7]), - .I3(sig_txd_occupancy[6]), - .O(D[5])); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT5 #( - .INIT(32'h870F0F0F)) - \gfifo_gen.gmm2s.vacancy_i[8]_i_1 - (.I0(sig_txd_occupancy[5]), - .I1(\gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 ), - .I2(sig_txd_occupancy[8]), - .I3(sig_txd_occupancy[6]), - .I4(sig_txd_occupancy[7]), - .O(D[6])); - LUT6 #( - .INIT(64'h78F0F0F0F0F0F0F0)) - \gfifo_gen.gmm2s.vacancy_i[9]_i_2 - (.I0(sig_txd_occupancy[5]), - .I1(\gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 ), - .I2(sig_txd_occupancy[9]), - .I3(sig_txd_occupancy[8]), - .I4(sig_txd_occupancy[7]), - .I5(sig_txd_occupancy[6]), - .O(D[7])); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT4 #( - .INIT(16'h8000)) - \gfifo_gen.gmm2s.vacancy_i[9]_i_3 - (.I0(sig_txd_occupancy[4]), - .I1(sig_txd_occupancy[3]), - .I2(sig_txd_occupancy[2]), - .I3(wr_data_count_axis), - .O(\gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__0_i_1 + (.I0(wr_data_count_axis[6]), + .O(\gwdc.wr_data_count_i_reg[7] [3])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__0_i_2 + (.I0(wr_data_count_axis[5]), + .O(\gwdc.wr_data_count_i_reg[7] [2])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__0_i_3 + (.I0(wr_data_count_axis[4]), + .O(\gwdc.wr_data_count_i_reg[7] [1])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__0_i_4 + (.I0(wr_data_count_axis[3]), + .O(\gwdc.wr_data_count_i_reg[7] [0])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__1_i_1 + (.I0(wr_data_count_axis[10]), + .O(DI[3])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__1_i_2 + (.I0(wr_data_count_axis[9]), + .O(DI[2])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__1_i_3 + (.I0(wr_data_count_axis[8]), + .O(DI[1])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__1_i_4 + (.I0(wr_data_count_axis[7]), + .O(DI[0])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry__2_i_1 + (.I0(sig_txd_occupancy[12]), + .O(S)); + LUT1 #( + .INIT(2'h1)) + minusOp_carry_i_1 + (.I0(wr_data_count_axis[2]), + .O(\gwdc.wr_data_count_i_reg[3] [2])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry_i_2 + (.I0(wr_data_count_axis[1]), + .O(\gwdc.wr_data_count_i_reg[3] [1])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry_i_3 + (.I0(wr_data_count_axis[0]), + .O(\gwdc.wr_data_count_i_reg[3] [0])); + LUT1 #( + .INIT(2'h1)) + minusOp_carry_i_4 + (.I0(sig_txd_occupancy[0]), + .O(\gwdc.wr_data_count_i_reg[0] )); LUT3 #( .INIT(8'h04)) mm2s_prmry_reset_out_n_INST_0 @@ -1909,45 +1851,42 @@ module design_1_axi_fifo_mm_s_0_0_axis_fg .I1(sig_txd_prog_empty_d1), .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg )); LUT6 #( - .INIT(64'h1555555555555555)) + .INIT(64'hABAAAAAAAAAAAAAA)) \sig_register_array[0][3]_i_3 - (.I0(sig_txd_occupancy[9]), - .I1(sig_txd_occupancy[6]), - .I2(sig_txd_occupancy[5]), - .I3(sig_txd_occupancy[8]), - .I4(sig_txd_occupancy[7]), - .I5(\gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0 ), - .O(\gwdc.wr_data_count_i_reg[9] )); - LUT5 #( - .INIT(32'hF8FFF8F8)) - \sig_register_array[0][4]_i_3 - (.I0(axi_str_txd_tvalid), - .I1(axi_str_txd_tlast), - .I2(\sig_register_array_reg[0][4] ), - .I3(\sig_register_array_reg[0][4]_0 ), - .I4(s_axi_wdata), - .O(\gen_wr_a.gen_word_narrow.mem_reg )); + (.I0(sig_txd_occupancy[12]), + .I1(\sig_register_array[0][3]_i_4_n_0 ), + .I2(\sig_register_array[0][3]_i_5_n_0 ), + .I3(wr_data_count_axis[8]), + .I4(wr_data_count_axis[7]), + .I5(wr_data_count_axis[3]), + .O(\gwdc.wr_data_count_i_reg[12] )); + LUT4 #( + .INIT(16'h7FFF)) + \sig_register_array[0][3]_i_4 + (.I0(wr_data_count_axis[1]), + .I1(wr_data_count_axis[4]), + .I2(wr_data_count_axis[6]), + .I3(wr_data_count_axis[10]), + .O(\sig_register_array[0][3]_i_4_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \sig_register_array[0][3]_i_5 + (.I0(wr_data_count_axis[0]), + .I1(wr_data_count_axis[2]), + .I2(wr_data_count_axis[5]), + .I3(wr_data_count_axis[9]), + .O(\sig_register_array[0][3]_i_5_n_0 )); LUT2 #( .INIT(4'h2)) \sig_register_array[0][9]_i_2 (.I0(prog_full_axis), .I1(sig_txd_prog_full_d1), .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg )); - LUT6 #( - .INIT(64'h000000002222F222)) - \sig_txd_wr_data[31]_i_1 - (.I0(\gwdc.wr_data_count_i_reg[9] ), - .I1(IP2Bus_Error_reg_0), - .I2(\sig_txd_wr_data_reg[0] ), - .I3(\sig_txd_wr_data_reg[0]_0 ), - .I4(\sig_txd_wr_data_reg[0]_1 ), - .I5(IP2Bus_Error_reg_1), - .O(E)); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair6" *) LUT2 #( - .INIT(4'h2)) + .INIT(4'h1)) sig_txd_wr_en_i_1 - (.I0(\gwdc.wr_data_count_i_reg[9] ), + (.I0(\gwdc.wr_data_count_i_reg[12] ), .I1(IP2Bus_Error_reg_0), .O(sig_txd_wr_en)); endmodule @@ -1960,22 +1899,17 @@ module design_1_axi_fifo_mm_s_0_0_fifo prog_full_axis, prog_empty_axis, s_aresetn, - \gen_wr_a.gen_word_narrow.mem_reg , D, sig_txd_wr_en, - \gwdc.wr_data_count_i_reg[9] , + \gwdc.wr_data_count_i_reg[12] , \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg , \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg , IP2Bus_Error_reg, - E, s_axi_aclk, - \gen_wr_a.gen_word_narrow.mem_reg_0 , + \gen_wr_a.gen_word_narrow.mem_reg_5 , axi_str_txd_tready, txd_wr_en, - \sig_register_array_reg[0][4] , - \sig_register_array_reg[0][4]_0 , - s_axi_wdata, - \sig_ip2bus_data_reg[22] , + \sig_ip2bus_data_reg[19] , IP2Bus_Error_reg_0, sig_txd_prog_full_d1, sig_txd_prog_empty_d1, @@ -1984,32 +1918,24 @@ module design_1_axi_fifo_mm_s_0_0_fifo s_axi_aresetn, IP2Bus_Error_reg_1, Axi_Str_RxD_AReset, - mm2s_prmry_reset_out_n, - \sig_txd_wr_data_reg[0] , - \sig_txd_wr_data_reg[0]_0 , - \sig_txd_wr_data_reg[0]_1 ); + mm2s_prmry_reset_out_n); output axi_str_txd_tvalid; output [31:0]axi_str_txd_tdata; output axi_str_txd_tlast; output prog_full_axis; output prog_empty_axis; output s_aresetn; - output \gen_wr_a.gen_word_narrow.mem_reg ; - output [8:0]D; + output [11:0]D; output sig_txd_wr_en; - output \gwdc.wr_data_count_i_reg[9] ; + output \gwdc.wr_data_count_i_reg[12] ; output \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ; output \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg ; output IP2Bus_Error_reg; - output [0:0]E; input s_axi_aclk; - input \gen_wr_a.gen_word_narrow.mem_reg_0 ; + input \gen_wr_a.gen_word_narrow.mem_reg_5 ; input axi_str_txd_tready; input txd_wr_en; - input \sig_register_array_reg[0][4] ; - input \sig_register_array_reg[0][4]_0 ; - input [0:0]s_axi_wdata; - input \sig_ip2bus_data_reg[22] ; + input \sig_ip2bus_data_reg[19] ; input IP2Bus_Error_reg_0; input sig_txd_prog_full_d1; input sig_txd_prog_empty_d1; @@ -2019,13 +1945,9 @@ module design_1_axi_fifo_mm_s_0_0_fifo input IP2Bus_Error_reg_1; input Axi_Str_RxD_AReset; input mm2s_prmry_reset_out_n; - input \sig_txd_wr_data_reg[0] ; - input \sig_txd_wr_data_reg[0]_0 ; - input \sig_txd_wr_data_reg[0]_1 ; wire Axi_Str_RxD_AReset; - wire [8:0]D; - wire [0:0]E; + wire [11:0]D; wire IP2Bus_Error_reg; wire IP2Bus_Error_reg_0; wire IP2Bus_Error_reg_1; @@ -2034,15 +1956,38 @@ module design_1_axi_fifo_mm_s_0_0_fifo wire axi_str_txd_tlast; wire axi_str_txd_tready; wire axi_str_txd_tvalid; - wire [9:1]data2; + wire [12:1]data2; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ; - wire \gen_wr_a.gen_word_narrow.mem_reg ; - wire \gen_wr_a.gen_word_narrow.mem_reg_0 ; - wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_42 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_5 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_50 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_51 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_52 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_53 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_54 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_55 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_56 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_57 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_58 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_59 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_60 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_61 ; + wire \gfifo_gen.COMP_AXIS_FG_FIFO_n_62 ; wire \gfifo_gen.gmm2s.start_wr_i_1_n_0 ; - wire \gwdc.wr_data_count_i_reg[9] ; - wire [9:2]minusOp; + wire \gwdc.wr_data_count_i_reg[12] ; + wire [12:1]minusOp; + wire minusOp_carry__0_n_0; + wire minusOp_carry__0_n_1; + wire minusOp_carry__0_n_2; + wire minusOp_carry__0_n_3; + wire minusOp_carry__1_n_0; + wire minusOp_carry__1_n_1; + wire minusOp_carry__1_n_2; + wire minusOp_carry__1_n_3; + wire minusOp_carry_n_0; + wire minusOp_carry_n_1; + wire minusOp_carry_n_2; + wire minusOp_carry_n_3; wire mm2s_prmry_reset_out_n; wire [0:0]p_1_in; wire prog_empty_axis; @@ -2050,40 +1995,39 @@ module design_1_axi_fifo_mm_s_0_0_fifo wire s_aresetn; wire s_axi_aclk; wire s_axi_aresetn; - wire [0:0]s_axi_wdata; - wire \sig_ip2bus_data_reg[22] ; - wire \sig_register_array_reg[0][4] ; - wire \sig_register_array_reg[0][4]_0 ; - wire [1:1]sig_txd_occupancy; + wire \sig_ip2bus_data_reg[19] ; + wire [11:1]sig_txd_occupancy; wire sig_txd_prog_empty_d1; wire sig_txd_prog_full_d1; wire sig_txd_reset0_out; - wire \sig_txd_wr_data_reg[0] ; - wire \sig_txd_wr_data_reg[0]_0 ; - wire \sig_txd_wr_data_reg[0]_1 ; wire sig_txd_wr_en; wire start_wr; wire txd_wr_en; wire [31:0]wr_data_int; + wire [0:0]NLW_minusOp_carry_O_UNCONNECTED; + wire [3:0]NLW_minusOp_carry__2_CO_UNCONNECTED; + wire [3:1]NLW_minusOp_carry__2_O_UNCONNECTED; design_1_axi_fifo_mm_s_0_0_axis_fg \gfifo_gen.COMP_AXIS_FG_FIFO (.Axi_Str_RxD_AReset(Axi_Str_RxD_AReset), - .D({minusOp[9],\gfifo_gen.COMP_AXIS_FG_FIFO_n_42 ,minusOp[7:2]}), - .E(E), + .DI({\gfifo_gen.COMP_AXIS_FG_FIFO_n_51 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_52 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_53 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_54 }), .IP2Bus_Error_reg(IP2Bus_Error_reg), .IP2Bus_Error_reg_0(IP2Bus_Error_reg_0), .IP2Bus_Error_reg_1(IP2Bus_Error_reg_1), .Q(wr_data_int), + .S(\gfifo_gen.COMP_AXIS_FG_FIFO_n_50 ), .axi_str_txd_tdata(axi_str_txd_tdata), .axi_str_txd_tlast(axi_str_txd_tlast), .axi_str_txd_tready(axi_str_txd_tready), .axi_str_txd_tvalid(axi_str_txd_tvalid), .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg (\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg ), .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg (\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ), - .\gen_wr_a.gen_word_narrow.mem_reg (\gen_wr_a.gen_word_narrow.mem_reg ), - .\gen_wr_a.gen_word_narrow.mem_reg_0 (\gen_wr_a.gen_word_narrow.mem_reg_0 ), - .\gen_wr_a.gen_word_narrow.mem_reg_1 (Q[1:0]), - .\gwdc.wr_data_count_i_reg[9] (\gwdc.wr_data_count_i_reg[9] ), + .\gen_wr_a.gen_word_narrow.mem_reg_3 (Q[1:0]), + .\gen_wr_a.gen_word_narrow.mem_reg_5 (\gen_wr_a.gen_word_narrow.mem_reg_5 ), + .\gwdc.wr_data_count_i_reg[0] (\gfifo_gen.COMP_AXIS_FG_FIFO_n_62 ), + .\gwdc.wr_data_count_i_reg[12] (\gwdc.wr_data_count_i_reg[12] ), + .\gwdc.wr_data_count_i_reg[3] ({\gfifo_gen.COMP_AXIS_FG_FIFO_n_59 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_60 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_61 }), + .\gwdc.wr_data_count_i_reg[7] ({\gfifo_gen.COMP_AXIS_FG_FIFO_n_55 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_56 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_57 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_58 }), .mm2s_prmry_reset_out_n(mm2s_prmry_reset_out_n), .p_1_in(p_1_in), .prog_empty_axis(prog_empty_axis), @@ -2091,14 +2035,8 @@ module design_1_axi_fifo_mm_s_0_0_fifo .s_aresetn(s_aresetn), .s_axi_aclk(s_axi_aclk), .s_axi_aresetn(s_axi_aresetn), - .s_axi_wdata(s_axi_wdata), - .\sig_register_array_reg[0][4] (\sig_register_array_reg[0][4] ), - .\sig_register_array_reg[0][4]_0 (\sig_register_array_reg[0][4]_0 ), .sig_txd_prog_empty_d1(sig_txd_prog_empty_d1), .sig_txd_prog_full_d1(sig_txd_prog_full_d1), - .\sig_txd_wr_data_reg[0] (\sig_txd_wr_data_reg[0] ), - .\sig_txd_wr_data_reg[0]_0 (\sig_txd_wr_data_reg[0]_0 ), - .\sig_txd_wr_data_reg[0]_1 (\sig_txd_wr_data_reg[0]_1 ), .sig_txd_wr_en(sig_txd_wr_en), .start_wr(start_wr), .txd_wr_en(txd_wr_en), @@ -2107,7 +2045,7 @@ module design_1_axi_fifo_mm_s_0_0_fifo .INIT(8'hBA)) \gfifo_gen.gmm2s.start_wr_i_1 (.I0(txd_wr_en), - .I1(\gen_wr_a.gen_word_narrow.mem_reg_0 ), + .I1(\gen_wr_a.gen_word_narrow.mem_reg_5 ), .I2(start_wr), .O(\gfifo_gen.gmm2s.start_wr_i_1_n_0 )); FDRE #( @@ -2120,15 +2058,39 @@ module design_1_axi_fifo_mm_s_0_0_fifo .R(sig_txd_reset0_out)); LUT1 #( .INIT(2'h1)) - \gfifo_gen.gmm2s.vacancy_i[9]_i_1 + \gfifo_gen.gmm2s.vacancy_i[12]_i_1 (.I0(s_aresetn), .O(sig_txd_reset0_out)); + FDRE #( + .INIT(1'b0)) + \gfifo_gen.gmm2s.vacancy_i_reg[10] + (.C(s_axi_aclk), + .CE(1'b1), + .D(minusOp[10]), + .Q(data2[10]), + .R(sig_txd_reset0_out)); + FDRE #( + .INIT(1'b0)) + \gfifo_gen.gmm2s.vacancy_i_reg[11] + (.C(s_axi_aclk), + .CE(1'b1), + .D(minusOp[11]), + .Q(data2[11]), + .R(sig_txd_reset0_out)); + FDRE #( + .INIT(1'b0)) + \gfifo_gen.gmm2s.vacancy_i_reg[12] + (.C(s_axi_aclk), + .CE(1'b1), + .D(minusOp[12]), + .Q(data2[12]), + .R(sig_txd_reset0_out)); FDRE #( .INIT(1'b0)) \gfifo_gen.gmm2s.vacancy_i_reg[1] (.C(s_axi_aclk), .CE(1'b1), - .D(sig_txd_occupancy), + .D(minusOp[1]), .Q(data2[1]), .R(sig_txd_reset0_out)); FDRE #( @@ -2184,7 +2146,7 @@ module design_1_axi_fifo_mm_s_0_0_fifo \gfifo_gen.gmm2s.vacancy_i_reg[8] (.C(s_axi_aclk), .CE(1'b1), - .D(\gfifo_gen.COMP_AXIS_FG_FIFO_n_42 ), + .D(minusOp[8]), .Q(data2[8]), .R(sig_txd_reset0_out)); FDRE #( @@ -2451,67 +2413,121 @@ module design_1_axi_fifo_mm_s_0_0_fifo .D(Q[9]), .Q(wr_data_int[9]), .R(sig_txd_reset0_out)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 minusOp_carry + (.CI(1'b0), + .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}), + .CYINIT(1'b0), + .DI({\gfifo_gen.COMP_AXIS_FG_FIFO_n_59 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_60 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_61 ,1'b0}), + .O({minusOp[3:1],NLW_minusOp_carry_O_UNCONNECTED[0]}), + .S({sig_txd_occupancy[3:1],\gfifo_gen.COMP_AXIS_FG_FIFO_n_62 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 minusOp_carry__0 + (.CI(minusOp_carry_n_0), + .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({\gfifo_gen.COMP_AXIS_FG_FIFO_n_55 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_56 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_57 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_58 }), + .O(minusOp[7:4]), + .S(sig_txd_occupancy[7:4])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 minusOp_carry__1 + (.CI(minusOp_carry__0_n_0), + .CO({minusOp_carry__1_n_0,minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({\gfifo_gen.COMP_AXIS_FG_FIFO_n_51 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_52 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_53 ,\gfifo_gen.COMP_AXIS_FG_FIFO_n_54 }), + .O(minusOp[11:8]), + .S(sig_txd_occupancy[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 minusOp_carry__2 + (.CI(minusOp_carry__1_n_0), + .CO(NLW_minusOp_carry__2_CO_UNCONNECTED[3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({NLW_minusOp_carry__2_O_UNCONNECTED[3:1],minusOp[12]}), + .S({1'b0,1'b0,1'b0,\gfifo_gen.COMP_AXIS_FG_FIFO_n_50 })); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h2)) + \sig_ip2bus_data[19]_i_1 + (.I0(data2[12]), + .I1(\sig_ip2bus_data_reg[19] ), + .O(D[11])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h2)) + \sig_ip2bus_data[20]_i_1 + (.I0(data2[11]), + .I1(\sig_ip2bus_data_reg[19] ), + .O(D[10])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h2)) + \sig_ip2bus_data[21]_i_1 + (.I0(data2[10]), + .I1(\sig_ip2bus_data_reg[19] ), + .O(D[9])); + (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[22]_i_1 (.I0(data2[9]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[8])); - (* SOFT_HLUTNM = "soft_lutpair34" *) + (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[23]_i_1 (.I0(data2[8]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[7])); - (* SOFT_HLUTNM = "soft_lutpair34" *) + (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[24]_i_1 (.I0(data2[7]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[6])); - (* SOFT_HLUTNM = "soft_lutpair33" *) + (* SOFT_HLUTNM = "soft_lutpair9" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[25]_i_1 (.I0(data2[6]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[5])); - (* SOFT_HLUTNM = "soft_lutpair33" *) + (* SOFT_HLUTNM = "soft_lutpair9" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[26]_i_1 (.I0(data2[5]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[4])); - (* SOFT_HLUTNM = "soft_lutpair32" *) + (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[27]_i_1 (.I0(data2[4]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[3])); - (* SOFT_HLUTNM = "soft_lutpair32" *) + (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[28]_i_1 (.I0(data2[3]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[2])); - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair7" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[29]_i_1 (.I0(data2[2]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[1])); - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair7" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[30]_i_1 (.I0(data2[1]), - .I1(\sig_ip2bus_data_reg[22] ), + .I1(\sig_ip2bus_data_reg[19] ), .O(D[0])); endmodule @@ -2527,43 +2543,39 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s p_1_in, sig_tx_channel_reset_reg_0, cs_ce_clr, - IPIC_STATE_reg_0, IP2Bus_Error1_in, s2mm_prmry_reset_out_n, s_axi_wdata_7_sp_1, - s_axi_wdata_0_sp_1, interrupt, Q, - \sig_register_array_reg[0][4]_0 , - \sig_register_array_reg[0][3]_0 , - \sig_register_array_reg[0][6]_0 , \sig_register_array_reg[0][10]_0 , + \sig_register_array_reg[0][3]_0 , \sig_register_array_reg[0][7]_0 , - \sig_register_array_reg[0][9]_0 , + \sig_register_array_reg[0][4]_0 , \sig_register_array_reg[0][8]_0 , + \sig_register_array_reg[0][6]_0 , + \sig_register_array_reg[0][9]_0 , \sig_ip2bus_data_reg[0]_0 , s_axi_aclk, axi_str_txd_tready, - sig_txd_sb_wr_en, sig_str_rst_reg_1, IP2Bus_WrAck_reg_1, IP2Bus_RdAck_reg_1, sig_Bus2IP_CS, s_axi_aresetn, + sig_txd_sb_wr_en_reg_0, \sig_register_array_reg[0][3]_1 , s_axi_wdata, - \sig_txd_wr_data_reg[0]_0 , D, + \sig_ip2bus_data_reg[19]_0 , \sig_ip2bus_data_reg[12]_0 , - \sig_ip2bus_data_reg[22]_0 , IP2Bus_Error_reg_0, sig_tx_channel_reset_reg_1, - \sig_txd_wr_data_reg[0]_1 , \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg , \sig_register_array_reg[0][4]_1 , + \sig_register_array_reg[0][4]_2 , \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg , Bus_RNW_reg, - \sig_register_array_reg[0][6]_1 , E, \sig_register_array_reg[1][0]_0 ); output axi_str_txd_tvalid; @@ -2576,43 +2588,39 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s output [0:0]p_1_in; output sig_tx_channel_reset_reg_0; output cs_ce_clr; - output IPIC_STATE_reg_0; output IP2Bus_Error1_in; output s2mm_prmry_reset_out_n; output s_axi_wdata_7_sp_1; - output s_axi_wdata_0_sp_1; output interrupt; output [6:0]Q; - output \sig_register_array_reg[0][4]_0 ; - output \sig_register_array_reg[0][3]_0 ; - output \sig_register_array_reg[0][6]_0 ; output \sig_register_array_reg[0][10]_0 ; + output \sig_register_array_reg[0][3]_0 ; output \sig_register_array_reg[0][7]_0 ; - output \sig_register_array_reg[0][9]_0 ; + output \sig_register_array_reg[0][4]_0 ; output \sig_register_array_reg[0][8]_0 ; - output [21:0]\sig_ip2bus_data_reg[0]_0 ; + output \sig_register_array_reg[0][6]_0 ; + output \sig_register_array_reg[0][9]_0 ; + output [24:0]\sig_ip2bus_data_reg[0]_0 ; input s_axi_aclk; input axi_str_txd_tready; - input sig_txd_sb_wr_en; input sig_str_rst_reg_1; input IP2Bus_WrAck_reg_1; input IP2Bus_RdAck_reg_1; input sig_Bus2IP_CS; input s_axi_aresetn; + input sig_txd_sb_wr_en_reg_0; input \sig_register_array_reg[0][3]_1 ; input [31:0]s_axi_wdata; - input \sig_txd_wr_data_reg[0]_0 ; input [6:0]D; + input \sig_ip2bus_data_reg[19]_0 ; input \sig_ip2bus_data_reg[12]_0 ; - input \sig_ip2bus_data_reg[22]_0 ; input IP2Bus_Error_reg_0; input sig_tx_channel_reset_reg_1; - input \sig_txd_wr_data_reg[0]_1 ; input \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ; input \sig_register_array_reg[0][4]_1 ; + input \sig_register_array_reg[0][4]_2 ; input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ; input Bus_RNW_reg; - input \sig_register_array_reg[0][6]_1 ; input [0:0]E; input [12:0]\sig_register_array_reg[1][0]_0 ; @@ -2630,7 +2638,6 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s wire IP2Bus_WrAck_reg_0; wire IP2Bus_WrAck_reg_1; wire IPIC_STATE; - wire IPIC_STATE_reg_0; wire [6:0]Q; wire [30:1]R; wire R_carry__0_i_1_n_0; @@ -2719,12 +2726,10 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s wire \eqOp_inferred__2/i__carry_n_1 ; wire \eqOp_inferred__2/i__carry_n_2 ; wire \eqOp_inferred__2/i__carry_n_3 ; - wire \gtxd.COMP_TXD_FIFO_n_37 ; - wire \gtxd.COMP_TXD_FIFO_n_48 ; - wire \gtxd.COMP_TXD_FIFO_n_49 ; wire \gtxd.COMP_TXD_FIFO_n_50 ; wire \gtxd.COMP_TXD_FIFO_n_51 ; wire \gtxd.COMP_TXD_FIFO_n_52 ; + wire \gtxd.COMP_TXD_FIFO_n_53 ; wire \gtxd.sig_txd_packet_size[0]_i_1_n_0 ; wire \gtxd.sig_txd_packet_size[0]_i_3_n_0 ; wire [30:0]\gtxd.sig_txd_packet_size_reg ; @@ -2819,18 +2824,18 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s wire s_axi_aclk; wire s_axi_aresetn; wire [31:0]s_axi_wdata; - wire s_axi_wdata_0_sn_1; wire s_axi_wdata_7_sn_1; wire sig_Bus2IP_CS; wire sig_Bus2IP_Reset; wire [0:30]sig_ip2bus_data; - wire [21:0]\sig_ip2bus_data_reg[0]_0 ; + wire [24:0]\sig_ip2bus_data_reg[0]_0 ; wire \sig_ip2bus_data_reg[12]_0 ; - wire \sig_ip2bus_data_reg[22]_0 ; + wire \sig_ip2bus_data_reg[19]_0 ; wire \sig_register_array[0][10]_i_1_n_0 ; wire \sig_register_array[0][3]_i_1_n_0 ; wire \sig_register_array[0][4]_i_1_n_0 ; wire \sig_register_array[0][6]_i_1_n_0 ; + wire \sig_register_array[0][6]_i_2_n_0 ; wire \sig_register_array[0][7]_i_1_n_0 ; wire \sig_register_array[0][8]_i_1_n_0 ; wire \sig_register_array[0][9]_i_1_n_0 ; @@ -2839,8 +2844,8 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s wire \sig_register_array_reg[0][3]_1 ; wire \sig_register_array_reg[0][4]_0 ; wire \sig_register_array_reg[0][4]_1 ; + wire \sig_register_array_reg[0][4]_2 ; wire \sig_register_array_reg[0][6]_0 ; - wire \sig_register_array_reg[0][6]_1 ; wire \sig_register_array_reg[0][7]_0 ; wire \sig_register_array_reg[0][8]_0 ; wire \sig_register_array_reg[0][9]_0 ; @@ -2862,9 +2867,10 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s wire sig_txd_prog_full; wire sig_txd_prog_full_d1; wire sig_txd_sb_wr_en; + wire sig_txd_sb_wr_en_reg_0; wire sig_txd_sb_wr_en_reg_n_0; - wire \sig_txd_wr_data_reg[0]_0 ; - wire \sig_txd_wr_data_reg[0]_1 ; + wire \sig_txd_wr_data[31]_i_1_n_0 ; + wire \sig_txd_wr_data[31]_i_2_n_0 ; wire sig_txd_wr_en; wire [31:2]txd_wr_data; wire [1:0]txd_wr_data_0; @@ -2882,14 +2888,13 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s wire [3:2]\NLW_gtxd.sig_txd_packet_size_reg[28]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_gtxd.sig_txd_packet_size_reg[28]_i_1_O_UNCONNECTED ; - assign s_axi_wdata_0_sp_1 = s_axi_wdata_0_sn_1; assign s_axi_wdata_7_sp_1 = s_axi_wdata_7_sn_1; FDRE #( .INIT(1'b0)) IP2Bus_Error_reg (.C(s_axi_aclk), .CE(1'b1), - .D(\gtxd.COMP_TXD_FIFO_n_51 ), + .D(\gtxd.COMP_TXD_FIFO_n_53 ), .Q(p_1_in), .R(1'b0)); LUT1 #( @@ -3196,9 +3201,8 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .S({1'b0,i__carry__1_i_1_n_0,i__carry__1_i_2__0_n_0,i__carry__1_i_3__0_n_0})); design_1_axi_fifo_mm_s_0_0_fifo \gtxd.COMP_TXD_FIFO (.Axi_Str_RxD_AReset(Axi_Str_RxD_AReset), - .D({sig_ip2bus_data[22],sig_ip2bus_data[23],sig_ip2bus_data[24],sig_ip2bus_data[25],sig_ip2bus_data[26],sig_ip2bus_data[27],sig_ip2bus_data[28],sig_ip2bus_data[29],sig_ip2bus_data[30]}), - .E(\gtxd.COMP_TXD_FIFO_n_52 ), - .IP2Bus_Error_reg(\gtxd.COMP_TXD_FIFO_n_51 ), + .D({sig_ip2bus_data[19],sig_ip2bus_data[20],sig_ip2bus_data[21],sig_ip2bus_data[22],sig_ip2bus_data[23],sig_ip2bus_data[24],sig_ip2bus_data[25],sig_ip2bus_data[26],sig_ip2bus_data[27],sig_ip2bus_data[28],sig_ip2bus_data[29],sig_ip2bus_data[30]}), + .IP2Bus_Error_reg(\gtxd.COMP_TXD_FIFO_n_53 ), .IP2Bus_Error_reg_0(IP2Bus_Error_reg_0), .IP2Bus_Error_reg_1(IP2Bus_Error1_in), .Q({txd_wr_data,txd_wr_data_0}), @@ -3206,11 +3210,10 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .axi_str_txd_tlast(axi_str_txd_tlast), .axi_str_txd_tready(axi_str_txd_tready), .axi_str_txd_tvalid(axi_str_txd_tvalid), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg (\gtxd.COMP_TXD_FIFO_n_50 ), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg (\gtxd.COMP_TXD_FIFO_n_49 ), - .\gen_wr_a.gen_word_narrow.mem_reg (\gtxd.COMP_TXD_FIFO_n_37 ), - .\gen_wr_a.gen_word_narrow.mem_reg_0 (sig_txd_sb_wr_en_reg_n_0), - .\gwdc.wr_data_count_i_reg[9] (\gtxd.COMP_TXD_FIFO_n_48 ), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg (\gtxd.COMP_TXD_FIFO_n_52 ), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg (\gtxd.COMP_TXD_FIFO_n_51 ), + .\gen_wr_a.gen_word_narrow.mem_reg_5 (sig_txd_sb_wr_en_reg_n_0), + .\gwdc.wr_data_count_i_reg[12] (\gtxd.COMP_TXD_FIFO_n_50 ), .mm2s_prmry_reset_out_n(sig_tx_channel_reset_reg_0), .p_1_in(p_1_in), .prog_empty_axis(sig_txd_prog_empty), @@ -3218,15 +3221,9 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .s_aresetn(sig_str_rst_reg_0), .s_axi_aclk(s_axi_aclk), .s_axi_aresetn(s_axi_aresetn), - .s_axi_wdata(s_axi_wdata[27]), - .\sig_ip2bus_data_reg[22] (\sig_ip2bus_data_reg[22]_0 ), - .\sig_register_array_reg[0][4] (sig_str_rst_reg_1), - .\sig_register_array_reg[0][4]_0 (\sig_register_array_reg[0][3]_1 ), + .\sig_ip2bus_data_reg[19] (\sig_ip2bus_data_reg[19]_0 ), .sig_txd_prog_empty_d1(sig_txd_prog_empty_d1), .sig_txd_prog_full_d1(sig_txd_prog_full_d1), - .\sig_txd_wr_data_reg[0] (\sig_txd_wr_data_reg[0]_1 ), - .\sig_txd_wr_data_reg[0]_0 (s_axi_wdata_0_sn_1), - .\sig_txd_wr_data_reg[0]_1 (\sig_txd_wr_data_reg[0]_0 ), .sig_txd_wr_en(sig_txd_wr_en), .txd_wr_en(txd_wr_en)); LUT2 #( @@ -3501,42 +3498,42 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_1 - (.I0(\gtxd.sig_txd_packet_size_reg [22]), - .I1(s_axi_wdata[24]), - .I2(s_axi_wdata[25]), - .I3(\gtxd.sig_txd_packet_size_reg [23]), - .I4(s_axi_wdata[23]), - .I5(\gtxd.sig_txd_packet_size_reg [21]), + (.I0(\gtxd.sig_txd_packet_size_reg [23]), + .I1(s_axi_wdata[25]), + .I2(s_axi_wdata[23]), + .I3(\gtxd.sig_txd_packet_size_reg [21]), + .I4(s_axi_wdata[24]), + .I5(\gtxd.sig_txd_packet_size_reg [22]), .O(i__carry__0_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_1__0 - (.I0(s_axi_wdata[23]), - .I1(R[21]), - .I2(s_axi_wdata[24]), - .I3(R[22]), - .I4(R[23]), - .I5(s_axi_wdata[25]), + (.I0(s_axi_wdata[25]), + .I1(R[23]), + .I2(s_axi_wdata[23]), + .I3(R[21]), + .I4(R[22]), + .I5(s_axi_wdata[24]), .O(i__carry__0_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_2 - (.I0(\gtxd.sig_txd_packet_size_reg [19]), - .I1(s_axi_wdata[21]), - .I2(s_axi_wdata[22]), - .I3(\gtxd.sig_txd_packet_size_reg [20]), - .I4(s_axi_wdata[20]), - .I5(\gtxd.sig_txd_packet_size_reg [18]), + (.I0(\gtxd.sig_txd_packet_size_reg [20]), + .I1(s_axi_wdata[22]), + .I2(s_axi_wdata[20]), + .I3(\gtxd.sig_txd_packet_size_reg [18]), + .I4(s_axi_wdata[21]), + .I5(\gtxd.sig_txd_packet_size_reg [19]), .O(i__carry__0_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_2__0 - (.I0(s_axi_wdata[20]), - .I1(R[18]), - .I2(s_axi_wdata[21]), - .I3(R[19]), - .I4(R[20]), - .I5(s_axi_wdata[22]), + (.I0(s_axi_wdata[22]), + .I1(R[20]), + .I2(s_axi_wdata[20]), + .I3(R[18]), + .I4(R[19]), + .I5(s_axi_wdata[21]), .O(i__carry__0_i_2__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) @@ -3551,32 +3548,32 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_3__0 - (.I0(R[16]), - .I1(s_axi_wdata[18]), - .I2(s_axi_wdata[19]), - .I3(R[17]), - .I4(s_axi_wdata[17]), - .I5(R[15]), + (.I0(s_axi_wdata[18]), + .I1(R[16]), + .I2(s_axi_wdata[17]), + .I3(R[15]), + .I4(R[17]), + .I5(s_axi_wdata[19]), .O(i__carry__0_i_3__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_4 - (.I0(\gtxd.sig_txd_packet_size_reg [14]), - .I1(s_axi_wdata[16]), - .I2(s_axi_wdata[15]), - .I3(\gtxd.sig_txd_packet_size_reg [13]), + (.I0(\gtxd.sig_txd_packet_size_reg [13]), + .I1(s_axi_wdata[15]), + .I2(s_axi_wdata[16]), + .I3(\gtxd.sig_txd_packet_size_reg [14]), .I4(s_axi_wdata[14]), .I5(\gtxd.sig_txd_packet_size_reg [12]), .O(i__carry__0_i_4_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_4__0 - (.I0(s_axi_wdata[16]), - .I1(R[14]), - .I2(s_axi_wdata[14]), - .I3(R[12]), - .I4(R[13]), - .I5(s_axi_wdata[15]), + (.I0(s_axi_wdata[14]), + .I1(R[12]), + .I2(s_axi_wdata[15]), + .I3(R[13]), + .I4(R[14]), + .I5(s_axi_wdata[16]), .O(i__carry__0_i_4__0_n_0)); LUT1 #( .INIT(2'h1)) @@ -3591,22 +3588,22 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s LUT6 #( .INIT(64'h9009000000009009)) i__carry__1_i_2 - (.I0(\gtxd.sig_txd_packet_size_reg [29]), - .I1(s_axi_wdata[31]), - .I2(s_axi_wdata[30]), - .I3(\gtxd.sig_txd_packet_size_reg [28]), + (.I0(\gtxd.sig_txd_packet_size_reg [28]), + .I1(s_axi_wdata[30]), + .I2(s_axi_wdata[31]), + .I3(\gtxd.sig_txd_packet_size_reg [29]), .I4(s_axi_wdata[29]), .I5(\gtxd.sig_txd_packet_size_reg [27]), .O(i__carry__1_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__1_i_2__0 - (.I0(s_axi_wdata[29]), - .I1(R[27]), - .I2(s_axi_wdata[31]), - .I3(R[29]), - .I4(R[28]), - .I5(s_axi_wdata[30]), + (.I0(R[28]), + .I1(s_axi_wdata[30]), + .I2(s_axi_wdata[29]), + .I3(R[27]), + .I4(s_axi_wdata[31]), + .I5(R[29]), .O(i__carry__1_i_2__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) @@ -3631,62 +3628,62 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_1 - (.I0(\gtxd.sig_txd_packet_size_reg [10]), - .I1(s_axi_wdata[12]), - .I2(s_axi_wdata[13]), - .I3(\gtxd.sig_txd_packet_size_reg [11]), + (.I0(\gtxd.sig_txd_packet_size_reg [11]), + .I1(s_axi_wdata[13]), + .I2(s_axi_wdata[12]), + .I3(\gtxd.sig_txd_packet_size_reg [10]), .I4(s_axi_wdata[11]), .I5(\gtxd.sig_txd_packet_size_reg [9]), .O(i__carry_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_1__0 - (.I0(R[10]), - .I1(s_axi_wdata[12]), - .I2(s_axi_wdata[13]), - .I3(R[11]), - .I4(s_axi_wdata[11]), - .I5(R[9]), + (.I0(s_axi_wdata[13]), + .I1(R[11]), + .I2(s_axi_wdata[11]), + .I3(R[9]), + .I4(R[10]), + .I5(s_axi_wdata[12]), .O(i__carry_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_2 - (.I0(\gtxd.sig_txd_packet_size_reg [8]), - .I1(s_axi_wdata[10]), + (.I0(\gtxd.sig_txd_packet_size_reg [7]), + .I1(s_axi_wdata[9]), .I2(s_axi_wdata[8]), .I3(\gtxd.sig_txd_packet_size_reg [6]), - .I4(s_axi_wdata[9]), - .I5(\gtxd.sig_txd_packet_size_reg [7]), + .I4(s_axi_wdata[10]), + .I5(\gtxd.sig_txd_packet_size_reg [8]), .O(i__carry_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_2__0 - (.I0(R[8]), - .I1(s_axi_wdata[10]), + (.I0(s_axi_wdata[9]), + .I1(R[7]), .I2(s_axi_wdata[8]), .I3(R[6]), - .I4(s_axi_wdata[9]), - .I5(R[7]), + .I4(R[8]), + .I5(s_axi_wdata[10]), .O(i__carry_i_2__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_3 - (.I0(\gtxd.sig_txd_packet_size_reg [4]), - .I1(s_axi_wdata[6]), - .I2(s_axi_wdata[7]), - .I3(\gtxd.sig_txd_packet_size_reg [5]), + (.I0(\gtxd.sig_txd_packet_size_reg [5]), + .I1(s_axi_wdata[7]), + .I2(s_axi_wdata[6]), + .I3(\gtxd.sig_txd_packet_size_reg [4]), .I4(s_axi_wdata[5]), .I5(\gtxd.sig_txd_packet_size_reg [3]), .O(i__carry_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_3__0 - (.I0(s_axi_wdata[6]), - .I1(R[4]), + (.I0(s_axi_wdata[7]), + .I1(R[5]), .I2(s_axi_wdata[5]), .I3(R[3]), - .I4(R[5]), - .I5(s_axi_wdata[7]), + .I4(R[4]), + .I5(s_axi_wdata[6]), .O(i__carry_i_3__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) @@ -3713,70 +3710,70 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s interrupt_INST_0 (.I0(interrupt_INST_0_i_1_n_0), .I1(interrupt_INST_0_i_2_n_0), - .I2(Q[5]), - .I3(\sig_register_array_reg[0][4]_0 ), + .I2(Q[0]), + .I3(\sig_register_array_reg[0][10]_0 ), .I4(Q[6]), .I5(\sig_register_array_reg[0][3]_0 ), .O(interrupt)); LUT6 #( .INIT(64'hFFFFF888F888F888)) interrupt_INST_0_i_1 - (.I0(Q[3]), - .I1(\sig_register_array_reg[0][7]_0 ), - .I2(\sig_register_array_reg[0][9]_0 ), - .I3(Q[1]), - .I4(\sig_register_array_reg[0][8]_0 ), - .I5(Q[2]), + (.I0(Q[2]), + .I1(\sig_register_array_reg[0][8]_0 ), + .I2(\sig_register_array_reg[0][6]_0 ), + .I3(Q[4]), + .I4(\sig_register_array_reg[0][9]_0 ), + .I5(Q[1]), .O(interrupt_INST_0_i_1_n_0)); LUT4 #( .INIT(16'hF888)) interrupt_INST_0_i_2 - (.I0(Q[4]), - .I1(\sig_register_array_reg[0][6]_0 ), - .I2(Q[0]), - .I3(\sig_register_array_reg[0][10]_0 ), + (.I0(Q[3]), + .I1(\sig_register_array_reg[0][7]_0 ), + .I2(Q[5]), + .I3(\sig_register_array_reg[0][4]_0 ), .O(interrupt_INST_0_i_2_n_0)); LUT1 #( .INIT(2'h1)) s2mm_prmry_reset_out_n_INST_0 (.I0(Axi_Str_RxD_AReset), .O(s2mm_prmry_reset_out_n)); - (* SOFT_HLUTNM = "soft_lutpair37" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[0]_i_1 (.I0(\sig_register_array_reg_n_0_[1][0] ), .I1(\sig_ip2bus_data_reg[12]_0 ), .O(sig_ip2bus_data[0])); - (* SOFT_HLUTNM = "soft_lutpair35" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[11]_i_1 (.I0(\sig_register_array_reg_n_0_[1][11] ), .I1(\sig_ip2bus_data_reg[12]_0 ), .O(sig_ip2bus_data[11])); - (* SOFT_HLUTNM = "soft_lutpair35" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[12]_i_1 (.I0(\sig_register_array_reg_n_0_[1][12] ), .I1(\sig_ip2bus_data_reg[12]_0 ), .O(sig_ip2bus_data[12])); - (* SOFT_HLUTNM = "soft_lutpair37" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[1]_i_1 (.I0(\sig_register_array_reg_n_0_[1][1] ), .I1(\sig_ip2bus_data_reg[12]_0 ), .O(sig_ip2bus_data[1])); - (* SOFT_HLUTNM = "soft_lutpair36" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[2]_i_1 (.I0(\sig_register_array_reg_n_0_[1][2] ), .I1(\sig_ip2bus_data_reg[12]_0 ), .O(sig_ip2bus_data[2])); - (* SOFT_HLUTNM = "soft_lutpair36" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h2)) \sig_ip2bus_data[5]_i_1 @@ -3789,7 +3786,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(sig_ip2bus_data[0]), - .Q(\sig_ip2bus_data_reg[0]_0 [21]), + .Q(\sig_ip2bus_data_reg[0]_0 [24]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3797,7 +3794,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(D[0]), - .Q(\sig_ip2bus_data_reg[0]_0 [11]), + .Q(\sig_ip2bus_data_reg[0]_0 [14]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3805,7 +3802,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(sig_ip2bus_data[11]), - .Q(\sig_ip2bus_data_reg[0]_0 [10]), + .Q(\sig_ip2bus_data_reg[0]_0 [13]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3813,7 +3810,15 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(sig_ip2bus_data[12]), - .Q(\sig_ip2bus_data_reg[0]_0 [9]), + .Q(\sig_ip2bus_data_reg[0]_0 [12]), + .R(IP2Bus_WrAck_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + \sig_ip2bus_data_reg[19] + (.C(s_axi_aclk), + .CE(1'b1), + .D(sig_ip2bus_data[19]), + .Q(\sig_ip2bus_data_reg[0]_0 [11]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3821,7 +3826,23 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(sig_ip2bus_data[1]), - .Q(\sig_ip2bus_data_reg[0]_0 [20]), + .Q(\sig_ip2bus_data_reg[0]_0 [23]), + .R(IP2Bus_WrAck_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + \sig_ip2bus_data_reg[20] + (.C(s_axi_aclk), + .CE(1'b1), + .D(sig_ip2bus_data[20]), + .Q(\sig_ip2bus_data_reg[0]_0 [10]), + .R(IP2Bus_WrAck_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + \sig_ip2bus_data_reg[21] + (.C(s_axi_aclk), + .CE(1'b1), + .D(sig_ip2bus_data[21]), + .Q(\sig_ip2bus_data_reg[0]_0 [9]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3893,7 +3914,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(sig_ip2bus_data[2]), - .Q(\sig_ip2bus_data_reg[0]_0 [19]), + .Q(\sig_ip2bus_data_reg[0]_0 [22]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3909,7 +3930,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(D[6]), - .Q(\sig_ip2bus_data_reg[0]_0 [18]), + .Q(\sig_ip2bus_data_reg[0]_0 [21]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3917,7 +3938,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(D[5]), - .Q(\sig_ip2bus_data_reg[0]_0 [17]), + .Q(\sig_ip2bus_data_reg[0]_0 [20]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3925,7 +3946,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(sig_ip2bus_data[5]), - .Q(\sig_ip2bus_data_reg[0]_0 [16]), + .Q(\sig_ip2bus_data_reg[0]_0 [19]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3933,7 +3954,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(D[4]), - .Q(\sig_ip2bus_data_reg[0]_0 [15]), + .Q(\sig_ip2bus_data_reg[0]_0 [18]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3941,7 +3962,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(D[3]), - .Q(\sig_ip2bus_data_reg[0]_0 [14]), + .Q(\sig_ip2bus_data_reg[0]_0 [17]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3949,7 +3970,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(D[2]), - .Q(\sig_ip2bus_data_reg[0]_0 [13]), + .Q(\sig_ip2bus_data_reg[0]_0 [16]), .R(IP2Bus_WrAck_i_1_n_0)); FDRE #( .INIT(1'b0)) @@ -3957,33 +3978,28 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s (.C(s_axi_aclk), .CE(1'b1), .D(D[1]), - .Q(\sig_ip2bus_data_reg[0]_0 [12]), + .Q(\sig_ip2bus_data_reg[0]_0 [15]), .R(IP2Bus_WrAck_i_1_n_0)); LUT6 #( - .INIT(64'h0F004F470C004C44)) + .INIT(64'h3705330337050000)) \sig_register_array[0][10]_i_1 (.I0(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ), - .I1(\gtxd.COMP_TXD_FIFO_n_50 ), - .I2(sig_str_rst_reg_1), + .I1(sig_str_rst_reg_1), + .I2(s_axi_wdata[21]), .I3(\sig_register_array_reg[0][3]_1 ), - .I4(s_axi_wdata[21]), + .I4(\gtxd.COMP_TXD_FIFO_n_52 ), .I5(\sig_register_array_reg[0][10]_0 ), .O(\sig_register_array[0][10]_i_1_n_0 )); - LUT5 #( - .INIT(32'h0D0D000D)) + LUT6 #( + .INIT(64'h3705330337050000)) \sig_register_array[0][3]_i_1 - (.I0(s_axi_wdata[28]), - .I1(\sig_register_array_reg[0][3]_1 ), - .I2(sig_str_rst_reg_1), - .I3(\gtxd.COMP_TXD_FIFO_n_48 ), - .I4(\sig_register_array_reg[0][3]_0 ), + (.I0(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ), + .I1(sig_str_rst_reg_1), + .I2(s_axi_wdata[28]), + .I3(\sig_register_array_reg[0][3]_1 ), + .I4(\gtxd.COMP_TXD_FIFO_n_50 ), + .I5(\sig_register_array_reg[0][3]_0 ), .O(\sig_register_array[0][3]_i_1_n_0 )); - LUT2 #( - .INIT(4'hE)) - \sig_register_array[0][3]_i_4 - (.I0(IP2Bus_Error1_in), - .I1(\sig_txd_wr_data_reg[0]_0 ), - .O(IPIC_STATE_reg_0)); LUT6 #( .INIT(64'h02AAFFFF02AA0000)) \sig_register_array[0][4]_i_1 @@ -3991,19 +4007,30 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .I1(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ), .I2(s_axi_wdata[27]), .I3(\sig_register_array_reg[0][4]_1 ), - .I4(\gtxd.COMP_TXD_FIFO_n_37 ), + .I4(\sig_register_array_reg[0][4]_2 ), .I5(\sig_register_array_reg[0][4]_0 ), .O(\sig_register_array[0][4]_i_1_n_0 )); - LUT4 #( - .INIT(16'h2F20)) + LUT5 #( + .INIT(32'h222F2220)) \sig_register_array[0][6]_i_1 (.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ), .I1(Bus_RNW_reg), - .I2(\sig_register_array_reg[0][6]_1 ), - .I3(\sig_register_array_reg[0][6]_0 ), + .I2(sig_str_rst_reg_1), + .I3(\sig_register_array[0][6]_i_2_n_0 ), + .I4(\sig_register_array_reg[0][6]_0 ), .O(\sig_register_array[0][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) LUT5 #( - .INIT(32'hF0FFD0DD)) + .INIT(32'h10FF1010)) + \sig_register_array[0][6]_i_2 + (.I0(IP2Bus_Error1_in), + .I1(\sig_txd_wr_data[31]_i_2_n_0 ), + .I2(sig_txd_sb_wr_en_reg_0), + .I3(\sig_register_array_reg[0][3]_1 ), + .I4(s_axi_wdata[25]), + .O(\sig_register_array[0][6]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFCFFDCDD)) \sig_register_array[0][7]_i_1 (.I0(sig_str_rst_reg_0), .I1(sig_str_rst_reg_1), @@ -4022,13 +4049,13 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .I5(\sig_register_array_reg[0][8]_0 ), .O(\sig_register_array[0][8]_i_1_n_0 )); LUT6 #( - .INIT(64'h0F004F470C004C44)) + .INIT(64'h3705330337050000)) \sig_register_array[0][9]_i_1 (.I0(\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg ), - .I1(\gtxd.COMP_TXD_FIFO_n_49 ), - .I2(sig_str_rst_reg_1), + .I1(sig_str_rst_reg_1), + .I2(s_axi_wdata[22]), .I3(\sig_register_array_reg[0][3]_1 ), - .I4(s_axi_wdata[22]), + .I4(\gtxd.COMP_TXD_FIFO_n_51 ), .I5(\sig_register_array_reg[0][9]_0 ), .O(\sig_register_array[0][9]_i_1_n_0 )); FDRE \sig_register_array_reg[0][10] @@ -4152,7 +4179,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .Q(Q[1]), .R(sig_Bus2IP_Reset)); LUT5 #( - .INIT(32'h00000008)) + .INIT(32'hFFFFFFF7)) sig_str_rst_i_2 (.I0(s_axi_wdata[7]), .I1(s_axi_wdata[5]), @@ -4191,6 +4218,13 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .D(sig_tx_channel_reset_i_1_n_0), .Q(sig_tx_channel_reset_reg_0), .R(sig_Bus2IP_Reset)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT2 #( + .INIT(4'h8)) + sig_txd_sb_wr_en_i_1 + (.I0(\sig_txd_wr_data[31]_i_2_n_0 ), + .I1(sig_txd_sb_wr_en_reg_0), + .O(sig_txd_sb_wr_en)); FDRE #( .INIT(1'b0)) sig_txd_sb_wr_en_reg @@ -4199,19 +4233,28 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .D(sig_txd_sb_wr_en), .Q(sig_txd_sb_wr_en_reg_n_0), .R(IP2Bus_WrAck_i_1_n_0)); + LUT5 #( + .INIT(32'h0000888F)) + \sig_txd_wr_data[31]_i_1 + (.I0(\sig_txd_wr_data[31]_i_2_n_0 ), + .I1(sig_txd_sb_wr_en_reg_0), + .I2(\gtxd.COMP_TXD_FIFO_n_50 ), + .I3(IP2Bus_Error_reg_0), + .I4(IP2Bus_Error1_in), + .O(\sig_txd_wr_data[31]_i_1_n_0 )); LUT4 #( .INIT(16'hFE02)) - \sig_txd_wr_data[31]_i_3 + \sig_txd_wr_data[31]_i_2 (.I0(eqOp0_out), .I1(s_axi_wdata[0]), .I2(s_axi_wdata[1]), .I3(\eqOp_inferred__2/i__carry__1_n_1 ), - .O(s_axi_wdata_0_sn_1)); + .O(\sig_txd_wr_data[31]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \sig_txd_wr_data_reg[0] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[0]), .Q(txd_wr_data_0[0]), .R(sig_Bus2IP_Reset)); @@ -4219,7 +4262,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[10] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[10]), .Q(txd_wr_data[10]), .R(sig_Bus2IP_Reset)); @@ -4227,7 +4270,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[11] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[11]), .Q(txd_wr_data[11]), .R(sig_Bus2IP_Reset)); @@ -4235,7 +4278,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[12] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[12]), .Q(txd_wr_data[12]), .R(sig_Bus2IP_Reset)); @@ -4243,7 +4286,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[13] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[13]), .Q(txd_wr_data[13]), .R(sig_Bus2IP_Reset)); @@ -4251,7 +4294,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[14] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[14]), .Q(txd_wr_data[14]), .R(sig_Bus2IP_Reset)); @@ -4259,7 +4302,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[15] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[15]), .Q(txd_wr_data[15]), .R(sig_Bus2IP_Reset)); @@ -4267,7 +4310,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[16] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[16]), .Q(txd_wr_data[16]), .R(sig_Bus2IP_Reset)); @@ -4275,7 +4318,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[17] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[17]), .Q(txd_wr_data[17]), .R(sig_Bus2IP_Reset)); @@ -4283,7 +4326,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[18] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[18]), .Q(txd_wr_data[18]), .R(sig_Bus2IP_Reset)); @@ -4291,7 +4334,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[19] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[19]), .Q(txd_wr_data[19]), .R(sig_Bus2IP_Reset)); @@ -4299,7 +4342,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[1] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[1]), .Q(txd_wr_data_0[1]), .R(sig_Bus2IP_Reset)); @@ -4307,7 +4350,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[20] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[20]), .Q(txd_wr_data[20]), .R(sig_Bus2IP_Reset)); @@ -4315,7 +4358,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[21] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[21]), .Q(txd_wr_data[21]), .R(sig_Bus2IP_Reset)); @@ -4323,7 +4366,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[22] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[22]), .Q(txd_wr_data[22]), .R(sig_Bus2IP_Reset)); @@ -4331,7 +4374,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[23] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[23]), .Q(txd_wr_data[23]), .R(sig_Bus2IP_Reset)); @@ -4339,7 +4382,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[24] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[24]), .Q(txd_wr_data[24]), .R(sig_Bus2IP_Reset)); @@ -4347,7 +4390,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[25] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[25]), .Q(txd_wr_data[25]), .R(sig_Bus2IP_Reset)); @@ -4355,7 +4398,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[26] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[26]), .Q(txd_wr_data[26]), .R(sig_Bus2IP_Reset)); @@ -4363,7 +4406,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[27] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[27]), .Q(txd_wr_data[27]), .R(sig_Bus2IP_Reset)); @@ -4371,7 +4414,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[28] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[28]), .Q(txd_wr_data[28]), .R(sig_Bus2IP_Reset)); @@ -4379,7 +4422,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[29] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[29]), .Q(txd_wr_data[29]), .R(sig_Bus2IP_Reset)); @@ -4387,7 +4430,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[2] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[2]), .Q(txd_wr_data[2]), .R(sig_Bus2IP_Reset)); @@ -4395,7 +4438,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[30] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[30]), .Q(txd_wr_data[30]), .R(sig_Bus2IP_Reset)); @@ -4403,7 +4446,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[31] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[31]), .Q(txd_wr_data[31]), .R(sig_Bus2IP_Reset)); @@ -4411,7 +4454,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[3] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[3]), .Q(txd_wr_data[3]), .R(sig_Bus2IP_Reset)); @@ -4419,7 +4462,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[4] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[4]), .Q(txd_wr_data[4]), .R(sig_Bus2IP_Reset)); @@ -4427,7 +4470,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[5] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[5]), .Q(txd_wr_data[5]), .R(sig_Bus2IP_Reset)); @@ -4435,7 +4478,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[6] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[6]), .Q(txd_wr_data[6]), .R(sig_Bus2IP_Reset)); @@ -4443,7 +4486,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[7] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[7]), .Q(txd_wr_data[7]), .R(sig_Bus2IP_Reset)); @@ -4451,7 +4494,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[8] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[8]), .Q(txd_wr_data[8]), .R(sig_Bus2IP_Reset)); @@ -4459,7 +4502,7 @@ module design_1_axi_fifo_mm_s_0_0_ipic2axi_s .INIT(1'b0)) \sig_txd_wr_data_reg[9] (.C(s_axi_aclk), - .CE(\gtxd.COMP_TXD_FIFO_n_52 ), + .CE(\sig_txd_wr_data[31]_i_1_n_0 ), .D(s_axi_wdata[9]), .Q(txd_wr_data[9]), .R(sig_Bus2IP_Reset)); @@ -4743,22 +4786,20 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment s_axi_rvalid, s_axi_bvalid, s_axi_bresp, - \s_axi_wdata[25] , + \s_axi_wdata[27] , + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] , \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 , - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 , - sig_tx_channel_reset_reg, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 , + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 , + E, bus2ip_rnw_i_reg_0, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] , - sig_txd_sb_wr_en, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] , D, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 , - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] , - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 , + sig_tx_channel_reset_reg, + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 , + \s_axi_wdata[31] , bus2ip_rnw_i_reg_1, - Bus_RNW_reg_reg_0, - E, s_axi_rdata, sig_Bus2IP_Reset, s_axi_aclk, @@ -4770,8 +4811,8 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment s_axi_wvalid, s_axi_awvalid, s_axi_wdata, - \sig_register_array_reg[0][6] , - sig_txd_sb_wr_en_reg, + axi_str_txd_tvalid, + axi_str_txd_tlast, IP2Bus_Error1_in, sig_str_rst_reg, \sig_ip2bus_data_reg[10] , @@ -4782,7 +4823,7 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment \sig_ip2bus_data_reg[6] , \sig_ip2bus_data_reg[4] , \sig_ip2bus_data_reg[3] , - sig_txd_sb_wr_en_reg_0, + IP2Bus_Error_reg, s_axi_rready, s_axi_bready, s_axi_araddr, @@ -4796,23 +4837,21 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment output s_axi_rvalid; output s_axi_bvalid; output [0:0]s_axi_bresp; - output \s_axi_wdata[25] ; + output \s_axi_wdata[27] ; + output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ; output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ; - output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ; - output sig_tx_channel_reset_reg; - output \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 ; + output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ; + output [0:0]E; output bus2ip_rnw_i_reg_0; output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ; - output sig_txd_sb_wr_en; output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ; output [6:0]D; output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ; - output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ; - output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ; + output sig_tx_channel_reset_reg; + output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ; + output [12:0]\s_axi_wdata[31] ; output bus2ip_rnw_i_reg_1; - output [12:0]Bus_RNW_reg_reg_0; - output [0:0]E; - output [21:0]s_axi_rdata; + output [24:0]s_axi_rdata; input sig_Bus2IP_Reset; input s_axi_aclk; input cs_ce_clr; @@ -4823,8 +4862,8 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment input s_axi_wvalid; input s_axi_awvalid; input [12:0]s_axi_wdata; - input \sig_register_array_reg[0][6] ; - input sig_txd_sb_wr_en_reg; + input axi_str_txd_tvalid; + input axi_str_txd_tlast; input IP2Bus_Error1_in; input sig_str_rst_reg; input \sig_ip2bus_data_reg[10] ; @@ -4835,15 +4874,14 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment input \sig_ip2bus_data_reg[6] ; input \sig_ip2bus_data_reg[4] ; input \sig_ip2bus_data_reg[3] ; - input sig_txd_sb_wr_en_reg_0; + input IP2Bus_Error_reg; input s_axi_rready; input s_axi_bready; input [3:0]s_axi_araddr; input [3:0]s_axi_awaddr; - input [21:0]\s_axi_rdata_i_reg[31]_0 ; + input [24:0]\s_axi_rdata_i_reg[31]_0 ; wire Bus_RNW_reg_reg; - wire [12:0]Bus_RNW_reg_reg_0; wire [6:0]D; wire [0:0]E; wire \FSM_onehot_state[0]_i_1_n_0 ; @@ -4857,16 +4895,18 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment wire \FSM_onehot_state_reg_n_0_[1] ; wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] ; wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ; - wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ; - wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 ; wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ; wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ; wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ; - wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ; - wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ; + wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ; + wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ; + wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ; wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ; wire IP2Bus_Error1_in; + wire IP2Bus_Error_reg; wire [6:0]Q; + wire axi_str_txd_tlast; + wire axi_str_txd_tvalid; wire \bus2ip_addr_i[2]_i_1_n_0 ; wire \bus2ip_addr_i[3]_i_1_n_0 ; wire \bus2ip_addr_i[4]_i_1_n_0 ; @@ -4893,15 +4933,16 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment wire \s_axi_bresp_i[1]_i_1_n_0 ; wire s_axi_bvalid; wire s_axi_bvalid_i_i_1_n_0; - wire [21:0]s_axi_rdata; - wire [21:0]\s_axi_rdata_i_reg[31]_0 ; + wire [24:0]s_axi_rdata; + wire [24:0]\s_axi_rdata_i_reg[31]_0 ; wire s_axi_rready; wire [0:0]s_axi_rresp; wire s_axi_rresp_i; wire s_axi_rvalid; wire s_axi_rvalid_i_i_1_n_0; wire [12:0]s_axi_wdata; - wire \s_axi_wdata[25] ; + wire \s_axi_wdata[27] ; + wire [12:0]\s_axi_wdata[31] ; wire s_axi_wvalid; wire sig_Bus2IP_CS; wire sig_Bus2IP_RNW; @@ -4913,12 +4954,8 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment wire \sig_ip2bus_data_reg[7] ; wire \sig_ip2bus_data_reg[8] ; wire \sig_ip2bus_data_reg[9] ; - wire \sig_register_array_reg[0][6] ; wire sig_str_rst_reg; wire sig_tx_channel_reset_reg; - wire sig_txd_sb_wr_en; - wire sig_txd_sb_wr_en_reg; - wire sig_txd_sb_wr_en_reg_0; wire start2; wire start2_i_1_n_0; @@ -5004,14 +5041,14 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .D(\FSM_onehot_state[3]_i_1_n_0 ), .Q(s_axi_rresp_i), .R(rst)); - (* SOFT_HLUTNM = "soft_lutpair49" *) + (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h2)) IP2Bus_RdAck_i_2 (.I0(sig_Bus2IP_RNW), .I1(IP2Bus_Error1_in), .O(bus2ip_rnw_i_reg_0)); - (* SOFT_HLUTNM = "soft_lutpair49" *) + (* SOFT_HLUTNM = "soft_lutpair29" *) LUT1 #( .INIT(2'h1)) IP2Bus_WrAck_i_2 @@ -5019,26 +5056,28 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .O(bus2ip_rnw_i_reg_1)); design_1_axi_fifo_mm_s_0_0_address_decoder I_DECODER (.Bus_RNW_reg_reg_0(Bus_RNW_reg_reg), - .Bus_RNW_reg_reg_1(Bus_RNW_reg_reg_0), .D(D), .E(E), .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] ), .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0 ), - .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1 ), - .\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3 (\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2 ), .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ), .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ), .\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ), - .\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ), - .\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ), + .\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ), + .\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ), + .\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ), .\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ), .\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0 ({\bus2ip_addr_i_reg_n_0_[5] ,\bus2ip_addr_i_reg_n_0_[4] ,\bus2ip_addr_i_reg_n_0_[3] ,\bus2ip_addr_i_reg_n_0_[2] }), .IP2Bus_Error1_in(IP2Bus_Error1_in), + .IP2Bus_Error_reg(IP2Bus_Error_reg), .Q(Q), + .axi_str_txd_tlast(axi_str_txd_tlast), + .axi_str_txd_tvalid(axi_str_txd_tvalid), .cs_ce_clr(cs_ce_clr), .s_axi_aclk(s_axi_aclk), .s_axi_wdata(s_axi_wdata), - .\s_axi_wdata[25] (\s_axi_wdata[25] ), + .\s_axi_wdata[27] (\s_axi_wdata[27] ), + .\s_axi_wdata[31] (\s_axi_wdata[31] ), .sig_Bus2IP_CS(sig_Bus2IP_CS), .sig_Bus2IP_RNW(sig_Bus2IP_RNW), .\sig_ip2bus_data_reg[10] (\sig_ip2bus_data_reg[10] ), @@ -5048,14 +5087,10 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .\sig_ip2bus_data_reg[7] (\sig_ip2bus_data_reg[7] ), .\sig_ip2bus_data_reg[8] (\sig_ip2bus_data_reg[8] ), .\sig_ip2bus_data_reg[9] (\sig_ip2bus_data_reg[9] ), - .\sig_register_array_reg[0][6] (\sig_register_array_reg[0][6] ), .sig_str_rst_reg(sig_str_rst_reg), .sig_tx_channel_reset_reg(sig_tx_channel_reset_reg), - .sig_txd_sb_wr_en(sig_txd_sb_wr_en), - .sig_txd_sb_wr_en_reg(sig_txd_sb_wr_en_reg), - .sig_txd_sb_wr_en_reg_0(sig_txd_sb_wr_en_reg_0), .start2(start2)); - (* SOFT_HLUTNM = "soft_lutpair48" *) + (* SOFT_HLUTNM = "soft_lutpair28" *) LUT4 #( .INIT(16'hF780)) \bus2ip_addr_i[2]_i_1 @@ -5120,7 +5155,7 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .I2(s_axi_wvalid), .I3(s_axi_awvalid), .O(bus2ip_rnw_i_i_1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair48" *) + (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h8)) bus2ip_rnw_i_i_2 @@ -5172,12 +5207,36 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .R(rst)); FDRE #( .INIT(1'b0)) - \s_axi_rdata_i_reg[19] + \s_axi_rdata_i_reg[10] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [9]), .Q(s_axi_rdata[9]), .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[11] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(\s_axi_rdata_i_reg[31]_0 [10]), + .Q(s_axi_rdata[10]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[12] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(\s_axi_rdata_i_reg[31]_0 [11]), + .Q(s_axi_rdata[11]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[19] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(\s_axi_rdata_i_reg[31]_0 [12]), + .Q(s_axi_rdata[12]), + .R(rst)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[1] @@ -5189,30 +5248,6 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[20] - (.C(s_axi_aclk), - .CE(s_axi_rresp_i), - .D(\s_axi_rdata_i_reg[31]_0 [10]), - .Q(s_axi_rdata[10]), - .R(rst)); - FDRE #( - .INIT(1'b0)) - \s_axi_rdata_i_reg[21] - (.C(s_axi_aclk), - .CE(s_axi_rresp_i), - .D(\s_axi_rdata_i_reg[31]_0 [11]), - .Q(s_axi_rdata[11]), - .R(rst)); - FDRE #( - .INIT(1'b0)) - \s_axi_rdata_i_reg[22] - (.C(s_axi_aclk), - .CE(s_axi_rresp_i), - .D(\s_axi_rdata_i_reg[31]_0 [12]), - .Q(s_axi_rdata[12]), - .R(rst)); - FDRE #( - .INIT(1'b0)) - \s_axi_rdata_i_reg[23] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [13]), @@ -5220,7 +5255,7 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .R(rst)); FDRE #( .INIT(1'b0)) - \s_axi_rdata_i_reg[24] + \s_axi_rdata_i_reg[21] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [14]), @@ -5228,7 +5263,7 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .R(rst)); FDRE #( .INIT(1'b0)) - \s_axi_rdata_i_reg[25] + \s_axi_rdata_i_reg[22] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [15]), @@ -5236,7 +5271,7 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .R(rst)); FDRE #( .INIT(1'b0)) - \s_axi_rdata_i_reg[26] + \s_axi_rdata_i_reg[23] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [16]), @@ -5244,7 +5279,7 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .R(rst)); FDRE #( .INIT(1'b0)) - \s_axi_rdata_i_reg[27] + \s_axi_rdata_i_reg[24] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [17]), @@ -5252,7 +5287,7 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .R(rst)); FDRE #( .INIT(1'b0)) - \s_axi_rdata_i_reg[28] + \s_axi_rdata_i_reg[25] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [18]), @@ -5260,12 +5295,36 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment .R(rst)); FDRE #( .INIT(1'b0)) - \s_axi_rdata_i_reg[29] + \s_axi_rdata_i_reg[26] (.C(s_axi_aclk), .CE(s_axi_rresp_i), .D(\s_axi_rdata_i_reg[31]_0 [19]), .Q(s_axi_rdata[19]), .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[27] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(\s_axi_rdata_i_reg[31]_0 [20]), + .Q(s_axi_rdata[20]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[28] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(\s_axi_rdata_i_reg[31]_0 [21]), + .Q(s_axi_rdata[21]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[29] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(\s_axi_rdata_i_reg[31]_0 [22]), + .Q(s_axi_rdata[22]), + .R(rst)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[2] @@ -5279,16 +5338,16 @@ module design_1_axi_fifo_mm_s_0_0_slave_attachment \s_axi_rdata_i_reg[30] (.C(s_axi_aclk), .CE(s_axi_rresp_i), - .D(\s_axi_rdata_i_reg[31]_0 [20]), - .Q(s_axi_rdata[20]), + .D(\s_axi_rdata_i_reg[31]_0 [23]), + .Q(s_axi_rdata[23]), .R(rst)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[31] (.C(s_axi_aclk), .CE(s_axi_rresp_i), - .D(\s_axi_rdata_i_reg[31]_0 [21]), - .Q(s_axi_rdata[21]), + .D(\s_axi_rdata_i_reg[31]_0 [24]), + .Q(s_axi_rdata[24]), .R(rst)); FDRE #( .INIT(1'b0)) @@ -5451,247 +5510,167 @@ endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized0 - (\count_value_i_reg[7]_0 , - Q, - \count_value_i_reg[4]_0 , + (Q, + S, \count_value_i_reg[0]_0 , - E, + ram_wr_en_pf, wr_clk); - output [0:0]\count_value_i_reg[7]_0 ; - input [8:0]Q; - input \count_value_i_reg[4]_0 ; + output [11:0]Q; + input [0:0]S; input [0:0]\count_value_i_reg[0]_0 ; - input [0:0]E; + input ram_wr_en_pf; input wr_clk; - wire [0:0]E; - wire [8:0]Q; - wire \count_value_i[0]_i_1__3_n_0 ; - wire \count_value_i[1]_i_1__1_n_0 ; - wire \count_value_i[2]_i_1__0_n_0 ; - wire \count_value_i[3]_i_1__0_n_0 ; - wire \count_value_i[4]_i_1__0_n_0 ; - wire \count_value_i[5]_i_1__0_n_0 ; - wire \count_value_i[6]_i_1__0_n_0 ; - wire \count_value_i[7]_i_1__0_n_0 ; - wire \count_value_i[8]_i_1__2_n_0 ; - wire \count_value_i[8]_i_2__0_n_0 ; + wire [11:0]Q; + wire [0:0]S; wire [0:0]\count_value_i_reg[0]_0 ; - wire \count_value_i_reg[4]_0 ; - wire [0:0]\count_value_i_reg[7]_0 ; - wire \count_value_i_reg_n_0_[0] ; - wire \count_value_i_reg_n_0_[1] ; - wire \count_value_i_reg_n_0_[2] ; - wire \count_value_i_reg_n_0_[3] ; - wire \count_value_i_reg_n_0_[4] ; - wire \count_value_i_reg_n_0_[5] ; - wire \count_value_i_reg_n_0_[6] ; - wire \count_value_i_reg_n_0_[7] ; - wire \count_value_i_reg_n_0_[8] ; - wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0 ; - wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0 ; - wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0 ; - wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2 ; - wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3 ; + wire \count_value_i_reg[11]_i_1__3_n_1 ; + wire \count_value_i_reg[11]_i_1__3_n_2 ; + wire \count_value_i_reg[11]_i_1__3_n_3 ; + wire \count_value_i_reg[11]_i_1__3_n_4 ; + wire \count_value_i_reg[11]_i_1__3_n_5 ; + wire \count_value_i_reg[11]_i_1__3_n_6 ; + wire \count_value_i_reg[11]_i_1__3_n_7 ; + wire \count_value_i_reg[3]_i_1__3_n_0 ; + wire \count_value_i_reg[3]_i_1__3_n_1 ; + wire \count_value_i_reg[3]_i_1__3_n_2 ; + wire \count_value_i_reg[3]_i_1__3_n_3 ; + wire \count_value_i_reg[3]_i_1__3_n_4 ; + wire \count_value_i_reg[3]_i_1__3_n_5 ; + wire \count_value_i_reg[3]_i_1__3_n_6 ; + wire \count_value_i_reg[3]_i_1__3_n_7 ; + wire \count_value_i_reg[7]_i_1__3_n_0 ; + wire \count_value_i_reg[7]_i_1__3_n_1 ; + wire \count_value_i_reg[7]_i_1__3_n_2 ; + wire \count_value_i_reg[7]_i_1__3_n_3 ; + wire \count_value_i_reg[7]_i_1__3_n_4 ; + wire \count_value_i_reg[7]_i_1__3_n_5 ; + wire \count_value_i_reg[7]_i_1__3_n_6 ; + wire \count_value_i_reg[7]_i_1__3_n_7 ; + wire ram_wr_en_pf; wire wr_clk; - wire [3:3]\NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_CO_UNCONNECTED ; - wire [3:0]\NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_count_value_i_reg[11]_i_1__3_CO_UNCONNECTED ; - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT1 #( - .INIT(2'h1)) - \count_value_i[0]_i_1__3 - (.I0(\count_value_i_reg_n_0_[0] ), - .O(\count_value_i[0]_i_1__3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT2 #( - .INIT(4'h6)) - \count_value_i[1]_i_1__1 - (.I0(\count_value_i_reg_n_0_[1] ), - .I1(\count_value_i_reg_n_0_[0] ), - .O(\count_value_i[1]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT4 #( - .INIT(16'hDF20)) - \count_value_i[2]_i_1__0 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[2] ), - .O(\count_value_i[2]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT5 #( - .INIT(32'hDF20FF00)) - \count_value_i[3]_i_1__0 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[3] ), - .I4(\count_value_i_reg_n_0_[2] ), - .O(\count_value_i[3]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'hDF20FF00FF00FF00)) - \count_value_i[4]_i_1__0 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[4] ), - .I4(\count_value_i_reg_n_0_[2] ), - .I5(\count_value_i_reg_n_0_[3] ), - .O(\count_value_i[4]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT2 #( - .INIT(4'h9)) - \count_value_i[5]_i_1__0 - (.I0(\count_value_i[8]_i_2__0_n_0 ), - .I1(\count_value_i_reg_n_0_[5] ), - .O(\count_value_i[5]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'h9A)) - \count_value_i[6]_i_1__0 - (.I0(\count_value_i_reg_n_0_[6] ), - .I1(\count_value_i[8]_i_2__0_n_0 ), - .I2(\count_value_i_reg_n_0_[5] ), - .O(\count_value_i[6]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT4 #( - .INIT(16'hA6AA)) - \count_value_i[7]_i_1__0 - (.I0(\count_value_i_reg_n_0_[7] ), - .I1(\count_value_i_reg_n_0_[5] ), - .I2(\count_value_i[8]_i_2__0_n_0 ), - .I3(\count_value_i_reg_n_0_[6] ), - .O(\count_value_i[7]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT5 #( - .INIT(32'hA6AAAAAA)) - \count_value_i[8]_i_1__2 - (.I0(\count_value_i_reg_n_0_[8] ), - .I1(\count_value_i_reg_n_0_[6] ), - .I2(\count_value_i[8]_i_2__0_n_0 ), - .I3(\count_value_i_reg_n_0_[5] ), - .I4(\count_value_i_reg_n_0_[7] ), - .O(\count_value_i[8]_i_1__2_n_0 )); - LUT6 #( - .INIT(64'hDFFFFFFFFFFFFFFF)) - \count_value_i[8]_i_2__0 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[3] ), - .I4(\count_value_i_reg_n_0_[2] ), - .I5(\count_value_i_reg_n_0_[4] ), - .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), - .CE(E), - .D(\count_value_i[0]_i_1__3_n_0 ), - .Q(\count_value_i_reg_n_0_[0] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__3_n_7 ), + .Q(Q[0]), .R(\count_value_i_reg[0]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[10] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__3_n_5 ), + .Q(Q[10]), + .R(\count_value_i_reg[0]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[11] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__3_n_4 ), + .Q(Q[11]), + .R(\count_value_i_reg[0]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[11]_i_1__3 + (.CI(\count_value_i_reg[7]_i_1__3_n_0 ), + .CO({\NLW_count_value_i_reg[11]_i_1__3_CO_UNCONNECTED [3],\count_value_i_reg[11]_i_1__3_n_1 ,\count_value_i_reg[11]_i_1__3_n_2 ,\count_value_i_reg[11]_i_1__3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[11]_i_1__3_n_4 ,\count_value_i_reg[11]_i_1__3_n_5 ,\count_value_i_reg[11]_i_1__3_n_6 ,\count_value_i_reg[11]_i_1__3_n_7 }), + .S(Q[11:8])); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), - .CE(E), - .D(\count_value_i[1]_i_1__1_n_0 ), - .Q(\count_value_i_reg_n_0_[1] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__3_n_6 ), + .Q(Q[1]), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), - .CE(E), - .D(\count_value_i[2]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[2] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__3_n_5 ), + .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), - .CE(E), - .D(\count_value_i[3]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[3] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__3_n_4 ), + .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[3]_i_1__3 + (.CI(1'b0), + .CO({\count_value_i_reg[3]_i_1__3_n_0 ,\count_value_i_reg[3]_i_1__3_n_1 ,\count_value_i_reg[3]_i_1__3_n_2 ,\count_value_i_reg[3]_i_1__3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[0]}), + .O({\count_value_i_reg[3]_i_1__3_n_4 ,\count_value_i_reg[3]_i_1__3_n_5 ,\count_value_i_reg[3]_i_1__3_n_6 ,\count_value_i_reg[3]_i_1__3_n_7 }), + .S({Q[3:1],S})); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), - .CE(E), - .D(\count_value_i[4]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[4] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__3_n_7 ), + .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), - .CE(E), - .D(\count_value_i[5]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[5] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__3_n_6 ), + .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), - .CE(E), - .D(\count_value_i[6]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[6] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__3_n_5 ), + .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), - .CE(E), - .D(\count_value_i[7]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[7] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__3_n_4 ), + .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[7]_i_1__3 + (.CI(\count_value_i_reg[3]_i_1__3_n_0 ), + .CO({\count_value_i_reg[7]_i_1__3_n_0 ,\count_value_i_reg[7]_i_1__3_n_1 ,\count_value_i_reg[7]_i_1__3_n_2 ,\count_value_i_reg[7]_i_1__3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[7]_i_1__3_n_4 ,\count_value_i_reg[7]_i_1__3_n_5 ,\count_value_i_reg[7]_i_1__3_n_6 ,\count_value_i_reg[7]_i_1__3_n_7 }), + .S(Q[7:4])); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), - .CE(E), - .D(\count_value_i[8]_i_1__2_n_0 ), - .Q(\count_value_i_reg_n_0_[8] ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__3_n_7 ), + .Q(Q[8]), + .R(\count_value_i_reg[0]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[9] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__3_n_6 ), + .Q(Q[9]), .R(\count_value_i_reg[0]_0 )); - LUT6 #( - .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4 - (.I0(\count_value_i_reg_n_0_[7] ), - .I1(Q[7]), - .I2(Q[8]), - .I3(\count_value_i_reg_n_0_[8] ), - .I4(Q[6]), - .I5(\count_value_i_reg_n_0_[6] ), - .O(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0 )); - LUT6 #( - .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5 - (.I0(\count_value_i_reg_n_0_[3] ), - .I1(Q[3]), - .I2(Q[5]), - .I3(\count_value_i_reg_n_0_[5] ), - .I4(Q[4]), - .I5(\count_value_i_reg_n_0_[4] ), - .O(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0 )); - LUT6 #( - .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6 - (.I0(\count_value_i_reg_n_0_[1] ), - .I1(Q[1]), - .I2(Q[2]), - .I3(\count_value_i_reg_n_0_[2] ), - .I4(Q[0]), - .I5(\count_value_i_reg_n_0_[0] ), - .O(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0 )); - CARRY4 \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3 - (.CI(1'b0), - .CO({\NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_CO_UNCONNECTED [3],\count_value_i_reg[7]_0 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3 }), - .CYINIT(1'b1), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED [3:0]), - .S({1'b0,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) @@ -5699,9 +5678,9 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized1 (Q, S, DI, - \count_value_i_reg[1]_0 , - rd_en, ram_empty_i, + \count_value_i_reg[0]_0 , + rd_en, \grdc.rd_data_count_i_reg[3] , \grdc.rd_data_count_i_reg[3]_0 , SR, @@ -5709,9 +5688,9 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized1 output [0:0]Q; output [1:0]S; output [0:0]DI; - input [1:0]\count_value_i_reg[1]_0 ; - input rd_en; input ram_empty_i; + input [1:0]\count_value_i_reg[0]_0 ; + input rd_en; input [1:0]\grdc.rd_data_count_i_reg[3] ; input [1:0]\grdc.rd_data_count_i_reg[3]_0 ; input [0:0]SR; @@ -5722,9 +5701,9 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized1 wire [1:0]S; wire [0:0]SR; wire [0:0]count_value_i; - wire \count_value_i[0]_i_1__0_n_0 ; + wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_3_n_0 ; - wire [1:0]\count_value_i_reg[1]_0 ; + wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire [1:0]\grdc.rd_data_count_i_reg[3] ; wire [1:0]\grdc.rd_data_count_i_reg[3]_0 ; @@ -5733,36 +5712,40 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized1 wire wr_clk; (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT1 #( - .INIT(2'h1)) - \count_value_i[0]_i_1__0 + LUT5 #( + .INIT(32'h5AAAA655)) + \count_value_i[0]_i_1 (.I0(count_value_i), - .O(\count_value_i[0]_i_1__0_n_0 )); + .I1(\count_value_i_reg[0]_0 [0]), + .I2(rd_en), + .I3(\count_value_i_reg[0]_0 [1]), + .I4(ram_empty_i), + .O(\count_value_i[0]_i_1_n_0 )); LUT4 #( - .INIT(16'h9585)) + .INIT(16'hC02F)) \count_value_i[1]_i_2 - (.I0(ram_empty_i), + (.I0(\count_value_i_reg[0]_0 [0]), .I1(rd_en), - .I2(\count_value_i_reg[1]_0 [1]), - .I3(\count_value_i_reg[1]_0 [0]), + .I2(\count_value_i_reg[0]_0 [1]), + .I3(ram_empty_i), .O(\gen_fwft.count_en )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT6 #( - .INIT(64'hAA956AAAAA996AAA)) + .INIT(64'hA999A9A96AAA6AAA)) \count_value_i[1]_i_3 (.I0(Q), - .I1(\count_value_i_reg[1]_0 [1]), - .I2(rd_en), - .I3(ram_empty_i), - .I4(count_value_i), - .I5(\count_value_i_reg[1]_0 [0]), + .I1(ram_empty_i), + .I2(\count_value_i_reg[0]_0 [1]), + .I3(rd_en), + .I4(\count_value_i_reg[0]_0 [0]), + .I5(count_value_i), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(\gen_fwft.count_en ), - .D(\count_value_i[0]_i_1__0_n_0 ), + .D(\count_value_i[0]_i_1_n_0 ), .Q(count_value_i), .R(SR)); FDRE #( @@ -5778,744 +5761,732 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized1 .INIT(4'hB)) \gwdc.wr_data_count_i[3]_i_4 (.I0(count_value_i), - .I1(\grdc.rd_data_count_i_reg[3]_0 [0]), + .I1(\grdc.rd_data_count_i_reg[3] [0]), .O(DI)); LUT4 #( .INIT(16'h9669)) \gwdc.wr_data_count_i[3]_i_7 (.I0(DI), .I1(\grdc.rd_data_count_i_reg[3] [1]), - .I2(\grdc.rd_data_count_i_reg[3]_0 [1]), - .I3(Q), + .I2(Q), + .I3(\grdc.rd_data_count_i_reg[3]_0 [1]), .O(S[1])); (* HLUTNM = "lutpair0" *) LUT3 #( .INIT(8'h96)) \gwdc.wr_data_count_i[3]_i_8 (.I0(count_value_i), - .I1(\grdc.rd_data_count_i_reg[3]_0 [0]), - .I2(\grdc.rd_data_count_i_reg[3] [0]), + .I1(\grdc.rd_data_count_i_reg[3] [0]), + .I2(\grdc.rd_data_count_i_reg[3]_0 [0]), .O(S[0])); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2 - (\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg , + (\syncstages_ff_reg[3] , \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] , - \syncstages_ff_reg[3] , + DI, Q, - E, - D, - \count_value_i_reg[8]_0 , - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 , - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg , - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0 , + S, + \count_value_i_reg[1]_0 , + \count_value_i_reg[11]_0 , CO, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1 , + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg , + \count_value_i_reg[3]_0 , + \count_value_i_reg[7]_0 , + \count_value_i_reg[11]_1 , + \count_value_i_reg[0]_0 , + \count_value_i_reg[1]_1 , + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 , + clr_full, rst, almost_full, - \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg , - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2 , - ram_empty_i, + ram_wr_en_pf, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] , + \grdc.rd_data_count_i_reg[12] , + \grdc.rd_data_count_i_reg[3] , + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 , + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg , + \count_value_i_reg[0]_1 , rd_en, - S, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] , - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] , - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] , - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8] , - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 , - \count_value_i_reg[0]_0 , + ram_empty_i, + \count_value_i_reg[0]_2 , wr_clk); - output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ; - output \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ; output \syncstages_ff_reg[3] ; - output [9:0]Q; - output [0:0]E; - output [8:0]D; - output [8:0]\count_value_i_reg[8]_0 ; + output \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ; + output [0:0]DI; + output [11:0]Q; + output [0:0]S; + output [0:0]\count_value_i_reg[1]_0 ; + output [0:0]\count_value_i_reg[11]_0 ; + output [0:0]CO; + output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ; + output [2:0]\count_value_i_reg[3]_0 ; + output [3:0]\count_value_i_reg[7]_0 ; + output [3:0]\count_value_i_reg[11]_1 ; + output [0:0]\count_value_i_reg[0]_0 ; + output [0:0]\count_value_i_reg[1]_1 ; output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ; - input \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg ; - input \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0 ; - input [0:0]CO; - input \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1 ; + input clr_full; input rst; input almost_full; - input [0:0]\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg ; - input [1:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2 ; - input ram_empty_i; + input ram_wr_en_pf; + input [11:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] ; + input [12:0]\grdc.rd_data_count_i_reg[12] ; + input [0:0]\grdc.rd_data_count_i_reg[3] ; + input [11:0]\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 ; + input \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg ; + input [1:0]\count_value_i_reg[0]_1 ; input rd_en; - input [0:0]S; - input [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] ; - input [7:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] ; - input [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ; - input [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8] ; - input [8:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 ; - input [0:0]\count_value_i_reg[0]_0 ; + input ram_empty_i; + input [0:0]\count_value_i_reg[0]_2 ; input wr_clk; wire [0:0]CO; - wire [8:0]D; - wire [0:0]E; + wire [0:0]DI; wire \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ; - wire [9:0]Q; + wire [11:0]Q; wire [0:0]S; wire almost_full; - wire \count_value_i[0]_i_1_n_0 ; - wire \count_value_i[1]_i_1__4_n_0 ; - wire \count_value_i[2]_i_1__2_n_0 ; - wire \count_value_i[3]_i_1__2_n_0 ; - wire \count_value_i[4]_i_1__2_n_0 ; - wire \count_value_i[5]_i_1__2_n_0 ; - wire \count_value_i[6]_i_1__2_n_0 ; - wire \count_value_i[7]_i_1__2_n_0 ; - wire \count_value_i[8]_i_1_n_0 ; - wire \count_value_i[9]_i_1_n_0 ; - wire \count_value_i[9]_i_2_n_0 ; + wire clr_full; + wire \count_value_i[3]_i_2__0_n_0 ; wire [0:0]\count_value_i_reg[0]_0 ; - wire [8:0]\count_value_i_reg[8]_0 ; - wire [0:0]\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg ; + wire [1:0]\count_value_i_reg[0]_1 ; + wire [0:0]\count_value_i_reg[0]_2 ; + wire [0:0]\count_value_i_reg[11]_0 ; + wire [3:0]\count_value_i_reg[11]_1 ; + wire \count_value_i_reg[11]_i_1__0_n_0 ; + wire \count_value_i_reg[11]_i_1__0_n_1 ; + wire \count_value_i_reg[11]_i_1__0_n_2 ; + wire \count_value_i_reg[11]_i_1__0_n_3 ; + wire \count_value_i_reg[11]_i_1__0_n_4 ; + wire \count_value_i_reg[11]_i_1__0_n_5 ; + wire \count_value_i_reg[11]_i_1__0_n_6 ; + wire \count_value_i_reg[11]_i_1__0_n_7 ; + wire \count_value_i_reg[12]_i_1__0_n_7 ; + wire [0:0]\count_value_i_reg[1]_0 ; + wire [0:0]\count_value_i_reg[1]_1 ; + wire [2:0]\count_value_i_reg[3]_0 ; + wire \count_value_i_reg[3]_i_1__0_n_0 ; + wire \count_value_i_reg[3]_i_1__0_n_1 ; + wire \count_value_i_reg[3]_i_1__0_n_2 ; + wire \count_value_i_reg[3]_i_1__0_n_3 ; + wire \count_value_i_reg[3]_i_1__0_n_4 ; + wire \count_value_i_reg[3]_i_1__0_n_5 ; + wire \count_value_i_reg[3]_i_1__0_n_6 ; + wire \count_value_i_reg[3]_i_1__0_n_7 ; + wire [3:0]\count_value_i_reg[7]_0 ; + wire \count_value_i_reg[7]_i_1__0_n_0 ; + wire \count_value_i_reg[7]_i_1__0_n_1 ; + wire \count_value_i_reg[7]_i_1__0_n_2 ; + wire \count_value_i_reg[7]_i_1__0_n_3 ; + wire \count_value_i_reg[7]_i_1__0_n_4 ; + wire \count_value_i_reg[7]_i_1__0_n_5 ; + wire \count_value_i_reg[7]_i_1__0_n_6 ; + wire \count_value_i_reg[7]_i_1__0_n_7 ; + wire \count_value_i_reg_n_0_[12] ; + wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0 ; + wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0 ; + wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0 ; + wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0 ; + wire [11:0]\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 ; + wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_1 ; + wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2 ; + wire \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3 ; wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ; wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5_n_0 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0 ; wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0 ; wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0 ; wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0 ; wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0 ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1 ; - wire [1:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2 ; - wire [8:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_2 ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_3 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9_n_0 ; - wire [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3 ; - wire [7:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3 ; - wire [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8] ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3 ; - wire [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_1 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_2 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_3 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_1 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_2 ; + wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_3 ; + wire [11:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] ; + wire going_afull1; wire going_full1; + wire [12:0]\grdc.rd_data_count_i_reg[12] ; + wire [0:0]\grdc.rd_data_count_i_reg[3] ; wire ram_afull_i0; wire ram_empty_i; + wire ram_wr_en_pf; wire rd_en; wire rst; wire \syncstages_ff_reg[3] ; wire wr_clk; - wire [3:3]\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_CO_UNCONNECTED ; - wire [3:0]\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_O_UNCONNECTED ; - wire [3:0]\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED ; - wire [3:1]\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED ; - wire [3:0]\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED ; - wire [3:1]\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED ; + wire [3:0]\NLW_count_value_i_reg[12]_i_1__0_CO_UNCONNECTED ; + wire [3:1]\NLW_count_value_i_reg[12]_i_1__0_O_UNCONNECTED ; + wire [3:0]\NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED ; + wire [3:0]\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_O_UNCONNECTED ; + wire [3:0]\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_O_UNCONNECTED ; - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT1 #( - .INIT(2'h1)) - \count_value_i[0]_i_1 - (.I0(Q[0]), - .O(\count_value_i[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) - \count_value_i[1]_i_1__4 - (.I0(Q[1]), + \count_value_i[3]_i_2__0 + (.I0(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), .I1(Q[0]), - .O(\count_value_i[1]_i_1__4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT4 #( - .INIT(16'hDF20)) - \count_value_i[2]_i_1__2 - (.I0(Q[0]), - .I1(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I2(Q[1]), - .I3(Q[2]), - .O(\count_value_i[2]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT5 #( - .INIT(32'hDF20FF00)) - \count_value_i[3]_i_1__2 - (.I0(Q[0]), - .I1(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[2]), - .O(\count_value_i[3]_i_1__2_n_0 )); - LUT6 #( - .INIT(64'hDF20FF00FF00FF00)) - \count_value_i[4]_i_1__2 - (.I0(Q[0]), - .I1(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I2(Q[1]), - .I3(Q[4]), - .I4(Q[3]), - .I5(Q[2]), - .O(\count_value_i[4]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT2 #( - .INIT(4'h9)) - \count_value_i[5]_i_1__2 - (.I0(Q[5]), - .I1(\count_value_i[9]_i_2_n_0 ), - .O(\count_value_i[5]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'hA6)) - \count_value_i[6]_i_1__2 - (.I0(Q[6]), - .I1(Q[5]), - .I2(\count_value_i[9]_i_2_n_0 ), - .O(\count_value_i[6]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT4 #( - .INIT(16'hA6AA)) - \count_value_i[7]_i_1__2 - (.I0(Q[7]), - .I1(Q[6]), - .I2(\count_value_i[9]_i_2_n_0 ), - .I3(Q[5]), - .O(\count_value_i[7]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT5 #( - .INIT(32'hA6AAAAAA)) - \count_value_i[8]_i_1 - (.I0(Q[8]), - .I1(Q[5]), - .I2(\count_value_i[9]_i_2_n_0 ), - .I3(Q[6]), - .I4(Q[7]), - .O(\count_value_i[8]_i_1_n_0 )); - LUT6 #( - .INIT(64'hAAAA6AAAAAAAAAAA)) - \count_value_i[9]_i_1 - (.I0(Q[9]), - .I1(Q[8]), - .I2(Q[7]), - .I3(Q[6]), - .I4(\count_value_i[9]_i_2_n_0 ), - .I5(Q[5]), - .O(\count_value_i[9]_i_1_n_0 )); - LUT6 #( - .INIT(64'hDFFFFFFFFFFFFFFF)) - \count_value_i[9]_i_2 - (.I0(Q[0]), - .I1(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[2]), - .I5(Q[4]), - .O(\count_value_i[9]_i_2_n_0 )); + .O(\count_value_i[3]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), - .CE(E), - .D(\count_value_i[0]_i_1_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[3]_i_1__0_n_7 ), .Q(Q[0]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[10] + (.C(wr_clk), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[11]_i_1__0_n_5 ), + .Q(Q[10]), + .R(\count_value_i_reg[0]_2 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[11] + (.C(wr_clk), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[11]_i_1__0_n_4 ), + .Q(Q[11]), + .R(\count_value_i_reg[0]_2 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[11]_i_1__0 + (.CI(\count_value_i_reg[7]_i_1__0_n_0 ), + .CO({\count_value_i_reg[11]_i_1__0_n_0 ,\count_value_i_reg[11]_i_1__0_n_1 ,\count_value_i_reg[11]_i_1__0_n_2 ,\count_value_i_reg[11]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[11]_i_1__0_n_4 ,\count_value_i_reg[11]_i_1__0_n_5 ,\count_value_i_reg[11]_i_1__0_n_6 ,\count_value_i_reg[11]_i_1__0_n_7 }), + .S(Q[11:8])); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[12] + (.C(wr_clk), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[12]_i_1__0_n_7 ), + .Q(\count_value_i_reg_n_0_[12] ), + .R(\count_value_i_reg[0]_2 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[12]_i_1__0 + (.CI(\count_value_i_reg[11]_i_1__0_n_0 ), + .CO(\NLW_count_value_i_reg[12]_i_1__0_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_count_value_i_reg[12]_i_1__0_O_UNCONNECTED [3:1],\count_value_i_reg[12]_i_1__0_n_7 }), + .S({1'b0,1'b0,1'b0,\count_value_i_reg_n_0_[12] })); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), - .CE(E), - .D(\count_value_i[1]_i_1__4_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[3]_i_1__0_n_6 ), .Q(Q[1]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), - .CE(E), - .D(\count_value_i[2]_i_1__2_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[3]_i_1__0_n_5 ), .Q(Q[2]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), - .CE(E), - .D(\count_value_i[3]_i_1__2_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[3]_i_1__0_n_4 ), .Q(Q[3]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[3]_i_1__0 + (.CI(1'b0), + .CO({\count_value_i_reg[3]_i_1__0_n_0 ,\count_value_i_reg[3]_i_1__0_n_1 ,\count_value_i_reg[3]_i_1__0_n_2 ,\count_value_i_reg[3]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[0]}), + .O({\count_value_i_reg[3]_i_1__0_n_4 ,\count_value_i_reg[3]_i_1__0_n_5 ,\count_value_i_reg[3]_i_1__0_n_6 ,\count_value_i_reg[3]_i_1__0_n_7 }), + .S({Q[3:1],\count_value_i[3]_i_2__0_n_0 })); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), - .CE(E), - .D(\count_value_i[4]_i_1__2_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[7]_i_1__0_n_7 ), .Q(Q[4]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), - .CE(E), - .D(\count_value_i[5]_i_1__2_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[7]_i_1__0_n_6 ), .Q(Q[5]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), - .CE(E), - .D(\count_value_i[6]_i_1__2_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[7]_i_1__0_n_5 ), .Q(Q[6]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), - .CE(E), - .D(\count_value_i[7]_i_1__2_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[7]_i_1__0_n_4 ), .Q(Q[7]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[7]_i_1__0 + (.CI(\count_value_i_reg[3]_i_1__0_n_0 ), + .CO({\count_value_i_reg[7]_i_1__0_n_0 ,\count_value_i_reg[7]_i_1__0_n_1 ,\count_value_i_reg[7]_i_1__0_n_2 ,\count_value_i_reg[7]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[7]_i_1__0_n_4 ,\count_value_i_reg[7]_i_1__0_n_5 ,\count_value_i_reg[7]_i_1__0_n_6 ,\count_value_i_reg[7]_i_1__0_n_7 }), + .S(Q[7:4])); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), - .CE(E), - .D(\count_value_i[8]_i_1_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[11]_i_1__0_n_7 ), .Q(Q[8]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(wr_clk), - .CE(E), - .D(\count_value_i[9]_i_1_n_0 ), + .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .D(\count_value_i_reg[11]_i_1__0_n_6 ), .Q(Q[9]), - .R(\count_value_i_reg[0]_0 )); + .R(\count_value_i_reg[0]_2 )); LUT4 #( - .INIT(16'h3202)) + .INIT(16'hF202)) \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_1 (.I0(ram_afull_i0), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1 ), + .I1(clr_full), .I2(rst), .I3(almost_full), .O(\syncstages_ff_reg[3] )); LUT5 #( - .INIT(32'hC4FCC4CC)) + .INIT(32'hF3FF00A0)) \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_2 - (.I0(going_full1), - .I1(almost_full), - .I2(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg ), - .I4(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg ), + (.I0(going_afull1), + .I1(going_full1), + .I2(ram_wr_en_pf), + .I3(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .I4(almost_full), .O(ram_afull_i0)); LUT6 #( - .INIT(64'h00000000F020FF20)) + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4 + (.I0(Q[9]), + .I1(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [9]), + .I2(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [11]), + .I3(Q[11]), + .I4(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [10]), + .I5(Q[10]), + .O(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5 + (.I0(Q[6]), + .I1(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [6]), + .I2(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [8]), + .I3(Q[8]), + .I4(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [7]), + .I5(Q[7]), + .O(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6 + (.I0(Q[3]), + .I1(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [3]), + .I2(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [5]), + .I3(Q[5]), + .I4(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [4]), + .I5(Q[4]), + .O(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7 + (.I0(Q[0]), + .I1(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [0]), + .I2(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [2]), + .I3(Q[2]), + .I4(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 [1]), + .I5(Q[1]), + .O(\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0 )); + CARRY4 \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3 + (.CI(1'b0), + .CO({going_afull1,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_1 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED [3:0]), + .S({\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0 ,\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0 })); + LUT6 #( + .INIT(64'h0545044404440444)) \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_1 - (.I0(going_full1), + (.I0(clr_full), .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg ), .I2(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0 ), - .I4(CO), - .I5(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1 ), + .I3(CO), + .I4(going_full1), + .I5(ram_wr_en_pf), .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 )); LUT6 #( - .INIT(64'hFFFFFFFF0FDF00DF)) + .INIT(64'hFABAFBBBFBBBFBBB)) \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_1 - (.I0(going_full1), + (.I0(clr_full), .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg ), .I2(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0 ), - .I4(CO), - .I5(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1 ), + .I3(CO), + .I4(going_full1), + .I5(ram_wr_en_pf), .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg )); - LUT4 #( - .INIT(16'hF0F4)) - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_4 - (.I0(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2 [0]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2 [1]), - .I2(ram_empty_i), - .I3(rd_en), - .O(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10 + (.I0(Q[6]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [6]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [8]), + .I3(Q[8]), + .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [7]), + .I5(Q[7]), + .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11 + (.I0(Q[3]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [3]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [5]), + .I3(Q[5]), + .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [4]), + .I5(Q[4]), + .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12 + (.I0(Q[0]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [0]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [2]), + .I3(Q[2]), + .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [1]), + .I5(Q[1]), + .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5 + (.I0(Q[9]), + .I1(\grdc.rd_data_count_i_reg[12] [9]), + .I2(\grdc.rd_data_count_i_reg[12] [11]), + .I3(Q[11]), + .I4(\grdc.rd_data_count_i_reg[12] [10]), + .I5(Q[10]), + .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6 + (.I0(Q[6]), + .I1(\grdc.rd_data_count_i_reg[12] [6]), + .I2(\grdc.rd_data_count_i_reg[12] [8]), + .I3(Q[8]), + .I4(\grdc.rd_data_count_i_reg[12] [7]), + .I5(Q[7]), + .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7 - (.I0(Q[6]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [6]), - .I2(Q[7]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [7]), - .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [8]), - .I5(Q[8]), + (.I0(Q[3]), + .I1(\grdc.rd_data_count_i_reg[12] [3]), + .I2(\grdc.rd_data_count_i_reg[12] [5]), + .I3(Q[5]), + .I4(\grdc.rd_data_count_i_reg[12] [4]), + .I5(Q[4]), .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8 - (.I0(Q[4]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [4]), - .I2(Q[3]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [3]), - .I4(Q[5]), - .I5(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [5]), + (.I0(Q[0]), + .I1(\grdc.rd_data_count_i_reg[12] [0]), + .I2(\grdc.rd_data_count_i_reg[12] [2]), + .I3(Q[2]), + .I4(\grdc.rd_data_count_i_reg[12] [1]), + .I5(Q[1]), .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9 - (.I0(Q[2]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [2]), - .I2(Q[1]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [1]), - .I4(Q[0]), - .I5(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [0]), + (.I0(Q[9]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [9]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [11]), + .I3(Q[11]), + .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [10]), + .I5(Q[10]), .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0 )); - CARRY4 \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2 + CARRY4 \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3 (.CI(1'b0), - .CO({\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_CO_UNCONNECTED [3],going_full1,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_2 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_3 }), + .CO({CO,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_1 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_2 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_3 }), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_O_UNCONNECTED [3:0]), - .S({1'b0,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0 })); - LUT1 #( - .INIT(2'h1)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2 - (.I0(Q[3]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2_n_0 )); - LUT1 #( - .INIT(2'h1)) + .O(\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_O_UNCONNECTED [3:0]), + .S({\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0 })); + CARRY4 \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4 + (.CI(1'b0), + .CO({going_full1,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_1 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_2 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_O_UNCONNECTED [3:0]), + .S({\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0 })); + LUT2 #( + .INIT(4'h9)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_2 + (.I0(Q[11]), + .I1(\grdc.rd_data_count_i_reg[12] [11]), + .O(\count_value_i_reg[11]_1 [3])); + LUT2 #( + .INIT(4'h9)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_3 + (.I0(Q[10]), + .I1(\grdc.rd_data_count_i_reg[12] [10]), + .O(\count_value_i_reg[11]_1 [2])); + LUT2 #( + .INIT(4'h9)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_4 + (.I0(Q[9]), + .I1(\grdc.rd_data_count_i_reg[12] [9]), + .O(\count_value_i_reg[11]_1 [1])); + LUT2 #( + .INIT(4'h9)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_5 + (.I0(Q[8]), + .I1(\grdc.rd_data_count_i_reg[12] [8]), + .O(\count_value_i_reg[11]_1 [0])); + LUT2 #( + .INIT(4'h9)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3 - (.I0(Q[2]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3_n_0 )); - LUT1 #( - .INIT(2'h1)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4 - (.I0(Q[1]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4_n_0 )); - LUT1 #( - .INIT(2'h1)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5 - (.I0(Q[0]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6 (.I0(Q[3]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [3]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6_n_0 )); + .I1(\grdc.rd_data_count_i_reg[12] [3]), + .O(\count_value_i_reg[3]_0 [2])); LUT2 #( .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7 + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4 (.I0(Q[2]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [2]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7_n_0 )); + .I1(\grdc.rd_data_count_i_reg[12] [2]), + .O(\count_value_i_reg[3]_0 [1])); LUT2 #( .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8 + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5 (.I0(Q[1]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [1]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8_n_0 )); - LUT1 #( - .INIT(2'h1)) + .I1(\grdc.rd_data_count_i_reg[12] [1]), + .O(\count_value_i_reg[3]_0 [0])); + LUT2 #( + .INIT(4'h9)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2 (.I0(Q[7]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2_n_0 )); - LUT1 #( - .INIT(2'h1)) + .I1(\grdc.rd_data_count_i_reg[12] [7]), + .O(\count_value_i_reg[7]_0 [3])); + LUT2 #( + .INIT(4'h9)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3 (.I0(Q[6]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3_n_0 )); - LUT1 #( - .INIT(2'h1)) + .I1(\grdc.rd_data_count_i_reg[12] [6]), + .O(\count_value_i_reg[7]_0 [2])); + LUT2 #( + .INIT(4'h9)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4 (.I0(Q[5]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4_n_0 )); - LUT1 #( - .INIT(2'h1)) + .I1(\grdc.rd_data_count_i_reg[12] [5]), + .O(\count_value_i_reg[7]_0 [1])); + LUT2 #( + .INIT(4'h9)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5 (.I0(Q[4]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6 - (.I0(Q[7]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [7]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7 - (.I0(Q[6]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [6]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8 - (.I0(Q[5]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [5]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9 - (.I0(Q[4]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [4]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9_n_0 )); - (* ADDER_THRESHOLD = "35" *) - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1 - (.CI(1'b0), - .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3 }), - .CYINIT(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] [0]), - .DI({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5_n_0 }), - .O(\count_value_i_reg[8]_0 [3:0]), - .S({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] })); - (* ADDER_THRESHOLD = "35" *) - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1 - (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0 ), - .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5_n_0 }), - .O(\count_value_i_reg[8]_0 [7:4]), - .S({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9_n_0 })); - (* ADDER_THRESHOLD = "35" *) - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1 - (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0 ), - .CO(\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED [3:0]), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED [3:1],\count_value_i_reg[8]_0 [8]}), - .S({1'b0,1'b0,1'b0,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8] })); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2 - (.I0(Q[3]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [3]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3 - (.I0(Q[2]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [2]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0 )); - LUT2 #( - .INIT(4'h9)) + .I1(\grdc.rd_data_count_i_reg[12] [4]), + .O(\count_value_i_reg[7]_0 [0])); + LUT4 #( + .INIT(16'hB44B)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_5 + (.I0(Q[10]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [10]), + .I2(Q[11]), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [11]), + .O(S)); + LUT4 #( + .INIT(16'h7510)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4 - (.I0(Q[1]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [1]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5 - (.I0(Q[3]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [3]), - .I2(Q[2]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [2]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6 - (.I0(Q[2]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [2]), - .I2(Q[1]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [1]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0 )); + (.I0(Q[0]), + .I1(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .I2(ram_wr_en_pf), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [0]), + .O(DI)); LUT6 #( - .INIT(64'h9699999966669699)) + .INIT(64'h8AEF751075108AEF)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7 - (.I0(Q[1]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [1]), - .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg ), - .I3(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [0]), - .I5(Q[0]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2 - (.I0(Q[7]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [7]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3 - (.I0(Q[6]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [6]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4 - (.I0(Q[5]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [5]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5 - (.I0(Q[4]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [4]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0 )); + (.I0(Q[0]), + .I1(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), + .I2(ram_wr_en_pf), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [0]), + .I4(Q[1]), + .I5(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] [1]), + .O(\count_value_i_reg[0]_0 )); LUT4 #( - .INIT(16'h9699)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6 - (.I0(Q[7]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [7]), - .I2(Q[6]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [6]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7 - (.I0(Q[6]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [6]), - .I2(Q[5]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [5]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8 - (.I0(Q[5]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [5]), - .I2(Q[4]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [4]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9 - (.I0(Q[4]), - .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [4]), - .I2(Q[3]), - .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 [3]), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0 )); - (* ADDER_THRESHOLD = "35" *) - CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1 - (.CI(1'b0), - .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4_n_0 ,1'b0}), - .O(D[3:0]), - .S({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7_n_0 ,S})); - (* ADDER_THRESHOLD = "35" *) - CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1 - (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0 ), - .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0 }), - .O(D[7:4]), - .S({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0 })); - (* ADDER_THRESHOLD = "35" *) - CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1 - (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0 ), - .CO(\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED [3:0]), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED [3:1],D[8]}), - .S({1'b0,1'b0,1'b0,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] })); - LUT1 #( - .INIT(2'h1)) + .INIT(16'h00FB)) \gen_sdpram.xpm_memory_base_inst_i_2 - (.I0(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] ), - .O(E)); + (.I0(\count_value_i_reg[0]_1 [0]), + .I1(\count_value_i_reg[0]_1 [1]), + .I2(rd_en), + .I3(ram_empty_i), + .O(\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] )); + LUT4 #( + .INIT(16'hB44B)) + \gwdc.wr_data_count_i[12]_i_2 + (.I0(Q[11]), + .I1(\grdc.rd_data_count_i_reg[12] [11]), + .I2(\count_value_i_reg_n_0_[12] ), + .I3(\grdc.rd_data_count_i_reg[12] [12]), + .O(\count_value_i_reg[11]_0 )); + LUT3 #( + .INIT(8'hD4)) + \gwdc.wr_data_count_i[3]_i_3 + (.I0(Q[1]), + .I1(\grdc.rd_data_count_i_reg[3] ), + .I2(\grdc.rd_data_count_i_reg[12] [1]), + .O(\count_value_i_reg[1]_0 )); + LUT5 #( + .INIT(32'h2BD4D42B)) + \gwdc.wr_data_count_i[3]_i_6 + (.I0(Q[1]), + .I1(\grdc.rd_data_count_i_reg[3] ), + .I2(\grdc.rd_data_count_i_reg[12] [1]), + .I3(Q[2]), + .I4(\grdc.rd_data_count_i_reg[12] [2]), + .O(\count_value_i_reg[1]_1 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0 (ram_empty_i0, - CO, Q, D, - \count_value_i_reg[8]_0 , - ram_empty_i, + \count_value_i_reg[10]_0 , \gen_pntr_flags_cc.ram_empty_i_reg , - \gen_pntr_flags_cc.ram_empty_i_reg_0 , - \gen_pntr_flags_cc.ram_empty_i_reg_1 , - \grdc.rd_data_count_i_reg[9] , - DI, + CO, + ram_wr_en_pf, + ram_empty_i, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 , S, + DI, \grdc.rd_data_count_i_reg[3] , - \count_value_i_reg[9]_0 , - E, + \grdc.rd_data_count_i_reg[12] , + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] , + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0 , + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] , + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11] , + \grdc.rd_data_count_i_reg[11] , + \count_value_i_reg[12]_0 , wr_clk); output ram_empty_i0; - output [0:0]CO; - output [8:0]Q; - output [9:0]D; - output [0:0]\count_value_i_reg[8]_0 ; - input ram_empty_i; + output [12:0]Q; + output [12:0]D; + output [11:0]\count_value_i_reg[10]_0 ; input \gen_pntr_flags_cc.ram_empty_i_reg ; - input \gen_pntr_flags_cc.ram_empty_i_reg_0 ; - input [0:0]\gen_pntr_flags_cc.ram_empty_i_reg_1 ; - input [9:0]\grdc.rd_data_count_i_reg[9] ; - input [0:0]DI; - input [1:0]S; - input [0:0]\grdc.rd_data_count_i_reg[3] ; - input [0:0]\count_value_i_reg[9]_0 ; - input [0:0]E; + input [0:0]CO; + input ram_wr_en_pf; + input ram_empty_i; + input [11:0]\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 ; + input [0:0]S; + input [1:0]DI; + input [2:0]\grdc.rd_data_count_i_reg[3] ; + input [0:0]\grdc.rd_data_count_i_reg[12] ; + input [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ; + input [3:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0 ; + input [3:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] ; + input [3:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11] ; + input [9:0]\grdc.rd_data_count_i_reg[11] ; + input [0:0]\count_value_i_reg[12]_0 ; input wr_clk; wire [0:0]CO; - wire [9:0]D; - wire [0:0]DI; - wire [0:0]E; - wire [8:0]Q; - wire [1:0]S; - wire \count_value_i[0]_i_1__1_n_0 ; - wire \count_value_i[1]_i_1__3_n_0 ; - wire \count_value_i[2]_i_1__3_n_0 ; - wire \count_value_i[3]_i_1__3_n_0 ; - wire \count_value_i[4]_i_1__3_n_0 ; - wire \count_value_i[5]_i_1__3_n_0 ; - wire \count_value_i[6]_i_1__3_n_0 ; - wire \count_value_i[7]_i_1__3_n_0 ; - wire \count_value_i[8]_i_1__1_n_0 ; - wire \count_value_i[9]_i_1__0_n_0 ; - wire \count_value_i[9]_i_2__0_n_0 ; - wire [0:0]\count_value_i_reg[8]_0 ; - wire [0:0]\count_value_i_reg[9]_0 ; - wire \count_value_i_reg_n_0_[9] ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0 ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0 ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0 ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_2 ; - wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_3 ; + wire [12:0]D; + wire [1:0]DI; + wire [12:0]Q; + wire [0:0]S; + wire [11:0]\count_value_i_reg[10]_0 ; + wire \count_value_i_reg[11]_i_1_n_0 ; + wire \count_value_i_reg[11]_i_1_n_1 ; + wire \count_value_i_reg[11]_i_1_n_2 ; + wire \count_value_i_reg[11]_i_1_n_3 ; + wire \count_value_i_reg[11]_i_1_n_4 ; + wire \count_value_i_reg[11]_i_1_n_5 ; + wire \count_value_i_reg[11]_i_1_n_6 ; + wire \count_value_i_reg[11]_i_1_n_7 ; + wire [0:0]\count_value_i_reg[12]_0 ; + wire \count_value_i_reg[12]_i_1_n_7 ; + wire \count_value_i_reg[3]_i_1_n_0 ; + wire \count_value_i_reg[3]_i_1_n_1 ; + wire \count_value_i_reg[3]_i_1_n_2 ; + wire \count_value_i_reg[3]_i_1_n_3 ; + wire \count_value_i_reg[3]_i_1_n_4 ; + wire \count_value_i_reg[3]_i_1_n_5 ; + wire \count_value_i_reg[3]_i_1_n_6 ; + wire \count_value_i_reg[3]_i_1_n_7 ; + wire \count_value_i_reg[7]_i_1_n_0 ; + wire \count_value_i_reg[7]_i_1_n_1 ; + wire \count_value_i_reg[7]_i_1_n_2 ; + wire \count_value_i_reg[7]_i_1_n_3 ; + wire \count_value_i_reg[7]_i_1_n_4 ; + wire \count_value_i_reg[7]_i_1_n_5 ; + wire \count_value_i_reg[7]_i_1_n_6 ; + wire \count_value_i_reg[7]_i_1_n_7 ; + wire \gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ; + wire \gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ; + wire \gen_pntr_flags_cc.ram_empty_i_i_5_n_0 ; + wire \gen_pntr_flags_cc.ram_empty_i_i_6_n_0 ; wire \gen_pntr_flags_cc.ram_empty_i_reg ; - wire \gen_pntr_flags_cc.ram_empty_i_reg_0 ; - wire [0:0]\gen_pntr_flags_cc.ram_empty_i_reg_1 ; - wire [0:0]\grdc.rd_data_count_i_reg[3] ; - wire [9:0]\grdc.rd_data_count_i_reg[9] ; + wire [11:0]\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 ; + wire \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_1 ; + wire \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2 ; + wire \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3 ; + wire [3:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11] ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_1 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_2 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_3 ; + wire [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ; + wire [3:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3 ; + wire [3:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3 ; + wire going_empty1; + wire [9:0]\grdc.rd_data_count_i_reg[11] ; + wire [0:0]\grdc.rd_data_count_i_reg[12] ; + wire [2:0]\grdc.rd_data_count_i_reg[3] ; + wire \gwdc.wr_data_count_i[11]_i_2_n_0 ; + wire \gwdc.wr_data_count_i[11]_i_3_n_0 ; + wire \gwdc.wr_data_count_i[11]_i_4_n_0 ; + wire \gwdc.wr_data_count_i[11]_i_5_n_0 ; + wire \gwdc.wr_data_count_i[11]_i_6_n_0 ; + wire \gwdc.wr_data_count_i[11]_i_7_n_0 ; + wire \gwdc.wr_data_count_i[11]_i_8_n_0 ; + wire \gwdc.wr_data_count_i[11]_i_9_n_0 ; wire \gwdc.wr_data_count_i[3]_i_2_n_0 ; - wire \gwdc.wr_data_count_i[3]_i_3_n_0 ; wire \gwdc.wr_data_count_i[3]_i_5_n_0 ; - wire \gwdc.wr_data_count_i[3]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; @@ -6524,9 +6495,10 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0 wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; - wire \gwdc.wr_data_count_i[9]_i_2_n_0 ; - wire \gwdc.wr_data_count_i[9]_i_3_n_0 ; - wire \gwdc.wr_data_count_i[9]_i_4_n_0 ; + wire \gwdc.wr_data_count_i_reg[11]_i_1_n_0 ; + wire \gwdc.wr_data_count_i_reg[11]_i_1_n_1 ; + wire \gwdc.wr_data_count_i_reg[11]_i_1_n_2 ; + wire \gwdc.wr_data_count_i_reg[11]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[3]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[3]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[3]_i_1_n_2 ; @@ -6535,358 +6507,386 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0 wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; - wire \gwdc.wr_data_count_i_reg[9]_i_1_n_3 ; wire ram_empty_i; wire ram_empty_i0; + wire ram_wr_en_pf; wire wr_clk; - wire [3:3]\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_CO_UNCONNECTED ; - wire [3:0]\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_O_UNCONNECTED ; - wire [3:1]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED ; - wire [3:2]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED ; + wire [3:0]\NLW_count_value_i_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_count_value_i_reg[12]_i_1_O_UNCONNECTED ; + wire [3:0]\NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED ; + wire [3:3]\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_gwdc.wr_data_count_i_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_gwdc.wr_data_count_i_reg[12]_i_1_O_UNCONNECTED ; - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT1 #( - .INIT(2'h1)) - \count_value_i[0]_i_1__1 - (.I0(Q[0]), - .O(\count_value_i[0]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT2 #( - .INIT(4'h6)) - \count_value_i[1]_i_1__3 - (.I0(Q[1]), - .I1(Q[0]), - .O(\count_value_i[1]_i_1__3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT4 #( - .INIT(16'hDF20)) - \count_value_i[2]_i_1__3 - (.I0(Q[0]), - .I1(\gen_pntr_flags_cc.ram_empty_i_reg_0 ), - .I2(Q[1]), - .I3(Q[2]), - .O(\count_value_i[2]_i_1__3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT5 #( - .INIT(32'hDF20FF00)) - \count_value_i[3]_i_1__3 - (.I0(Q[0]), - .I1(\gen_pntr_flags_cc.ram_empty_i_reg_0 ), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[2]), - .O(\count_value_i[3]_i_1__3_n_0 )); - LUT6 #( - .INIT(64'hDF20FF00FF00FF00)) - \count_value_i[4]_i_1__3 - (.I0(Q[0]), - .I1(\gen_pntr_flags_cc.ram_empty_i_reg_0 ), - .I2(Q[1]), - .I3(Q[4]), - .I4(Q[3]), - .I5(Q[2]), - .O(\count_value_i[4]_i_1__3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT2 #( - .INIT(4'h9)) - \count_value_i[5]_i_1__3 - (.I0(Q[5]), - .I1(\count_value_i[9]_i_2__0_n_0 ), - .O(\count_value_i[5]_i_1__3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'hA6)) - \count_value_i[6]_i_1__3 - (.I0(Q[6]), - .I1(Q[5]), - .I2(\count_value_i[9]_i_2__0_n_0 ), - .O(\count_value_i[6]_i_1__3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT4 #( - .INIT(16'hA6AA)) - \count_value_i[7]_i_1__3 - (.I0(Q[7]), - .I1(Q[6]), - .I2(\count_value_i[9]_i_2__0_n_0 ), - .I3(Q[5]), - .O(\count_value_i[7]_i_1__3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT5 #( - .INIT(32'hA6AAAAAA)) - \count_value_i[8]_i_1__1 - (.I0(Q[8]), - .I1(Q[5]), - .I2(\count_value_i[9]_i_2__0_n_0 ), - .I3(Q[6]), - .I4(Q[7]), - .O(\count_value_i[8]_i_1__1_n_0 )); - LUT6 #( - .INIT(64'hAA6AAAAAAAAAAAAA)) - \count_value_i[9]_i_1__0 - (.I0(\count_value_i_reg_n_0_[9] ), - .I1(Q[7]), - .I2(Q[6]), - .I3(\count_value_i[9]_i_2__0_n_0 ), - .I4(Q[5]), - .I5(Q[8]), - .O(\count_value_i[9]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'hDFFFFFFFFFFFFFFF)) - \count_value_i[9]_i_2__0 - (.I0(Q[0]), - .I1(\gen_pntr_flags_cc.ram_empty_i_reg_0 ), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[2]), - .I5(Q[4]), - .O(\count_value_i[9]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), - .CE(E), - .D(\count_value_i[0]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1_n_7 ), .Q(Q[0]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[10] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1_n_5 ), + .Q(Q[10]), + .R(\count_value_i_reg[12]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[11] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1_n_4 ), + .Q(Q[11]), + .R(\count_value_i_reg[12]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[11]_i_1 + (.CI(\count_value_i_reg[7]_i_1_n_0 ), + .CO({\count_value_i_reg[11]_i_1_n_0 ,\count_value_i_reg[11]_i_1_n_1 ,\count_value_i_reg[11]_i_1_n_2 ,\count_value_i_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[11]_i_1_n_4 ,\count_value_i_reg[11]_i_1_n_5 ,\count_value_i_reg[11]_i_1_n_6 ,\count_value_i_reg[11]_i_1_n_7 }), + .S(Q[11:8])); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[12] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[12]_i_1_n_7 ), + .Q(Q[12]), + .R(\count_value_i_reg[12]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[12]_i_1 + (.CI(\count_value_i_reg[11]_i_1_n_0 ), + .CO(\NLW_count_value_i_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_count_value_i_reg[12]_i_1_O_UNCONNECTED [3:1],\count_value_i_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,Q[12]})); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), - .CE(E), - .D(\count_value_i[1]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1_n_6 ), .Q(Q[1]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), - .CE(E), - .D(\count_value_i[2]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1_n_5 ), .Q(Q[2]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), - .CE(E), - .D(\count_value_i[3]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1_n_4 ), .Q(Q[3]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[3]_i_1 + (.CI(1'b0), + .CO({\count_value_i_reg[3]_i_1_n_0 ,\count_value_i_reg[3]_i_1_n_1 ,\count_value_i_reg[3]_i_1_n_2 ,\count_value_i_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[0]}), + .O({\count_value_i_reg[3]_i_1_n_4 ,\count_value_i_reg[3]_i_1_n_5 ,\count_value_i_reg[3]_i_1_n_6 ,\count_value_i_reg[3]_i_1_n_7 }), + .S({Q[3:1],S})); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), - .CE(E), - .D(\count_value_i[4]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1_n_7 ), .Q(Q[4]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), - .CE(E), - .D(\count_value_i[5]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1_n_6 ), .Q(Q[5]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), - .CE(E), - .D(\count_value_i[6]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1_n_5 ), .Q(Q[6]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), - .CE(E), - .D(\count_value_i[7]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1_n_4 ), .Q(Q[7]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[7]_i_1 + (.CI(\count_value_i_reg[3]_i_1_n_0 ), + .CO({\count_value_i_reg[7]_i_1_n_0 ,\count_value_i_reg[7]_i_1_n_1 ,\count_value_i_reg[7]_i_1_n_2 ,\count_value_i_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[7]_i_1_n_4 ,\count_value_i_reg[7]_i_1_n_5 ,\count_value_i_reg[7]_i_1_n_6 ,\count_value_i_reg[7]_i_1_n_7 }), + .S(Q[7:4])); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), - .CE(E), - .D(\count_value_i[8]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1_n_7 ), .Q(Q[8]), - .R(\count_value_i_reg[9]_0 )); + .R(\count_value_i_reg[12]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(wr_clk), - .CE(E), - .D(\count_value_i[9]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[9] ), - .R(\count_value_i_reg[9]_0 )); + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1_n_6 ), + .Q(Q[9]), + .R(\count_value_i_reg[12]_0 )); + LUT5 #( + .INIT(32'h0FFF0088)) + \gen_pntr_flags_cc.ram_empty_i_i_1 + (.I0(\gen_pntr_flags_cc.ram_empty_i_reg ), + .I1(going_empty1), + .I2(CO), + .I3(ram_wr_en_pf), + .I4(ram_empty_i), + .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10 - (.I0(Q[7]), - .I1(\grdc.rd_data_count_i_reg[9] [7]), - .I2(Q[6]), - .I3(\grdc.rd_data_count_i_reg[9] [6]), - .I4(Q[8]), - .I5(\grdc.rd_data_count_i_reg[9] [8]), - .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0 )); + \gen_pntr_flags_cc.ram_empty_i_i_3 + (.I0(Q[9]), + .I1(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [9]), + .I2(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [11]), + .I3(Q[11]), + .I4(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [10]), + .I5(Q[10]), + .O(\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11 - (.I0(Q[5]), - .I1(\grdc.rd_data_count_i_reg[9] [5]), - .I2(Q[3]), - .I3(\grdc.rd_data_count_i_reg[9] [3]), - .I4(Q[4]), - .I5(\grdc.rd_data_count_i_reg[9] [4]), - .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0 )); + \gen_pntr_flags_cc.ram_empty_i_i_4 + (.I0(Q[6]), + .I1(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [6]), + .I2(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [8]), + .I3(Q[8]), + .I4(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [7]), + .I5(Q[7]), + .O(\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12 - (.I0(Q[2]), - .I1(\grdc.rd_data_count_i_reg[9] [2]), - .I2(\grdc.rd_data_count_i_reg[9] [1]), - .I3(Q[1]), - .I4(Q[0]), - .I5(\grdc.rd_data_count_i_reg[9] [0]), - .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0 )); - CARRY4 \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5 + \gen_pntr_flags_cc.ram_empty_i_i_5 + (.I0(Q[3]), + .I1(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [3]), + .I2(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [5]), + .I3(Q[5]), + .I4(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [4]), + .I5(Q[4]), + .O(\gen_pntr_flags_cc.ram_empty_i_i_5_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \gen_pntr_flags_cc.ram_empty_i_i_6 + (.I0(Q[0]), + .I1(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [0]), + .I2(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [2]), + .I3(Q[2]), + .I4(\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 [1]), + .I5(Q[1]), + .O(\gen_pntr_flags_cc.ram_empty_i_i_6_n_0 )); + CARRY4 \gen_pntr_flags_cc.ram_empty_i_reg_i_2 (.CI(1'b0), - .CO({\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_CO_UNCONNECTED [3],CO,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_2 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_3 }), + .CO({going_empty1,\gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_1 ,\gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2 ,\gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3 }), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_O_UNCONNECTED [3:0]), - .S({1'b0,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0 ,\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0 })); - LUT5 #( - .INIT(32'hCF44CC44)) - \gen_pntr_flags_cc.ram_empty_i_i_1 - (.I0(CO), - .I1(ram_empty_i), - .I2(\gen_pntr_flags_cc.ram_empty_i_reg ), - .I3(\gen_pntr_flags_cc.ram_empty_i_reg_0 ), - .I4(\gen_pntr_flags_cc.ram_empty_i_reg_1 ), - .O(ram_empty_i0)); + .O(\NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED [3:0]), + .S({\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ,\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ,\gen_pntr_flags_cc.ram_empty_i_i_5_n_0 ,\gen_pntr_flags_cc.ram_empty_i_i_6_n_0 })); + (* ADDER_THRESHOLD = "35" *) + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1 + (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0 ), + .CO({\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_CO_UNCONNECTED [3],\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,Q[10:8]}), + .O(\count_value_i_reg[10]_0 [11:8]), + .S(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11] )); + (* ADDER_THRESHOLD = "35" *) + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1 + (.CI(1'b0), + .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3 }), + .CYINIT(Q[0]), + .DI({Q[3:1],\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] }), + .O(\count_value_i_reg[10]_0 [3:0]), + .S(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0 )); + (* ADDER_THRESHOLD = "35" *) + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1 + (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0 ), + .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(Q[7:4]), + .O(\count_value_i_reg[10]_0 [7:4]), + .S(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] )); LUT2 #( - .INIT(4'h9)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[8]_i_2 + .INIT(4'h2)) + \gwdc.wr_data_count_i[11]_i_2 + (.I0(Q[10]), + .I1(\grdc.rd_data_count_i_reg[11] [8]), + .O(\gwdc.wr_data_count_i[11]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gwdc.wr_data_count_i[11]_i_3 + (.I0(Q[9]), + .I1(\grdc.rd_data_count_i_reg[11] [7]), + .O(\gwdc.wr_data_count_i[11]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gwdc.wr_data_count_i[11]_i_4 (.I0(Q[8]), - .I1(\grdc.rd_data_count_i_reg[9] [8]), - .O(\count_value_i_reg[8]_0 )); + .I1(\grdc.rd_data_count_i_reg[11] [6]), + .O(\gwdc.wr_data_count_i[11]_i_4_n_0 )); LUT2 #( - .INIT(4'h9)) - \gwdc.wr_data_count_i[3]_i_2 - (.I0(Q[3]), - .I1(\grdc.rd_data_count_i_reg[9] [3]), - .O(\gwdc.wr_data_count_i[3]_i_2_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gwdc.wr_data_count_i[3]_i_3 - (.I0(Q[2]), - .I1(\grdc.rd_data_count_i_reg[9] [2]), - .O(\gwdc.wr_data_count_i[3]_i_3_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gwdc.wr_data_count_i[3]_i_5 - (.I0(Q[3]), - .I1(\grdc.rd_data_count_i_reg[9] [3]), - .I2(\grdc.rd_data_count_i_reg[9] [2]), - .I3(Q[2]), - .O(\gwdc.wr_data_count_i[3]_i_5_n_0 )); - LUT5 #( - .INIT(32'h69669969)) - \gwdc.wr_data_count_i[3]_i_6 - (.I0(Q[2]), - .I1(\grdc.rd_data_count_i_reg[9] [2]), - .I2(Q[1]), - .I3(\grdc.rd_data_count_i_reg[9] [1]), - .I4(\grdc.rd_data_count_i_reg[3] ), - .O(\gwdc.wr_data_count_i[3]_i_6_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gwdc.wr_data_count_i[7]_i_2 + .INIT(4'h2)) + \gwdc.wr_data_count_i[11]_i_5 (.I0(Q[7]), - .I1(\grdc.rd_data_count_i_reg[9] [7]), - .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gwdc.wr_data_count_i[7]_i_3 - (.I0(Q[6]), - .I1(\grdc.rd_data_count_i_reg[9] [6]), - .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gwdc.wr_data_count_i[7]_i_4 - (.I0(Q[5]), - .I1(\grdc.rd_data_count_i_reg[9] [5]), - .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gwdc.wr_data_count_i[7]_i_5 - (.I0(Q[4]), - .I1(\grdc.rd_data_count_i_reg[9] [4]), - .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gwdc.wr_data_count_i[7]_i_6 - (.I0(Q[7]), - .I1(\grdc.rd_data_count_i_reg[9] [7]), - .I2(\grdc.rd_data_count_i_reg[9] [6]), - .I3(Q[6]), - .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gwdc.wr_data_count_i[7]_i_7 - (.I0(Q[6]), - .I1(\grdc.rd_data_count_i_reg[9] [6]), - .I2(\grdc.rd_data_count_i_reg[9] [5]), - .I3(Q[5]), - .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gwdc.wr_data_count_i[7]_i_8 - (.I0(Q[5]), - .I1(\grdc.rd_data_count_i_reg[9] [5]), - .I2(\grdc.rd_data_count_i_reg[9] [4]), - .I3(Q[4]), - .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); - LUT4 #( - .INIT(16'h9699)) - \gwdc.wr_data_count_i[7]_i_9 - (.I0(Q[4]), - .I1(\grdc.rd_data_count_i_reg[9] [4]), - .I2(\grdc.rd_data_count_i_reg[9] [3]), - .I3(Q[3]), - .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); - LUT2 #( - .INIT(4'h9)) - \gwdc.wr_data_count_i[9]_i_2 - (.I0(Q[8]), - .I1(\grdc.rd_data_count_i_reg[9] [8]), - .O(\gwdc.wr_data_count_i[9]_i_2_n_0 )); + .I1(\grdc.rd_data_count_i_reg[11] [5]), + .O(\gwdc.wr_data_count_i[11]_i_5_n_0 )); LUT4 #( .INIT(16'hD22D)) - \gwdc.wr_data_count_i[9]_i_3 - (.I0(Q[8]), - .I1(\grdc.rd_data_count_i_reg[9] [8]), - .I2(\count_value_i_reg_n_0_[9] ), - .I3(\grdc.rd_data_count_i_reg[9] [9]), - .O(\gwdc.wr_data_count_i[9]_i_3_n_0 )); + \gwdc.wr_data_count_i[11]_i_6 + (.I0(Q[10]), + .I1(\grdc.rd_data_count_i_reg[11] [8]), + .I2(\grdc.rd_data_count_i_reg[11] [9]), + .I3(Q[11]), + .O(\gwdc.wr_data_count_i[11]_i_6_n_0 )); LUT4 #( - .INIT(16'h9699)) - \gwdc.wr_data_count_i[9]_i_4 + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[11]_i_7 + (.I0(Q[9]), + .I1(\grdc.rd_data_count_i_reg[11] [7]), + .I2(\grdc.rd_data_count_i_reg[11] [8]), + .I3(Q[10]), + .O(\gwdc.wr_data_count_i[11]_i_7_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[11]_i_8 (.I0(Q[8]), - .I1(\grdc.rd_data_count_i_reg[9] [8]), - .I2(\grdc.rd_data_count_i_reg[9] [7]), + .I1(\grdc.rd_data_count_i_reg[11] [6]), + .I2(\grdc.rd_data_count_i_reg[11] [7]), + .I3(Q[9]), + .O(\gwdc.wr_data_count_i[11]_i_8_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[11]_i_9 + (.I0(Q[7]), + .I1(\grdc.rd_data_count_i_reg[11] [5]), + .I2(\grdc.rd_data_count_i_reg[11] [6]), + .I3(Q[8]), + .O(\gwdc.wr_data_count_i[11]_i_9_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gwdc.wr_data_count_i[3]_i_2 + (.I0(Q[2]), + .I1(\grdc.rd_data_count_i_reg[11] [0]), + .O(\gwdc.wr_data_count_i[3]_i_2_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[3]_i_5 + (.I0(Q[2]), + .I1(\grdc.rd_data_count_i_reg[11] [0]), + .I2(\grdc.rd_data_count_i_reg[11] [1]), + .I3(Q[3]), + .O(\gwdc.wr_data_count_i[3]_i_5_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gwdc.wr_data_count_i[7]_i_2 + (.I0(Q[6]), + .I1(\grdc.rd_data_count_i_reg[11] [4]), + .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gwdc.wr_data_count_i[7]_i_3 + (.I0(Q[5]), + .I1(\grdc.rd_data_count_i_reg[11] [3]), + .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gwdc.wr_data_count_i[7]_i_4 + (.I0(Q[4]), + .I1(\grdc.rd_data_count_i_reg[11] [2]), + .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gwdc.wr_data_count_i[7]_i_5 + (.I0(Q[3]), + .I1(\grdc.rd_data_count_i_reg[11] [1]), + .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[7]_i_6 + (.I0(Q[6]), + .I1(\grdc.rd_data_count_i_reg[11] [4]), + .I2(\grdc.rd_data_count_i_reg[11] [5]), .I3(Q[7]), - .O(\gwdc.wr_data_count_i[9]_i_4_n_0 )); + .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[7]_i_7 + (.I0(Q[5]), + .I1(\grdc.rd_data_count_i_reg[11] [3]), + .I2(\grdc.rd_data_count_i_reg[11] [4]), + .I3(Q[6]), + .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[7]_i_8 + (.I0(Q[4]), + .I1(\grdc.rd_data_count_i_reg[11] [2]), + .I2(\grdc.rd_data_count_i_reg[11] [3]), + .I3(Q[5]), + .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gwdc.wr_data_count_i[7]_i_9 + (.I0(Q[3]), + .I1(\grdc.rd_data_count_i_reg[11] [1]), + .I2(\grdc.rd_data_count_i_reg[11] [2]), + .I3(Q[4]), + .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \gwdc.wr_data_count_i_reg[11]_i_1 + (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), + .CO({\gwdc.wr_data_count_i_reg[11]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[11]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[11]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\gwdc.wr_data_count_i[11]_i_2_n_0 ,\gwdc.wr_data_count_i[11]_i_3_n_0 ,\gwdc.wr_data_count_i[11]_i_4_n_0 ,\gwdc.wr_data_count_i[11]_i_5_n_0 }), + .O(D[11:8]), + .S({\gwdc.wr_data_count_i[11]_i_6_n_0 ,\gwdc.wr_data_count_i[11]_i_7_n_0 ,\gwdc.wr_data_count_i[11]_i_8_n_0 ,\gwdc.wr_data_count_i[11]_i_9_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \gwdc.wr_data_count_i_reg[12]_i_1 + (.CI(\gwdc.wr_data_count_i_reg[11]_i_1_n_0 ), + .CO(\NLW_gwdc.wr_data_count_i_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_gwdc.wr_data_count_i_reg[12]_i_1_O_UNCONNECTED [3:1],D[12]}), + .S({1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[12] })); (* ADDER_THRESHOLD = "35" *) CARRY4 \gwdc.wr_data_count_i_reg[3]_i_1 (.CI(1'b0), .CO({\gwdc.wr_data_count_i_reg[3]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_3 }), .CYINIT(1'b0), - .DI({\gwdc.wr_data_count_i[3]_i_2_n_0 ,\gwdc.wr_data_count_i[3]_i_3_n_0 ,DI,Q[0]}), + .DI({\gwdc.wr_data_count_i[3]_i_2_n_0 ,DI,Q[0]}), .O(D[3:0]), - .S({\gwdc.wr_data_count_i[3]_i_5_n_0 ,\gwdc.wr_data_count_i[3]_i_6_n_0 ,S})); + .S({\gwdc.wr_data_count_i[3]_i_5_n_0 ,\grdc.rd_data_count_i_reg[3] })); (* ADDER_THRESHOLD = "35" *) CARRY4 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(\gwdc.wr_data_count_i_reg[3]_i_1_n_0 ), @@ -6895,492 +6895,563 @@ module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0 .DI({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 }), .O(D[7:4]), .S({\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); - (* ADDER_THRESHOLD = "35" *) - CARRY4 \gwdc.wr_data_count_i_reg[9]_i_1 - (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), - .CO({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED [3:1],\gwdc.wr_data_count_i_reg[9]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[9]_i_2_n_0 }), - .O({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED [3:2],D[9:8]}), - .S({1'b0,1'b0,\gwdc.wr_data_count_i[9]_i_3_n_0 ,\gwdc.wr_data_count_i[9]_i_4_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3 - (CO, - Q, - \count_value_i_reg[4]_0 , + (Q, \count_value_i_reg[0]_0 , - E, + \count_value_i_reg[0]_1 , wr_clk); - output [0:0]CO; - input [8:0]Q; - input \count_value_i_reg[4]_0 ; - input [0:0]\count_value_i_reg[0]_0 ; - input [0:0]E; + output [11:0]Q; + input \count_value_i_reg[0]_0 ; + input [0:0]\count_value_i_reg[0]_1 ; input wr_clk; - wire [0:0]CO; - wire [0:0]E; - wire [8:0]Q; - wire \count_value_i[0]_i_1__4_n_0 ; - wire \count_value_i[1]_i_1__2_n_0 ; - wire \count_value_i[2]_i_1_n_0 ; - wire \count_value_i[3]_i_1_n_0 ; - wire \count_value_i[4]_i_1_n_0 ; - wire \count_value_i[5]_i_1_n_0 ; - wire \count_value_i[6]_i_1_n_0 ; - wire \count_value_i[7]_i_1_n_0 ; - wire \count_value_i[8]_i_1__0_n_0 ; - wire \count_value_i[8]_i_2_n_0 ; - wire [0:0]\count_value_i_reg[0]_0 ; - wire \count_value_i_reg[4]_0 ; - wire \count_value_i_reg_n_0_[0] ; - wire \count_value_i_reg_n_0_[1] ; - wire \count_value_i_reg_n_0_[2] ; - wire \count_value_i_reg_n_0_[3] ; - wire \count_value_i_reg_n_0_[4] ; - wire \count_value_i_reg_n_0_[5] ; - wire \count_value_i_reg_n_0_[6] ; - wire \count_value_i_reg_n_0_[7] ; - wire \count_value_i_reg_n_0_[8] ; - wire \gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ; - wire \gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ; - wire \gen_pntr_flags_cc.ram_empty_i_i_5_n_0 ; - wire \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2 ; - wire \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3 ; + wire [11:0]Q; + wire \count_value_i[3]_i_2__1_n_0 ; + wire \count_value_i_reg[0]_0 ; + wire [0:0]\count_value_i_reg[0]_1 ; + wire \count_value_i_reg[11]_i_1__1_n_1 ; + wire \count_value_i_reg[11]_i_1__1_n_2 ; + wire \count_value_i_reg[11]_i_1__1_n_3 ; + wire \count_value_i_reg[11]_i_1__1_n_4 ; + wire \count_value_i_reg[11]_i_1__1_n_5 ; + wire \count_value_i_reg[11]_i_1__1_n_6 ; + wire \count_value_i_reg[11]_i_1__1_n_7 ; + wire \count_value_i_reg[3]_i_1__1_n_0 ; + wire \count_value_i_reg[3]_i_1__1_n_1 ; + wire \count_value_i_reg[3]_i_1__1_n_2 ; + wire \count_value_i_reg[3]_i_1__1_n_3 ; + wire \count_value_i_reg[3]_i_1__1_n_4 ; + wire \count_value_i_reg[3]_i_1__1_n_5 ; + wire \count_value_i_reg[3]_i_1__1_n_6 ; + wire \count_value_i_reg[3]_i_1__1_n_7 ; + wire \count_value_i_reg[7]_i_1__1_n_0 ; + wire \count_value_i_reg[7]_i_1__1_n_1 ; + wire \count_value_i_reg[7]_i_1__1_n_2 ; + wire \count_value_i_reg[7]_i_1__1_n_3 ; + wire \count_value_i_reg[7]_i_1__1_n_4 ; + wire \count_value_i_reg[7]_i_1__1_n_5 ; + wire \count_value_i_reg[7]_i_1__1_n_6 ; + wire \count_value_i_reg[7]_i_1__1_n_7 ; wire wr_clk; - wire [3:3]\NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_CO_UNCONNECTED ; - wire [3:0]\NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED ; + wire [3:3]\NLW_count_value_i_reg[11]_i_1__1_CO_UNCONNECTED ; - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT1 #( - .INIT(2'h1)) - \count_value_i[0]_i_1__4 - (.I0(\count_value_i_reg_n_0_[0] ), - .O(\count_value_i[0]_i_1__4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h6)) - \count_value_i[1]_i_1__2 - (.I0(\count_value_i_reg_n_0_[1] ), - .I1(\count_value_i_reg_n_0_[0] ), - .O(\count_value_i[1]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT4 #( - .INIT(16'hDF20)) - \count_value_i[2]_i_1 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[2] ), - .O(\count_value_i[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT5 #( - .INIT(32'hDF20FF00)) - \count_value_i[3]_i_1 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[3] ), - .I4(\count_value_i_reg_n_0_[2] ), - .O(\count_value_i[3]_i_1_n_0 )); - LUT6 #( - .INIT(64'hDFFFFFFF20000000)) - \count_value_i[4]_i_1 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[2] ), - .I4(\count_value_i_reg_n_0_[3] ), - .I5(\count_value_i_reg_n_0_[4] ), - .O(\count_value_i[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT2 #( - .INIT(4'h6)) - \count_value_i[5]_i_1 - (.I0(\count_value_i_reg_n_0_[5] ), - .I1(\count_value_i[8]_i_2_n_0 ), - .O(\count_value_i[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'h6A)) - \count_value_i[6]_i_1 - (.I0(\count_value_i_reg_n_0_[6] ), - .I1(\count_value_i[8]_i_2_n_0 ), - .I2(\count_value_i_reg_n_0_[5] ), - .O(\count_value_i[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT4 #( - .INIT(16'h6AAA)) - \count_value_i[7]_i_1 - (.I0(\count_value_i_reg_n_0_[7] ), - .I1(\count_value_i_reg_n_0_[5] ), - .I2(\count_value_i[8]_i_2_n_0 ), - .I3(\count_value_i_reg_n_0_[6] ), - .O(\count_value_i[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT5 #( - .INIT(32'h6AAAAAAA)) - \count_value_i[8]_i_1__0 - (.I0(\count_value_i_reg_n_0_[8] ), - .I1(\count_value_i_reg_n_0_[6] ), - .I2(\count_value_i[8]_i_2_n_0 ), - .I3(\count_value_i_reg_n_0_[5] ), - .I4(\count_value_i_reg_n_0_[7] ), - .O(\count_value_i[8]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'h2000000000000000)) - \count_value_i[8]_i_2 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(\count_value_i_reg[4]_0 ), - .I2(\count_value_i_reg_n_0_[1] ), - .I3(\count_value_i_reg_n_0_[4] ), - .I4(\count_value_i_reg_n_0_[3] ), - .I5(\count_value_i_reg_n_0_[2] ), - .O(\count_value_i[8]_i_2_n_0 )); + \count_value_i[3]_i_2__1 + (.I0(\count_value_i_reg[0]_0 ), + .I1(Q[0]), + .O(\count_value_i[3]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), - .CE(E), - .D(\count_value_i[0]_i_1__4_n_0 ), - .Q(\count_value_i_reg_n_0_[0] ), - .S(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[3]_i_1__1_n_7 ), + .Q(Q[0]), + .S(\count_value_i_reg[0]_1 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[10] + (.C(wr_clk), + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[11]_i_1__1_n_5 ), + .Q(Q[10]), + .R(\count_value_i_reg[0]_1 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[11] + (.C(wr_clk), + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[11]_i_1__1_n_4 ), + .Q(Q[11]), + .R(\count_value_i_reg[0]_1 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[11]_i_1__1 + (.CI(\count_value_i_reg[7]_i_1__1_n_0 ), + .CO({\NLW_count_value_i_reg[11]_i_1__1_CO_UNCONNECTED [3],\count_value_i_reg[11]_i_1__1_n_1 ,\count_value_i_reg[11]_i_1__1_n_2 ,\count_value_i_reg[11]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[11]_i_1__1_n_4 ,\count_value_i_reg[11]_i_1__1_n_5 ,\count_value_i_reg[11]_i_1__1_n_6 ,\count_value_i_reg[11]_i_1__1_n_7 }), + .S(Q[11:8])); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), - .CE(E), - .D(\count_value_i[1]_i_1__2_n_0 ), - .Q(\count_value_i_reg_n_0_[1] ), - .R(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[3]_i_1__1_n_6 ), + .Q(Q[1]), + .R(\count_value_i_reg[0]_1 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), - .CE(E), - .D(\count_value_i[2]_i_1_n_0 ), - .Q(\count_value_i_reg_n_0_[2] ), - .R(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[3]_i_1__1_n_5 ), + .Q(Q[2]), + .R(\count_value_i_reg[0]_1 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), - .CE(E), - .D(\count_value_i[3]_i_1_n_0 ), - .Q(\count_value_i_reg_n_0_[3] ), - .R(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[3]_i_1__1_n_4 ), + .Q(Q[3]), + .R(\count_value_i_reg[0]_1 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[3]_i_1__1 + (.CI(1'b0), + .CO({\count_value_i_reg[3]_i_1__1_n_0 ,\count_value_i_reg[3]_i_1__1_n_1 ,\count_value_i_reg[3]_i_1__1_n_2 ,\count_value_i_reg[3]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[0]}), + .O({\count_value_i_reg[3]_i_1__1_n_4 ,\count_value_i_reg[3]_i_1__1_n_5 ,\count_value_i_reg[3]_i_1__1_n_6 ,\count_value_i_reg[3]_i_1__1_n_7 }), + .S({Q[3:1],\count_value_i[3]_i_2__1_n_0 })); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), - .CE(E), - .D(\count_value_i[4]_i_1_n_0 ), - .Q(\count_value_i_reg_n_0_[4] ), - .R(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[7]_i_1__1_n_7 ), + .Q(Q[4]), + .R(\count_value_i_reg[0]_1 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), - .CE(E), - .D(\count_value_i[5]_i_1_n_0 ), - .Q(\count_value_i_reg_n_0_[5] ), - .R(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[7]_i_1__1_n_6 ), + .Q(Q[5]), + .R(\count_value_i_reg[0]_1 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), - .CE(E), - .D(\count_value_i[6]_i_1_n_0 ), - .Q(\count_value_i_reg_n_0_[6] ), - .R(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[7]_i_1__1_n_5 ), + .Q(Q[6]), + .R(\count_value_i_reg[0]_1 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), - .CE(E), - .D(\count_value_i[7]_i_1_n_0 ), - .Q(\count_value_i_reg_n_0_[7] ), - .R(\count_value_i_reg[0]_0 )); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[7]_i_1__1_n_4 ), + .Q(Q[7]), + .R(\count_value_i_reg[0]_1 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[7]_i_1__1 + (.CI(\count_value_i_reg[3]_i_1__1_n_0 ), + .CO({\count_value_i_reg[7]_i_1__1_n_0 ,\count_value_i_reg[7]_i_1__1_n_1 ,\count_value_i_reg[7]_i_1__1_n_2 ,\count_value_i_reg[7]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[7]_i_1__1_n_4 ,\count_value_i_reg[7]_i_1__1_n_5 ,\count_value_i_reg[7]_i_1__1_n_6 ,\count_value_i_reg[7]_i_1__1_n_7 }), + .S(Q[7:4])); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), - .CE(E), - .D(\count_value_i[8]_i_1__0_n_0 ), - .Q(\count_value_i_reg_n_0_[8] ), - .R(\count_value_i_reg[0]_0 )); - LUT6 #( - .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.ram_empty_i_i_3 - (.I0(\count_value_i_reg_n_0_[7] ), - .I1(Q[7]), - .I2(Q[8]), - .I3(\count_value_i_reg_n_0_[8] ), - .I4(Q[6]), - .I5(\count_value_i_reg_n_0_[6] ), - .O(\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 )); - LUT6 #( - .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.ram_empty_i_i_4 - (.I0(\count_value_i_reg_n_0_[3] ), - .I1(Q[3]), - .I2(Q[5]), - .I3(\count_value_i_reg_n_0_[5] ), - .I4(Q[4]), - .I5(\count_value_i_reg_n_0_[4] ), - .O(\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 )); - LUT6 #( - .INIT(64'h9009000000009009)) - \gen_pntr_flags_cc.ram_empty_i_i_5 - (.I0(\count_value_i_reg_n_0_[0] ), - .I1(Q[0]), - .I2(Q[2]), - .I3(\count_value_i_reg_n_0_[2] ), - .I4(Q[1]), - .I5(\count_value_i_reg_n_0_[1] ), - .O(\gen_pntr_flags_cc.ram_empty_i_i_5_n_0 )); - CARRY4 \gen_pntr_flags_cc.ram_empty_i_reg_i_2 - (.CI(1'b0), - .CO({\NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_CO_UNCONNECTED [3],CO,\gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2 ,\gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3 }), - .CYINIT(1'b1), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED [3:0]), - .S({1'b0,\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ,\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ,\gen_pntr_flags_cc.ram_empty_i_i_5_n_0 })); + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[11]_i_1__1_n_7 ), + .Q(Q[8]), + .R(\count_value_i_reg[0]_1 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[9] + (.C(wr_clk), + .CE(\count_value_i_reg[0]_0 ), + .D(\count_value_i_reg[11]_i_1__1_n_6 ), + .Q(Q[9]), + .R(\count_value_i_reg[0]_1 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3_1 (Q, - \count_value_i_reg[8]_0 , + D, S, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] , + DI, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] , - \count_value_i_reg[4]_0 , + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] , + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 , + ram_wr_en_pf, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0 , \count_value_i_reg[0]_0 , - E, wr_clk); - output [8:0]Q; - output [0:0]\count_value_i_reg[8]_0 ; - output [0:0]S; - input [2:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] ; - input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] ; - input \count_value_i_reg[4]_0 ; + output [11:0]Q; + output [11:0]D; + input [0:0]S; + input [0:0]DI; + input [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] ; + input [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] ; + input [10:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 ; + input ram_wr_en_pf; + input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0 ; input [0:0]\count_value_i_reg[0]_0 ; - input [0:0]E; input wr_clk; - wire [0:0]E; - wire [8:0]Q; + wire [11:0]D; + wire [0:0]DI; + wire [11:0]Q; wire [0:0]S; - wire \count_value_i[0]_i_1__2_n_0 ; - wire \count_value_i[1]_i_1__0_n_0 ; - wire \count_value_i[2]_i_1__1_n_0 ; - wire \count_value_i[3]_i_1__1_n_0 ; - wire \count_value_i[4]_i_1__1_n_0 ; - wire \count_value_i[5]_i_1__1_n_0 ; - wire \count_value_i[6]_i_1__1_n_0 ; - wire \count_value_i[7]_i_1__1_n_0 ; - wire \count_value_i[8]_i_1__3_n_0 ; - wire \count_value_i[8]_i_2__1_n_0 ; wire [0:0]\count_value_i_reg[0]_0 ; - wire \count_value_i_reg[4]_0 ; - wire [0:0]\count_value_i_reg[8]_0 ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] ; - wire [2:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] ; + wire \count_value_i_reg[11]_i_1__2_n_1 ; + wire \count_value_i_reg[11]_i_1__2_n_2 ; + wire \count_value_i_reg[11]_i_1__2_n_3 ; + wire \count_value_i_reg[11]_i_1__2_n_4 ; + wire \count_value_i_reg[11]_i_1__2_n_5 ; + wire \count_value_i_reg[11]_i_1__2_n_6 ; + wire \count_value_i_reg[11]_i_1__2_n_7 ; + wire \count_value_i_reg[3]_i_1__2_n_0 ; + wire \count_value_i_reg[3]_i_1__2_n_1 ; + wire \count_value_i_reg[3]_i_1__2_n_2 ; + wire \count_value_i_reg[3]_i_1__2_n_3 ; + wire \count_value_i_reg[3]_i_1__2_n_4 ; + wire \count_value_i_reg[3]_i_1__2_n_5 ; + wire \count_value_i_reg[3]_i_1__2_n_6 ; + wire \count_value_i_reg[3]_i_1__2_n_7 ; + wire \count_value_i_reg[7]_i_1__2_n_0 ; + wire \count_value_i_reg[7]_i_1__2_n_1 ; + wire \count_value_i_reg[7]_i_1__2_n_2 ; + wire \count_value_i_reg[7]_i_1__2_n_3 ; + wire \count_value_i_reg[7]_i_1__2_n_4 ; + wire \count_value_i_reg[7]_i_1__2_n_5 ; + wire \count_value_i_reg[7]_i_1__2_n_6 ; + wire \count_value_i_reg[7]_i_1__2_n_7 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0 ; + wire [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] ; + wire [10:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_1 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_2 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_3 ; + wire [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3 ; + wire ram_wr_en_pf; wire wr_clk; + wire [3:3]\NLW_count_value_i_reg[11]_i_1__2_CO_UNCONNECTED ; + wire [3:3]\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_CO_UNCONNECTED ; - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT1 #( - .INIT(2'h1)) - \count_value_i[0]_i_1__2 - (.I0(Q[0]), - .O(\count_value_i[0]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT2 #( - .INIT(4'h6)) - \count_value_i[1]_i_1__0 - (.I0(Q[1]), - .I1(Q[0]), - .O(\count_value_i[1]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT4 #( - .INIT(16'hDF20)) - \count_value_i[2]_i_1__1 - (.I0(Q[0]), - .I1(\count_value_i_reg[4]_0 ), - .I2(Q[1]), - .I3(Q[2]), - .O(\count_value_i[2]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT5 #( - .INIT(32'hDF20FF00)) - \count_value_i[3]_i_1__1 - (.I0(Q[0]), - .I1(\count_value_i_reg[4]_0 ), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[2]), - .O(\count_value_i[3]_i_1__1_n_0 )); - LUT6 #( - .INIT(64'hDF20FF00FF00FF00)) - \count_value_i[4]_i_1__1 - (.I0(Q[0]), - .I1(\count_value_i_reg[4]_0 ), - .I2(Q[1]), - .I3(Q[4]), - .I4(Q[2]), - .I5(Q[3]), - .O(\count_value_i[4]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT2 #( - .INIT(4'h9)) - \count_value_i[5]_i_1__1 - (.I0(\count_value_i[8]_i_2__1_n_0 ), - .I1(Q[5]), - .O(\count_value_i[5]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'h9A)) - \count_value_i[6]_i_1__1 - (.I0(Q[6]), - .I1(\count_value_i[8]_i_2__1_n_0 ), - .I2(Q[5]), - .O(\count_value_i[6]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT4 #( - .INIT(16'hA6AA)) - \count_value_i[7]_i_1__1 - (.I0(Q[7]), - .I1(Q[5]), - .I2(\count_value_i[8]_i_2__1_n_0 ), - .I3(Q[6]), - .O(\count_value_i[7]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT5 #( - .INIT(32'hA6AAAAAA)) - \count_value_i[8]_i_1__3 - (.I0(Q[8]), - .I1(Q[6]), - .I2(\count_value_i[8]_i_2__1_n_0 ), - .I3(Q[5]), - .I4(Q[7]), - .O(\count_value_i[8]_i_1__3_n_0 )); - LUT6 #( - .INIT(64'hDFFFFFFFFFFFFFFF)) - \count_value_i[8]_i_2__1 - (.I0(Q[0]), - .I1(\count_value_i_reg[4]_0 ), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[2]), - .I5(Q[4]), - .O(\count_value_i[8]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), - .CE(E), - .D(\count_value_i[0]_i_1__2_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__2_n_7 ), .Q(Q[0]), .S(\count_value_i_reg[0]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[10] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__2_n_5 ), + .Q(Q[10]), + .R(\count_value_i_reg[0]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[11] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__2_n_4 ), + .Q(Q[11]), + .R(\count_value_i_reg[0]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[11]_i_1__2 + (.CI(\count_value_i_reg[7]_i_1__2_n_0 ), + .CO({\NLW_count_value_i_reg[11]_i_1__2_CO_UNCONNECTED [3],\count_value_i_reg[11]_i_1__2_n_1 ,\count_value_i_reg[11]_i_1__2_n_2 ,\count_value_i_reg[11]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[11]_i_1__2_n_4 ,\count_value_i_reg[11]_i_1__2_n_5 ,\count_value_i_reg[11]_i_1__2_n_6 ,\count_value_i_reg[11]_i_1__2_n_7 }), + .S(Q[11:8])); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), - .CE(E), - .D(\count_value_i[1]_i_1__0_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__2_n_6 ), .Q(Q[1]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), - .CE(E), - .D(\count_value_i[2]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__2_n_5 ), .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), - .CE(E), - .D(\count_value_i[3]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[3]_i_1__2_n_4 ), .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[3]_i_1__2 + (.CI(1'b0), + .CO({\count_value_i_reg[3]_i_1__2_n_0 ,\count_value_i_reg[3]_i_1__2_n_1 ,\count_value_i_reg[3]_i_1__2_n_2 ,\count_value_i_reg[3]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[0]}), + .O({\count_value_i_reg[3]_i_1__2_n_4 ,\count_value_i_reg[3]_i_1__2_n_5 ,\count_value_i_reg[3]_i_1__2_n_6 ,\count_value_i_reg[3]_i_1__2_n_7 }), + .S({Q[3:1],S})); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), - .CE(E), - .D(\count_value_i[4]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__2_n_7 ), .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), - .CE(E), - .D(\count_value_i[5]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__2_n_6 ), .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), - .CE(E), - .D(\count_value_i[6]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__2_n_5 ), .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), - .CE(E), - .D(\count_value_i[7]_i_1__1_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[7]_i_1__2_n_4 ), .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \count_value_i_reg[7]_i_1__2 + (.CI(\count_value_i_reg[3]_i_1__2_n_0 ), + .CO({\count_value_i_reg[7]_i_1__2_n_0 ,\count_value_i_reg[7]_i_1__2_n_1 ,\count_value_i_reg[7]_i_1__2_n_2 ,\count_value_i_reg[7]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_value_i_reg[7]_i_1__2_n_4 ,\count_value_i_reg[7]_i_1__2_n_5 ,\count_value_i_reg[7]_i_1__2_n_6 ,\count_value_i_reg[7]_i_1__2_n_7 }), + .S(Q[7:4])); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), - .CE(E), - .D(\count_value_i[8]_i_1__3_n_0 ), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__2_n_7 ), .Q(Q[8]), .R(\count_value_i_reg[0]_0 )); + FDRE #( + .INIT(1'b0)) + \count_value_i_reg[9] + (.C(wr_clk), + .CE(ram_wr_en_pf), + .D(\count_value_i_reg[11]_i_1__2_n_6 ), + .Q(Q[9]), + .R(\count_value_i_reg[0]_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2 + (.I0(Q[9]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [9]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3 + (.I0(Q[8]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [8]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4 + (.I0(Q[7]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [7]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4_n_0 )); LUT4 #( - .INIT(16'hA659)) + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6 + (.I0(Q[9]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [9]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [10]), + .I3(Q[10]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7 + (.I0(Q[8]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [8]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [9]), + .I3(Q[9]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8 + (.I0(Q[7]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [7]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [8]), + .I3(Q[8]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2 + (.I0(Q[2]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [2]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3 + (.I0(Q[1]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [1]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5 + (.I0(Q[2]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [2]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [3]), + .I3(Q[3]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6 + (.I0(Q[1]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [1]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [2]), + .I3(Q[2]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0 )); + LUT4 #( + .INIT(16'h9969)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8 (.I0(Q[0]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] ), - .I2(\count_value_i_reg[4]_0 ), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] [0]), - .O(S)); + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [0]), + .I2(ram_wr_en_pf), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0 ), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2 + (.I0(Q[6]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [6]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3 + (.I0(Q[5]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [5]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4 + (.I0(Q[4]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [4]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5 + (.I0(Q[3]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [3]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0 )); LUT4 #( - .INIT(16'h9699)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[9]_i_2 - (.I0(Q[8]), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] [2]), - .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] [1]), + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6 + (.I0(Q[6]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [6]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [7]), .I3(Q[7]), - .O(\count_value_i_reg[8]_0 )); + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7 + (.I0(Q[5]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [5]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [6]), + .I3(Q[6]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8 + (.I0(Q[4]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [4]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [5]), + .I3(Q[5]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0 )); + LUT4 #( + .INIT(16'hD22D)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9 + (.I0(Q[3]), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [3]), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 [4]), + .I3(Q[4]), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1 + (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0 ), + .CO({\NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_CO_UNCONNECTED [3],\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4_n_0 }), + .O(D[11:8]), + .S({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1 + (.CI(1'b0), + .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0 ,DI,1'b0}), + .O(D[3:0]), + .S({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1 + (.CI(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0 ), + .CO({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0 }), + .O(D[7:4]), + .S({\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0 })); endmodule (* AXIS_DATA_WIDTH = "53" *) (* AXIS_FINAL_DATA_WIDTH = "53" *) (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "2" *) (* CLOCKING_MODE = "COMMON" *) (* ECC_MODE = "NO_ECC" *) (* EN_ADV_FEATURE_AXIS = "16'b0001011000000110" *) (* EN_ADV_FEATURE_AXIS_INT = "16'b0001111000001110" *) (* EN_ALMOST_EMPTY_INT = "1'b1" *) -(* EN_ALMOST_FULL_INT = "1'b1" *) (* EN_DATA_VALID_INT = "1'b1" *) (* FIFO_DEPTH = "512" *) -(* FIFO_MEMORY_TYPE = "BRAM" *) (* LOG_DEPTH_AXIS = "9" *) (* ORIG_REF_NAME = "xpm_fifo_axis" *) +(* EN_ALMOST_FULL_INT = "1'b1" *) (* EN_DATA_VALID_INT = "1'b1" *) (* FIFO_DEPTH = "4096" *) +(* FIFO_MEMORY_TYPE = "BRAM" *) (* LOG_DEPTH_AXIS = "12" *) (* ORIG_REF_NAME = "xpm_fifo_axis" *) (* PACKET_FIFO = "true" *) (* PKT_SIZE_LT8 = "1'b0" *) (* PROG_EMPTY_THRESH = "5" *) -(* PROG_FULL_THRESH = "507" *) (* P_COMMON_CLOCK = "1" *) (* P_ECC_MODE = "0" *) -(* P_FIFO_MEMORY_TYPE = "2" *) (* P_PKT_MODE = "1" *) (* RD_DATA_COUNT_WIDTH = "10" *) +(* PROG_FULL_THRESH = "4091" *) (* P_COMMON_CLOCK = "1" *) (* P_ECC_MODE = "0" *) +(* P_FIFO_MEMORY_TYPE = "2" *) (* P_PKT_MODE = "1" *) (* RD_DATA_COUNT_WIDTH = "13" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* TDATA_OFFSET = "32" *) (* TDATA_WIDTH = "32" *) (* TDEST_OFFSET = "48" *) (* TDEST_WIDTH = "4" *) (* TID_OFFSET = "44" *) (* TID_WIDTH = "4" *) (* TKEEP_OFFSET = "40" *) (* TSTRB_OFFSET = "36" *) (* TUSER_MAX_WIDTH = "4047" *) (* TUSER_OFFSET = "52" *) (* TUSER_WIDTH = "4" *) (* USE_ADV_FEATURES = "1606" *) (* USE_ADV_FEATURES_INT = "826617925" *) -(* WR_DATA_COUNT_WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) +(* WR_DATA_COUNT_WIDTH = "13" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis (s_aresetn, s_aclk, @@ -7435,10 +7506,10 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis output [3:0]m_axis_tdest; output [3:0]m_axis_tuser; output prog_full_axis; - output [9:0]wr_data_count_axis; + output [12:0]wr_data_count_axis; output almost_full_axis; output prog_empty_axis; - output [9:0]rd_data_count_axis; + output [12:0]rd_data_count_axis; output almost_empty_axis; input injectsbiterr_axis; input injectdbiterr_axis; @@ -7619,7 +7690,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis wire p_3_in; wire prog_empty_axis; wire prog_full_axis; - wire [9:0]rd_data_count_axis; + wire [12:0]rd_data_count_axis; wire rst_axis; wire s_aclk; wire s_aresetn; @@ -7632,7 +7703,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis wire [3:0]s_axis_tstrb; wire [3:0]s_axis_tuser; wire s_axis_tvalid; - wire [9:0]wr_data_count_axis; + wire [12:0]wr_data_count_axis; wire [3:3]\NLW_gaxis_pkt_fifo_cc.axis_pkt_cnt_reg[28]_i_1_CO_UNCONNECTED ; wire [3:0]\NLW_gaxis_pkt_fifo_cc.axis_pkt_read_reg_i_15_O_UNCONNECTED ; wire [3:0]\NLW_gaxis_pkt_fifo_cc.axis_pkt_read_reg_i_2_O_UNCONNECTED ; @@ -8144,7 +8215,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis .D(\gaxis_pkt_fifo_cc.axis_pkt_cnt_reg[8]_i_1_n_6 ), .Q(\gaxis_pkt_fifo_cc.axis_pkt_cnt_reg [9]), .R(rst_axis)); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair5" *) LUT5 #( .INIT(32'h0000FEEE)) \gaxis_pkt_fifo_cc.axis_pkt_read_i_1 @@ -8489,7 +8560,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis \gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 (.I0(s_aresetn), .O(\gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h8)) m_axis_tvalid_INST_0 @@ -8516,26 +8587,26 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) - (* FIFO_READ_DEPTH = "512" *) + (* FIFO_READ_DEPTH = "4096" *) (* FIFO_READ_LATENCY = "0" *) - (* FIFO_SIZE = "27136" *) - (* FIFO_WRITE_DEPTH = "512" *) + (* FIFO_SIZE = "217088" *) + (* FIFO_WRITE_DEPTH = "4096" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "3" *) - (* PE_THRESH_MAX = "507" *) + (* PE_THRESH_MAX = "4091" *) (* PE_THRESH_MIN = "5" *) - (* PF_THRESH_ADJ = "505" *) - (* PF_THRESH_MAX = "507" *) + (* PF_THRESH_ADJ = "4089" *) + (* PF_THRESH_MAX = "4091" *) (* PF_THRESH_MIN = "5" *) (* PROG_EMPTY_THRESH = "5" *) - (* PROG_FULL_THRESH = "507" *) - (* RD_DATA_COUNT_WIDTH = "10" *) - (* RD_DC_WIDTH_EXT = "10" *) + (* PROG_FULL_THRESH = "4091" *) + (* RD_DATA_COUNT_WIDTH = "13" *) + (* RD_DC_WIDTH_EXT = "13" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) - (* RD_PNTR_WIDTH = "9" *) + (* RD_PNTR_WIDTH = "12" *) (* READ_DATA_WIDTH = "53" *) (* READ_MODE = "1" *) (* RELATED_CLOCKS = "0" *) @@ -8546,10 +8617,10 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "53" *) - (* WR_DATA_COUNT_WIDTH = "10" *) - (* WR_DC_WIDTH_EXT = "10" *) - (* WR_DEPTH_LOG = "9" *) - (* WR_PNTR_WIDTH = "9" *) + (* WR_DATA_COUNT_WIDTH = "13" *) + (* WR_DC_WIDTH_EXT = "13" *) + (* WR_DEPTH_LOG = "12" *) + (* WR_PNTR_WIDTH = "12" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) @@ -8600,18 +8671,18 @@ endmodule (* EN_DVLD = "1'b1" *) (* EN_OF = "1'b0" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b0" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) -(* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) -(* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "27136" *) (* FIFO_WRITE_DEPTH = "512" *) +(* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "4096" *) +(* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "217088" *) (* FIFO_WRITE_DEPTH = "4096" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) -(* PE_THRESH_ADJ = "3" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) -(* PF_THRESH_ADJ = "505" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "5" *) -(* PROG_EMPTY_THRESH = "5" *) (* PROG_FULL_THRESH = "507" *) (* RD_DATA_COUNT_WIDTH = "10" *) -(* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) -(* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "53" *) (* READ_MODE = "1" *) +(* PE_THRESH_ADJ = "3" *) (* PE_THRESH_MAX = "4091" *) (* PE_THRESH_MIN = "5" *) +(* PF_THRESH_ADJ = "4089" *) (* PF_THRESH_MAX = "4091" *) (* PF_THRESH_MIN = "5" *) +(* PROG_EMPTY_THRESH = "5" *) (* PROG_FULL_THRESH = "4091" *) (* RD_DATA_COUNT_WIDTH = "13" *) +(* RD_DC_WIDTH_EXT = "13" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) +(* RD_PNTR_WIDTH = "12" *) (* READ_DATA_WIDTH = "53" *) (* READ_MODE = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "826617925" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) -(* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "53" *) (* WR_DATA_COUNT_WIDTH = "10" *) -(* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) +(* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "53" *) (* WR_DATA_COUNT_WIDTH = "13" *) +(* WR_DC_WIDTH_EXT = "13" *) (* WR_DEPTH_LOG = "12" *) (* WR_PNTR_WIDTH = "12" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) @@ -8651,7 +8722,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base output full; output full_n; output prog_full; - output [9:0]wr_data_count; + output [12:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; @@ -8661,7 +8732,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base output [52:0]dout; output empty; output prog_empty; - output [9:0]rd_data_count; + output [12:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; @@ -8675,13 +8746,14 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base wire aempty_fwft_i0; wire almost_empty; wire almost_full; + wire clr_full; wire [1:1]count_value_i; wire [1:0]curr_fwft_state; wire data_valid; wire data_valid_fwft1; - wire [8:0]diff_pntr_pe; - wire [9:1]diff_pntr_pf_q; - wire [9:1]diff_pntr_pf_q0; + wire [11:0]diff_pntr_pe; + wire [12:1]diff_pntr_pf_q; + wire [12:1]diff_pntr_pf_q0; wire [52:0]din; wire [52:0]dout; wire full_n; @@ -8694,6 +8766,8 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0 ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0] ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[10] ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[11] ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3] ; @@ -8702,47 +8776,76 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8] ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[9] ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2_n_0 ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0 ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2_n_0 ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0 ; - wire going_afull1; - wire going_empty1; - wire [9:0]\grdc.diff_wr_rd_pntr_rdc ; + wire [12:0]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire leaving_empty0; wire [1:0]next_fwft_state__0; + wire p_1_in__0; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; - wire ram_rd_en_pf; wire ram_rd_en_pf_q; wire ram_wr_en_pf; wire ram_wr_en_pf_q; - wire [9:0]rd_data_count; + wire [12:0]rd_data_count; wire rd_en; - wire [8:0]rd_pntr_ext; + wire [11:0]rd_pntr_ext; wire rdp_inst_n_0; wire rdp_inst_n_1; + wire rdp_inst_n_15; + wire rdp_inst_n_16; + wire rdp_inst_n_17; + wire rdp_inst_n_19; wire rdp_inst_n_2; - wire rdp_inst_n_3; + wire rdp_inst_n_20; + wire rdp_inst_n_21; + wire rdp_inst_n_22; + wire rdp_inst_n_23; + wire rdp_inst_n_24; + wire rdp_inst_n_25; + wire rdp_inst_n_26; + wire rdp_inst_n_27; + wire rdp_inst_n_28; + wire rdp_inst_n_29; + wire rdp_inst_n_30; + wire rdp_inst_n_31; wire rdp_inst_n_32; + wire rdp_inst_n_33; + wire rdpp1_inst_n_0; + wire rdpp1_inst_n_1; + wire rdpp1_inst_n_10; + wire rdpp1_inst_n_11; + wire rdpp1_inst_n_2; + wire rdpp1_inst_n_3; + wire rdpp1_inst_n_4; + wire rdpp1_inst_n_5; + wire rdpp1_inst_n_6; + wire rdpp1_inst_n_7; + wire rdpp1_inst_n_8; + wire rdpp1_inst_n_9; + wire read_only; wire read_only_q; wire rst; wire rst_d1; - wire rst_d1_inst_n_1; wire rst_d1_inst_n_2; wire sleep; wire wr_clk; - wire [9:0]wr_data_count; + wire [12:0]wr_data_count; wire wr_en; - wire [8:0]wr_pntr_ext; + wire [11:0]wr_pntr_ext; + wire write_only; wire write_only_q; - wire wrp_inst_n_21; + wire wrp_inst_n_1; wire wrpp1_inst_n_0; wire wrpp1_inst_n_1; wire wrpp1_inst_n_10; + wire wrpp1_inst_n_11; wire wrpp1_inst_n_2; wire wrpp1_inst_n_3; wire wrpp1_inst_n_4; @@ -8751,12 +8854,24 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base wire wrpp1_inst_n_7; wire wrpp1_inst_n_8; wire wrpp1_inst_n_9; + wire wrpp2_inst_n_0; + wire wrpp2_inst_n_1; + wire wrpp2_inst_n_10; + wire wrpp2_inst_n_11; + wire wrpp2_inst_n_2; + wire wrpp2_inst_n_3; + wire wrpp2_inst_n_4; + wire wrpp2_inst_n_5; + wire wrpp2_inst_n_6; + wire wrpp2_inst_n_7; + wire wrpp2_inst_n_8; + wire wrpp2_inst_n_9; wire xpm_fifo_rst_inst_n_0; wire xpm_fifo_rst_inst_n_1; - wire xpm_fifo_rst_inst_n_3; - wire xpm_fifo_rst_inst_n_6; + wire xpm_fifo_rst_inst_n_11; wire xpm_fifo_rst_inst_n_7; wire xpm_fifo_rst_inst_n_8; + wire xpm_fifo_rst_inst_n_9; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; @@ -8772,21 +8887,21 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base assign underflow = \ ; assign wr_ack = \ ; assign wr_rst_busy = \ ; - (* SOFT_HLUTNM = "soft_lutpair23" *) + (* SOFT_HLUTNM = "soft_lutpair3" *) LUT4 #( - .INIT(16'h6899)) + .INIT(16'h7883)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 - (.I0(curr_fwft_state[0]), - .I1(ram_empty_i), - .I2(rd_en), - .I3(curr_fwft_state[1]), - .O(next_fwft_state__0[0])); - LUT3 #( - .INIT(8'h7C)) - \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), + .I3(ram_empty_i), + .O(next_fwft_state__0[0])); + LUT3 #( + .INIT(8'h7A)) + \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 + (.I0(curr_fwft_state[0]), + .I1(rd_en), + .I2(curr_fwft_state[1]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( @@ -8808,13 +8923,13 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .R(xpm_fifo_rst_inst_n_1)); GND GND (.G(\ )); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( - .INIT(16'hBB80)) + .INIT(16'hF380)) \gen_fwft.empty_fwft_i_i_1 - (.I0(curr_fwft_state[1]), + (.I0(rd_en), .I1(curr_fwft_state[0]), - .I2(rd_en), + .I2(curr_fwft_state[1]), .I3(\gen_fwft.empty_fwft_i_reg_n_0 ), .O(data_valid_fwft1)); FDSE #( @@ -8825,15 +8940,15 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(data_valid_fwft1), .Q(\gen_fwft.empty_fwft_i_reg_n_0 ), .S(xpm_fifo_rst_inst_n_1)); - (* SOFT_HLUTNM = "soft_lutpair23" *) + (* SOFT_HLUTNM = "soft_lutpair3" *) LUT5 #( - .INIT(32'hA888EAAA)) + .INIT(32'hFDDD4000)) \gen_fwft.gae_fwft.aempty_fwft_i_i_1 - (.I0(almost_empty), + (.I0(curr_fwft_state[0]), .I1(ram_empty_i), - .I2(rd_en), - .I3(curr_fwft_state[1]), - .I4(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .I3(rd_en), + .I4(almost_empty), .O(aempty_fwft_i0)); FDSE #( .INIT(1'b1)) @@ -8843,13 +8958,13 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(aempty_fwft_i0), .Q(almost_empty), .S(xpm_fifo_rst_inst_n_1)); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( - .INIT(16'h447F)) + .INIT(16'h0C7F)) \gen_fwft.gdvld_fwft.data_valid_fwft_i_1 - (.I0(curr_fwft_state[1]), + (.I0(rd_en), .I1(curr_fwft_state[0]), - .I2(rd_en), + .I2(curr_fwft_state[1]), .I3(\gen_fwft.empty_fwft_i_reg_n_0 ), .O(\gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0 )); FDRE #( @@ -8865,9 +8980,9 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .Q(count_value_i), .S({\gen_fwft.rdpp1_inst_n_1 ,\gen_fwft.rdpp1_inst_n_2 }), .SR(\gen_fwft.count_rst ), - .\count_value_i_reg[1]_0 (curr_fwft_state), - .\grdc.rd_data_count_i_reg[3] (wr_pntr_ext[1:0]), - .\grdc.rd_data_count_i_reg[3]_0 (rd_pntr_ext[1:0]), + .\count_value_i_reg[0]_0 (curr_fwft_state), + .\grdc.rd_data_count_i_reg[3] (rd_pntr_ext[1:0]), + .\grdc.rd_data_count_i_reg[3]_0 (wr_pntr_ext[1:0]), .ram_empty_i(ram_empty_i), .rd_en(rd_en), .wr_clk(wr_clk)); @@ -8876,7 +8991,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg (.C(wr_clk), .CE(1'b1), - .D(rdp_inst_n_2), + .D(rdp_inst_n_0), .Q(almost_full), .S(xpm_fifo_rst_inst_n_1)); FDSE #( @@ -8884,7 +8999,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), - .D(rdp_inst_n_32), + .D(rdp_inst_n_33), .Q(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0 ), .S(xpm_fifo_rst_inst_n_1)); FDRE #( @@ -8892,7 +9007,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg (.C(wr_clk), .CE(1'b1), - .D(rdp_inst_n_0), + .D(rdp_inst_n_19), .Q(full_n), .R(xpm_fifo_rst_inst_n_1)); FDSE #( @@ -8911,6 +9026,22 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(diff_pntr_pe[0]), .Q(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0] ), .R(xpm_fifo_rst_inst_n_1)); + FDRE #( + .INIT(1'b0)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(diff_pntr_pe[10]), + .Q(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[10] ), + .R(xpm_fifo_rst_inst_n_1)); + FDRE #( + .INIT(1'b0)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(diff_pntr_pe[11]), + .Q(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[11] ), + .R(xpm_fifo_rst_inst_n_1)); FDRE #( .INIT(1'b0)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[1] @@ -8975,23 +9106,33 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(diff_pntr_pe[8]), .Q(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8] ), .R(xpm_fifo_rst_inst_n_1)); - LUT4 #( - .INIT(16'hFFEF)) + FDRE #( + .INIT(1'b0)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(diff_pntr_pe[9]), + .Q(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[9] ), + .R(xpm_fifo_rst_inst_n_1)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2 (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[2] ), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[5] ), - .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0] ), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0 ), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0] ), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1] ), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[5] ), + .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3] ), + .I5(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[4] ), .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFD)) + .INIT(64'h0000000000000001)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3 - (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1] ), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8] ), - .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[4] ), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[7] ), - .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3] ), - .I5(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[6] ), + (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[10] ), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[9] ), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[11] ), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[6] ), + .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[7] ), + .I5(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8] ), .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0 )); FDRE #( .INIT(1'b1)) @@ -9004,15 +9145,39 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base FDRE \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_reg (.C(wr_clk), .CE(1'b1), - .D(xpm_fifo_rst_inst_n_7), + .D(read_only), .Q(read_only_q), .R(xpm_fifo_rst_inst_n_1)); FDRE \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg (.C(wr_clk), .CE(1'b1), - .D(xpm_fifo_rst_inst_n_6), + .D(write_only), .Q(write_only_q), .R(xpm_fifo_rst_inst_n_1)); + FDRE #( + .INIT(1'b0)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(diff_pntr_pf_q0[10]), + .Q(diff_pntr_pf_q[10]), + .R(xpm_fifo_rst_inst_n_1)); + FDRE #( + .INIT(1'b0)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(diff_pntr_pf_q0[11]), + .Q(diff_pntr_pf_q[11]), + .R(xpm_fifo_rst_inst_n_1)); + FDRE #( + .INIT(1'b0)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(diff_pntr_pf_q0[12]), + .Q(diff_pntr_pf_q[12]), + .R(xpm_fifo_rst_inst_n_1)); FDRE #( .INIT(1'b0)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[1] @@ -9085,30 +9250,32 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(diff_pntr_pf_q0[9]), .Q(diff_pntr_pf_q[9]), .R(xpm_fifo_rst_inst_n_1)); - LUT4 #( - .INIT(16'h0080)) + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2 - (.I0(diff_pntr_pf_q[8]), - .I1(diff_pntr_pf_q[9]), - .I2(diff_pntr_pf_q[1]), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0 ), + (.I0(diff_pntr_pf_q[1]), + .I1(diff_pntr_pf_q[4]), + .I2(diff_pntr_pf_q[5]), + .I3(diff_pntr_pf_q[6]), + .I4(diff_pntr_pf_q[7]), + .I5(diff_pntr_pf_q[8]), .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2_n_0 )); LUT6 #( - .INIT(64'hFDFFFFFFFFFFFFFF)) + .INIT(64'h0400000000000000)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3 - (.I0(diff_pntr_pf_q[7]), - .I1(diff_pntr_pf_q[2]), - .I2(diff_pntr_pf_q[3]), - .I3(diff_pntr_pf_q[4]), - .I4(diff_pntr_pf_q[5]), - .I5(diff_pntr_pf_q[6]), + (.I0(diff_pntr_pf_q[3]), + .I1(diff_pntr_pf_q[11]), + .I2(diff_pntr_pf_q[2]), + .I3(diff_pntr_pf_q[12]), + .I4(diff_pntr_pf_q[9]), + .I5(diff_pntr_pf_q[10]), .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg (.C(wr_clk), .CE(1'b1), - .D(rst_d1_inst_n_1), + .D(rst_d1_inst_n_2), .Q(prog_full), .S(xpm_fifo_rst_inst_n_1)); FDRE #( @@ -9116,7 +9283,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg (.C(wr_clk), .CE(1'b1), - .D(ram_rd_en_pf), + .D(rdp_inst_n_1), .Q(ram_rd_en_pf_q), .R(xpm_fifo_rst_inst_n_1)); FDRE #( @@ -9127,8 +9294,8 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(ram_wr_en_pf), .Q(ram_wr_en_pf_q), .R(xpm_fifo_rst_inst_n_1)); - (* ADDR_WIDTH_A = "9" *) - (* ADDR_WIDTH_B = "9" *) + (* ADDR_WIDTH_A = "12" *) + (* ADDR_WIDTH_B = "12" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "53" *) (* BYTE_WRITE_WIDTH_B = "53" *) @@ -9141,20 +9308,20 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "52" *) - (* \MEM.ADDRESS_SPACE_END = "511" *) + (* \MEM.ADDRESS_SPACE_END = "4095" *) (* \MEM.CORE_MEMORY_WIDTH = "53" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) - (* MEMORY_SIZE = "27136" *) + (* MEMORY_SIZE = "217088" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) - (* P_MAX_DEPTH_DATA = "512" *) + (* P_MAX_DEPTH_DATA = "4096" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "53" *) @@ -9174,10 +9341,10 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) - (* P_WIDTH_ADDR_READ_A = "9" *) - (* P_WIDTH_ADDR_READ_B = "9" *) - (* P_WIDTH_ADDR_WRITE_A = "9" *) - (* P_WIDTH_ADDR_WRITE_B = "9" *) + (* P_WIDTH_ADDR_READ_A = "12" *) + (* P_WIDTH_ADDR_READ_B = "12" *) + (* P_WIDTH_ADDR_WRITE_A = "12" *) + (* P_WIDTH_ADDR_WRITE_B = "12" *) (* P_WIDTH_COL_WRITE_A = "53" *) (* P_WIDTH_COL_WRITE_B = "53" *) (* READ_DATA_WIDTH_A = "53" *) @@ -9214,7 +9381,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [52:0]), .doutb(dout), .ena(1'b0), - .enb(ram_rd_en_pf), + .enb(rdp_inst_n_1), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), @@ -9229,10 +9396,10 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .wea(ram_wr_en_pf), .web(1'b0)); LUT3 #( - .INIT(8'h4A)) + .INIT(8'h2C)) \gen_sdpram.xpm_memory_base_inst_i_3 - (.I0(curr_fwft_state[0]), - .I1(rd_en), + (.I0(rd_en), + .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(\gen_fwft.ram_regout_en )); FDRE \grdc.rd_data_count_i_reg[0] @@ -9241,6 +9408,24 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(\grdc.diff_wr_rd_pntr_rdc [0]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); + FDRE \grdc.rd_data_count_i_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(\grdc.diff_wr_rd_pntr_rdc [10]), + .Q(rd_data_count[10]), + .R(\grdc.rd_data_count_i0 )); + FDRE \grdc.rd_data_count_i_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(\grdc.diff_wr_rd_pntr_rdc [11]), + .Q(rd_data_count[11]), + .R(\grdc.rd_data_count_i0 )); + FDRE \grdc.rd_data_count_i_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(\grdc.diff_wr_rd_pntr_rdc [12]), + .Q(rd_data_count[12]), + .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), @@ -9301,6 +9486,24 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .D(\grdc.diff_wr_rd_pntr_rdc [0]), .Q(wr_data_count[0]), .R(xpm_fifo_rst_inst_n_1)); + FDRE \gwdc.wr_data_count_i_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(\grdc.diff_wr_rd_pntr_rdc [10]), + .Q(wr_data_count[10]), + .R(xpm_fifo_rst_inst_n_1)); + FDRE \gwdc.wr_data_count_i_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(\grdc.diff_wr_rd_pntr_rdc [11]), + .Q(wr_data_count[11]), + .R(xpm_fifo_rst_inst_n_1)); + FDRE \gwdc.wr_data_count_i_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(\grdc.diff_wr_rd_pntr_rdc [12]), + .Q(wr_data_count[12]), + .R(xpm_fifo_rst_inst_n_1)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), @@ -9357,141 +9560,158 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_base .R(xpm_fifo_rst_inst_n_1)); design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2 rdp_inst (.CO(leaving_empty0), - .D(diff_pntr_pf_q0), - .E(ram_rd_en_pf), + .DI(rdp_inst_n_2), .\FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (rdp_inst_n_1), - .Q({rdp_inst_n_3,rd_pntr_ext}), - .S(wrpp1_inst_n_10), + .Q(rd_pntr_ext), + .S(rdp_inst_n_15), .almost_full(almost_full), - .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1), - .\count_value_i_reg[8]_0 (diff_pntr_pe), - .\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg (going_afull1), - .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (rdp_inst_n_0), - .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 (rdp_inst_n_32), - .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg (xpm_fifo_rst_inst_n_3), - .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0 (\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0 ), - .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1 (rst_d1_inst_n_2), - .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2 (curr_fwft_state), - .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0 ({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6,wrpp1_inst_n_7,wrpp1_inst_n_8}), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] (xpm_fifo_rst_inst_n_8), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] (wr_pntr_ext[7:0]), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8] (wrp_inst_n_21), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] (wrpp1_inst_n_9), + .clr_full(clr_full), + .\count_value_i_reg[0]_0 (rdp_inst_n_31), + .\count_value_i_reg[0]_1 (curr_fwft_state), + .\count_value_i_reg[0]_2 (xpm_fifo_rst_inst_n_1), + .\count_value_i_reg[11]_0 (rdp_inst_n_17), + .\count_value_i_reg[11]_1 ({rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30}), + .\count_value_i_reg[1]_0 (rdp_inst_n_16), + .\count_value_i_reg[1]_1 (rdp_inst_n_32), + .\count_value_i_reg[3]_0 ({rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22}), + .\count_value_i_reg[7]_0 ({rdp_inst_n_23,rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26}), + .\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0 ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8,wrpp2_inst_n_9,wrpp2_inst_n_10,wrpp2_inst_n_11}), + .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (rdp_inst_n_19), + .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 (rdp_inst_n_33), + .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg (\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0 ), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] ({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6,wrpp1_inst_n_7,wrpp1_inst_n_8,wrpp1_inst_n_9,wrpp1_inst_n_10,wrpp1_inst_n_11}), + .\grdc.rd_data_count_i_reg[12] ({wrp_inst_n_1,wr_pntr_ext}), + .\grdc.rd_data_count_i_reg[3] (count_value_i), .ram_empty_i(ram_empty_i), + .ram_wr_en_pf(ram_wr_en_pf), .rd_en(rd_en), .rst(rst), - .\syncstages_ff_reg[3] (rdp_inst_n_2), + .\syncstages_ff_reg[3] (rdp_inst_n_0), .wr_clk(wr_clk)); design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3 rdpp1_inst - (.CO(going_empty1), - .E(ram_rd_en_pf), - .Q(wr_pntr_ext), - .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1), - .\count_value_i_reg[4]_0 (rdp_inst_n_1), + (.Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7,rdpp1_inst_n_8,rdpp1_inst_n_9,rdpp1_inst_n_10,rdpp1_inst_n_11}), + .\count_value_i_reg[0]_0 (rdp_inst_n_1), + .\count_value_i_reg[0]_1 (xpm_fifo_rst_inst_n_1), .wr_clk(wr_clk)); design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit rst_d1_inst (.Q(xpm_fifo_rst_inst_n_1), + .clr_full(clr_full), .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg (\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2_n_0 ), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg (rst_d1_inst_n_1), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0 (\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0 ), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg (rst_d1_inst_n_2), .prog_full(prog_full), .ram_rd_en_pf_q(ram_rd_en_pf_q), .ram_wr_en_pf_q(ram_wr_en_pf_q), .rst(rst), .rst_d1(rst_d1), - .\syncstages_ff_reg[3] (rst_d1_inst_n_2), .wr_clk(wr_clk)); design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0 wrp_inst (.CO(leaving_empty0), .D(\grdc.diff_wr_rd_pntr_rdc ), - .DI(\gen_fwft.rdpp1_inst_n_3 ), - .E(ram_wr_en_pf), - .Q(wr_pntr_ext), - .S({\gen_fwft.rdpp1_inst_n_1 ,\gen_fwft.rdpp1_inst_n_2 }), - .\count_value_i_reg[8]_0 (wrp_inst_n_21), - .\count_value_i_reg[9]_0 (xpm_fifo_rst_inst_n_1), + .DI({rdp_inst_n_16,\gen_fwft.rdpp1_inst_n_3 }), + .Q({wrp_inst_n_1,wr_pntr_ext}), + .S(xpm_fifo_rst_inst_n_7), + .\count_value_i_reg[10]_0 (diff_pntr_pe), + .\count_value_i_reg[12]_0 (xpm_fifo_rst_inst_n_1), .\gen_pntr_flags_cc.ram_empty_i_reg (rdp_inst_n_1), - .\gen_pntr_flags_cc.ram_empty_i_reg_0 (xpm_fifo_rst_inst_n_3), - .\gen_pntr_flags_cc.ram_empty_i_reg_1 (going_empty1), - .\grdc.rd_data_count_i_reg[3] (count_value_i), - .\grdc.rd_data_count_i_reg[9] ({rdp_inst_n_3,rd_pntr_ext}), + .\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7,rdpp1_inst_n_8,rdpp1_inst_n_9,rdpp1_inst_n_10,rdpp1_inst_n_11}), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11] ({rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30}), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] (p_1_in__0), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0 ({rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,xpm_fifo_rst_inst_n_11}), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7] ({rdp_inst_n_23,rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26}), + .\grdc.rd_data_count_i_reg[11] (rd_pntr_ext[11:2]), + .\grdc.rd_data_count_i_reg[12] (rdp_inst_n_17), + .\grdc.rd_data_count_i_reg[3] ({rdp_inst_n_32,\gen_fwft.rdpp1_inst_n_1 ,\gen_fwft.rdpp1_inst_n_2 }), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), + .ram_wr_en_pf(ram_wr_en_pf), .wr_clk(wr_clk)); design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3_1 wrpp1_inst - (.E(ram_wr_en_pf), - .Q({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6,wrpp1_inst_n_7,wrpp1_inst_n_8}), - .S(wrpp1_inst_n_10), + (.D(diff_pntr_pf_q0), + .DI(rdp_inst_n_2), + .Q({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6,wrpp1_inst_n_7,wrpp1_inst_n_8,wrpp1_inst_n_9,wrpp1_inst_n_10,wrpp1_inst_n_11}), + .S(xpm_fifo_rst_inst_n_8), .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1), - .\count_value_i_reg[4]_0 (xpm_fifo_rst_inst_n_3), - .\count_value_i_reg[8]_0 (wrpp1_inst_n_9), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] (rdp_inst_n_1), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9] ({rd_pntr_ext[8:7],rd_pntr_ext[0]}), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12] (rdp_inst_n_15), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0 (rd_pntr_ext[10:0]), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4] (rdp_inst_n_31), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0 (rdp_inst_n_1), + .ram_wr_en_pf(ram_wr_en_pf), .wr_clk(wr_clk)); design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized0 wrpp2_inst - (.E(ram_wr_en_pf), - .Q(rd_pntr_ext), + (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8,wrpp2_inst_n_9,wrpp2_inst_n_10,wrpp2_inst_n_11}), + .S(xpm_fifo_rst_inst_n_9), .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1), - .\count_value_i_reg[4]_0 (xpm_fifo_rst_inst_n_3), - .\count_value_i_reg[7]_0 (going_afull1), + .ram_wr_en_pf(ram_wr_en_pf), .wr_clk(wr_clk)); design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst xpm_fifo_rst_inst - (.E(ram_wr_en_pf), - .Q(xpm_fifo_rst_inst_n_1), - .SR(\gen_fwft.count_rst ), - .\count_value_i_reg[1] (curr_fwft_state), - .\gen_fwft.empty_fwft_i_reg (xpm_fifo_rst_inst_n_6), - .\gen_fwft.empty_fwft_i_reg_0 (xpm_fifo_rst_inst_n_7), - .\gen_fwft.empty_fwft_i_reg_1 (xpm_fifo_rst_inst_n_8), + (.Q(xpm_fifo_rst_inst_n_1), + .S(xpm_fifo_rst_inst_n_7), + .SR(\grdc.rd_data_count_i0 ), + .\count_value_i_reg[0] (xpm_fifo_rst_inst_n_8), + .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_9), + .\count_value_i_reg[3] (wr_pntr_ext[0]), + .\count_value_i_reg[3]_0 (wrpp1_inst_n_11), + .\count_value_i_reg[3]_1 (wrpp2_inst_n_11), + .\gen_fwft.empty_fwft_i_reg (p_1_in__0), + .\gen_fwft.empty_fwft_i_reg_0 (xpm_fifo_rst_inst_n_11), .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] (rd_pntr_ext[0]), .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg (xpm_fifo_rst_inst_n_0), .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0 (\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2_n_0 ), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1 (\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0 ), .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg (\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0 ), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 (rdp_inst_n_1), - .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 (\gen_fwft.empty_fwft_i_reg_n_0 ), - .\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 (xpm_fifo_rst_inst_n_3), - .\gen_rst_cc.fifo_wr_rst_cc_reg[2]_1 (\grdc.rd_data_count_i0 ), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 (\gen_fwft.empty_fwft_i_reg_n_0 ), + .\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 (rdp_inst_n_1), + .\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 (\gen_fwft.count_rst ), + .\grdc.rd_data_count_i_reg[0] (curr_fwft_state), .prog_empty(prog_empty), .ram_empty_i(ram_empty_i), + .ram_wr_en_pf(ram_wr_en_pf), + .read_only(read_only), .read_only_q(read_only_q), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), + .write_only(write_only), .write_only_q(write_only_q)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit (rst_d1, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg , - \syncstages_ff_reg[3] , + clr_full, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg , Q, wr_clk, - ram_rd_en_pf_q, - ram_wr_en_pf_q, + rst, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg , - prog_full, - rst); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0 , + ram_wr_en_pf_q, + ram_rd_en_pf_q, + prog_full); output rst_d1; - output \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg ; - output \syncstages_ff_reg[3] ; + output clr_full; + output \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg ; input [0:0]Q; input wr_clk; - input ram_rd_en_pf_q; - input ram_wr_en_pf_q; - input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ; - input prog_full; input rst; + input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ; + input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0 ; + input ram_wr_en_pf_q; + input ram_rd_en_pf_q; + input prog_full; wire [0:0]Q; + wire clr_full; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ; - wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg ; wire prog_full; wire ram_rd_en_pf_q; wire ram_wr_en_pf_q; wire rst; wire rst_d1; - wire \syncstages_ff_reg[3] ; wire wr_clk; FDRE #( @@ -9504,154 +9724,198 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit .R(1'b0)); LUT3 #( .INIT(8'h04)) - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6 + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_2 (.I0(rst), .I1(rst_d1), .I2(Q), - .O(\syncstages_ff_reg[3] )); - LUT5 #( - .INIT(32'h51551000)) + .O(clr_full)); + LUT6 #( + .INIT(64'h5545555500001000)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_1 - (.I0(\syncstages_ff_reg[3] ), - .I1(ram_rd_en_pf_q), - .I2(ram_wr_en_pf_q), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ), - .I4(prog_full), - .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg )); + (.I0(clr_full), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg ), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0 ), + .I3(ram_wr_en_pf_q), + .I4(ram_rd_en_pf_q), + .I5(prog_full), + .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg )); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst (\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg , Q, - E, - \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 , + write_only, + ram_wr_en_pf, + read_only, SR, - \gen_rst_cc.fifo_wr_rst_cc_reg[2]_1 , + \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 , + S, + \count_value_i_reg[0] , + \count_value_i_reg[0]_0 , \gen_fwft.empty_fwft_i_reg , \gen_fwft.empty_fwft_i_reg_0 , - \gen_fwft.empty_fwft_i_reg_1 , prog_empty, write_only_q, - read_only_q, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0 , + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1 , + read_only_q, rst, - wr_en, - rst_d1, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg , - \count_value_i_reg[1] , - ram_empty_i, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 , \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 , + wr_en, + rst_d1, + \grdc.rd_data_count_i_reg[0] , + ram_empty_i, + \count_value_i_reg[3] , + \count_value_i_reg[3]_0 , + \count_value_i_reg[3]_1 , \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] , wr_clk); output \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg ; output [0:0]Q; - output [0:0]E; - output \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ; + output write_only; + output ram_wr_en_pf; + output read_only; output [0:0]SR; - output [0:0]\gen_rst_cc.fifo_wr_rst_cc_reg[2]_1 ; - output \gen_fwft.empty_fwft_i_reg ; - output \gen_fwft.empty_fwft_i_reg_0 ; - output [0:0]\gen_fwft.empty_fwft_i_reg_1 ; + output [0:0]\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ; + output [0:0]S; + output [0:0]\count_value_i_reg[0] ; + output [0:0]\count_value_i_reg[0]_0 ; + output [0:0]\gen_fwft.empty_fwft_i_reg ; + output [0:0]\gen_fwft.empty_fwft_i_reg_0 ; input prog_empty; input write_only_q; - input read_only_q; input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0 ; + input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1 ; + input read_only_q; input rst; - input wr_en; - input rst_d1; input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ; - input [1:0]\count_value_i_reg[1] ; - input ram_empty_i; input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ; input \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ; + input wr_en; + input rst_d1; + input [1:0]\grdc.rd_data_count_i_reg[0] ; + input ram_empty_i; + input [0:0]\count_value_i_reg[3] ; + input [0:0]\count_value_i_reg[3]_0 ; + input [0:0]\count_value_i_reg[3]_1 ; input [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ; input wr_clk; - wire [0:0]E; wire [0:0]Q; + wire [0:0]S; wire [0:0]SR; - wire [1:0]\count_value_i_reg[1] ; - wire \gen_fwft.empty_fwft_i_reg ; - wire \gen_fwft.empty_fwft_i_reg_0 ; - wire [0:0]\gen_fwft.empty_fwft_i_reg_1 ; + wire [0:0]\count_value_i_reg[0] ; + wire [0:0]\count_value_i_reg[0]_0 ; + wire [0:0]\count_value_i_reg[3] ; + wire [0:0]\count_value_i_reg[3]_0 ; + wire [0:0]\count_value_i_reg[3]_1 ; + wire [0:0]\gen_fwft.empty_fwft_i_reg ; + wire [0:0]\gen_fwft.empty_fwft_i_reg_0 ; wire [0:0]\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0 ; + wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1 ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ; wire \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ; wire [1:0]\gen_rst_cc.fifo_wr_rst_cc ; - wire \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ; - wire [0:0]\gen_rst_cc.fifo_wr_rst_cc_reg[2]_1 ; + wire [0:0]\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ; + wire [1:0]\grdc.rd_data_count_i_reg[0] ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire prog_empty; wire ram_empty_i; + wire ram_wr_en_pf; + wire read_only; wire read_only_q; wire rst; wire rst_d1; wire rst_i; wire wr_clk; wire wr_en; + wire write_only; wire write_only_q; - (* SOFT_HLUTNM = "soft_lutpair21" *) + (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( - .INIT(16'hABAA)) + .INIT(16'hAAAE)) \count_value_i[1]_i_1 (.I0(Q), - .I1(\count_value_i_reg[1] [0]), - .I2(\count_value_i_reg[1] [1]), - .I3(ram_empty_i), - .O(SR)); - LUT4 #( - .INIT(16'hFFFD)) - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_3 - (.I0(wr_en), - .I1(Q), - .I2(rst_d1), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ), + .I1(ram_empty_i), + .I2(\grdc.rd_data_count_i_reg[0] [1]), + .I3(\grdc.rd_data_count_i_reg[0] [0]), .O(\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 )); + LUT2 #( + .INIT(4'h6)) + \count_value_i[3]_i_2 + (.I0(ram_wr_en_pf), + .I1(\count_value_i_reg[3] ), + .O(S)); + LUT2 #( + .INIT(4'h6)) + \count_value_i[3]_i_2__2 + (.I0(ram_wr_en_pf), + .I1(\count_value_i_reg[3]_0 ), + .O(\count_value_i_reg[0] )); + LUT2 #( + .INIT(4'h6)) + \count_value_i[3]_i_2__3 + (.I0(ram_wr_en_pf), + .I1(\count_value_i_reg[3]_1 ), + .O(\count_value_i_reg[0]_0 )); LUT4 #( - .INIT(16'hFB04)) - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_9 - (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ), - .I1(\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ), - .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ), - .O(\gen_fwft.empty_fwft_i_reg_1 )); + .INIT(16'hBFBB)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2 + (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ), + .I3(ram_wr_en_pf), + .O(\gen_fwft.empty_fwft_i_reg )); LUT5 #( - .INIT(32'hFFFFAAF2)) + .INIT(32'hBFBB4044)) + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6 + (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ), + .I3(ram_wr_en_pf), + .I4(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3] ), + .O(\gen_fwft.empty_fwft_i_reg_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFAFAAA2AA)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_1 (.I0(prog_empty), .I1(write_only_q), - .I2(read_only_q), - .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0 ), - .I4(Q), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0 ), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1 ), + .I4(read_only_q), + .I5(Q), .O(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT3 #( - .INIT(8'h04)) + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h4044)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_i_1 - (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ), - .I1(\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ), - .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ), - .O(\gen_fwft.empty_fwft_i_reg_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT3 #( - .INIT(8'h54)) + (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ), + .I3(ram_wr_en_pf), + .O(read_only)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h4044)) \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_i_1 - (.I0(\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ), - .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ), - .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ), - .O(\gen_fwft.empty_fwft_i_reg )); + (.I0(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ), + .I1(ram_wr_en_pf), + .I2(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0 ), + .I3(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1 ), + .O(write_only)); LUT2 #( .INIT(4'hE)) \gen_rst_cc.fifo_wr_rst_cc[2]_i_1 - (.I0(rst), - .I1(p_0_in), + (.I0(p_0_in), + .I1(rst), .O(rst_i)); FDSE #( .INIT(1'b0)) @@ -9677,19 +9941,22 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst .D(\gen_rst_cc.fifo_wr_rst_cc [1]), .Q(Q), .S(rst_i)); - LUT1 #( - .INIT(2'h1)) + LUT4 #( + .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 - (.I0(\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0 ), - .O(E)); - (* SOFT_HLUTNM = "soft_lutpair21" *) + (.I0(wr_en), + .I1(\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg ), + .I2(Q), + .I3(rst_d1), + .O(ram_wr_en_pf)); + (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'hAB)) - \grdc.rd_data_count_i[9]_i_1 + \grdc.rd_data_count_i[12]_i_1 (.I0(Q), - .I1(\count_value_i_reg[1] [1]), - .I2(\count_value_i_reg[1] [0]), - .O(\gen_rst_cc.fifo_wr_rst_cc_reg[2]_1 )); + .I1(\grdc.rd_data_count_i_reg[0] [1]), + .I2(\grdc.rd_data_count_i_reg[0] [0]), + .O(SR)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] @@ -9708,21 +9975,21 @@ module design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst .R(1'b0)); endmodule -(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) +(* ADDR_WIDTH_A = "12" *) (* ADDR_WIDTH_B = "12" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "53" *) (* BYTE_WRITE_WIDTH_B = "53" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "0" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) -(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "27136" *) (* MEMORY_TYPE = "1" *) +(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "217088" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) -(* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) +(* P_MAX_DEPTH_DATA = "4096" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "53" *) (* P_MIN_WIDTH_DATA_A = "53" *) (* P_MIN_WIDTH_DATA_B = "53" *) (* P_MIN_WIDTH_DATA_ECC = "53" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "53" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) -(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) -(* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) +(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "12" *) +(* P_WIDTH_ADDR_READ_B = "12" *) (* P_WIDTH_ADDR_WRITE_A = "12" *) (* P_WIDTH_ADDR_WRITE_B = "12" *) (* P_WIDTH_COL_WRITE_A = "53" *) (* P_WIDTH_COL_WRITE_B = "53" *) (* READ_DATA_WIDTH_A = "53" *) (* READ_DATA_WIDTH_B = "53" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "" *) (* RST_MODE_A = "SYNC" *) @@ -9764,7 +10031,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_memory_base input ena; input regcea; input [0:0]wea; - input [8:0]addra; + input [11:0]addra; input [52:0]dina; input injectsbiterra; input injectdbiterra; @@ -9776,7 +10043,7 @@ module design_1_axi_fifo_mm_s_0_0_xpm_memory_base input enb; input regceb; input [0:0]web; - input [8:0]addrb; + input [11:0]addrb; input [52:0]dinb; input injectsbiterrb; input injectdbiterrb; @@ -9785,25 +10052,97 @@ module design_1_axi_fifo_mm_s_0_0_xpm_memory_base output dbiterrb; wire \ ; - wire [8:0]addra; - wire [8:0]addrb; + wire [11:0]addra; + wire [11:0]addrb; wire clka; wire [52:0]dina; wire [52:0]doutb; wire enb; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_60 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_61 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_62 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_63 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_64 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_65 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_66 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_67 ; + wire \gen_wr_a.gen_word_narrow.mem_reg_4_n_75 ; wire regceb; wire rstb; wire sleep; wire [0:0]wea; - wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED ; - wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED ; - wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; - wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; - wire [31:21]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED ; - wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED ; - wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTA_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTB_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTDBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTSBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOADO_UNCONNECTED ; + wire [31:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_RDADDRECC_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTA_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTB_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_INJECTDBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_INJECTSBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOADO_UNCONNECTED ; + wire [31:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_RDADDRECC_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTA_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTB_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTDBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTSBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOADO_UNCONNECTED ; + wire [31:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_RDADDRECC_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTA_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTB_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTDBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTSBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOADO_UNCONNECTED ; + wire [31:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_RDADDRECC_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTA_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTB_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTDBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTSBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOADO_UNCONNECTED ; + wire [31:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_RDADDRECC_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTA_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTB_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTDBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTSBITERR_UNCONNECTED ; + wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOADO_UNCONNECTED ; + wire [31:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; @@ -9864,31 +10203,103 @@ module design_1_axi_fifo_mm_s_0_0_xpm_memory_base assign sbiterrb = \ ; GND GND (.G(\ )); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][36] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_67 ), + .Q(doutb[36]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][37] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_66 ), + .Q(doutb[37]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][38] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_65 ), + .Q(doutb[38]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][39] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_64 ), + .Q(doutb[39]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][40] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_63 ), + .Q(doutb[40]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][41] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_62 ), + .Q(doutb[41]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][42] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_61 ), + .Q(doutb[42]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][43] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_60 ), + .Q(doutb[43]), + .R(rstb)); + FDRE #( + .INIT(1'b0)) + \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][44] + (.C(clka), + .CE(regceb), + .D(\gen_wr_a.gen_word_narrow.mem_reg_4_n_75 ), + .Q(doutb[44]), + .R(rstb)); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) - (* \MEM.PORTA.ADDRESS_END = "511" *) - (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d53" *) + (* \MEM.PORTA.ADDRESS_END = "4095" *) + (* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *) (* \MEM.PORTA.DATA_LSB = "0" *) - (* \MEM.PORTA.DATA_MSB = "52" *) + (* \MEM.PORTA.DATA_MSB = "8" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) - (* \MEM.PORTB.ADDRESS_END = "511" *) - (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d53" *) + (* \MEM.PORTB.ADDRESS_END = "4095" *) + (* \MEM.PORTB.DATA_BIT_LAYOUT = "p1_d8" *) (* \MEM.PORTB.DATA_LSB = "0" *) - (* \MEM.PORTB.DATA_MSB = "52" *) + (* \MEM.PORTB.DATA_MSB = "8" *) (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "27136" *) + (* RTL_RAM_BITS = "217088" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* bram_addr_begin = "0" *) - (* bram_addr_end = "511" *) + (* bram_addr_end = "4095" *) (* bram_slice_begin = "0" *) - (* bram_slice_end = "52" *) + (* bram_slice_end = "8" *) (* ram_addr_begin = "0" *) - (* ram_addr_end = "511" *) + (* ram_addr_end = "4095" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) - (* ram_slice_end = "52" *) + (* ram_slice_end = "8" *) RAMB36E1 #( - .DOA_REG(1), + .DOA_REG(0), .DOB_REG(1), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), @@ -10040,53 +10451,1168 @@ module design_1_axi_fifo_mm_s_0_0_xpm_memory_base .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), - .RAM_MODE("SDP"), + .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(72), - .READ_WIDTH_B(0), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(0), - .WRITE_WIDTH_B(72)) - \gen_wr_a.gen_word_narrow.mem_reg - (.ADDRARDADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED ), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("NO_CHANGE"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \gen_wr_a.gen_word_narrow.mem_reg_0 + (.ADDRARDADDR({1'b1,addra,1'b0,1'b0,1'b0}), + .ADDRBWRADDR({1'b1,addrb,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b1), + .CASCADEINB(1'b1), + .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clka), - .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), - .DIADI(dina[31:0]), - .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[52:32]}), - .DIPADIP({1'b1,1'b1,1'b1,1'b1}), - .DIPBDIP({1'b1,1'b1,1'b1,1'b1}), - .DOADO(doutb[31:0]), - .DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED [31:21],doutb[52:32]}), - .DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED [3:0]), - .DOPBDOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED [3:0]), - .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(enb), - .ENBWREN(1'b1), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(regceb), + .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b1}), + .DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), + .DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), + .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(wea), + .ENBWREN(enb), + .INJECTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTDBITERR_UNCONNECTED ), + .INJECTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTSBITERR_UNCONNECTED ), + .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(regceb), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(rstb), + .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_SBITERR_UNCONNECTED ), + .WEA({wea,wea,wea,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); + (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTA.ADDRESS_END = "4095" *) + (* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTA.DATA_LSB = "9" *) + (* \MEM.PORTA.DATA_MSB = "17" *) + (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTB.ADDRESS_END = "4095" *) + (* \MEM.PORTB.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTB.DATA_LSB = "9" *) + (* \MEM.PORTB.DATA_MSB = "17" *) + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "217088" *) + (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* bram_addr_begin = "0" *) + (* bram_addr_end = "4095" *) + (* bram_slice_begin = "9" *) + (* bram_slice_end = "17" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "4095" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "9" *) + (* ram_slice_end = "17" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("NO_CHANGE"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \gen_wr_a.gen_word_narrow.mem_reg_1 + (.ADDRARDADDR({1'b1,addra,1'b0,1'b0,1'b0}), + .ADDRBWRADDR({1'b1,addrb,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b1), + .CASCADEINB(1'b1), + .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(clka), + .CLKBWRCLK(clka), + .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[16:9]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .DIPADIP({1'b0,1'b0,1'b0,dina[17]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b1}), + .DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOBDO_UNCONNECTED [31:8],doutb[16:9]}), + .DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOPBDOP_UNCONNECTED [3:1],doutb[17]}), + .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(wea), + .ENBWREN(enb), + .INJECTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_INJECTDBITERR_UNCONNECTED ), + .INJECTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_INJECTSBITERR_UNCONNECTED ), + .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(regceb), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(rstb), + .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_1_SBITERR_UNCONNECTED ), + .WEA({wea,wea,wea,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); + (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTA.ADDRESS_END = "4095" *) + (* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTA.DATA_LSB = "18" *) + (* \MEM.PORTA.DATA_MSB = "26" *) + (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTB.ADDRESS_END = "4095" *) + (* \MEM.PORTB.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTB.DATA_LSB = "18" *) + (* \MEM.PORTB.DATA_MSB = "26" *) + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "217088" *) + (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* bram_addr_begin = "0" *) + (* bram_addr_end = "4095" *) + (* bram_slice_begin = "18" *) + (* bram_slice_end = "26" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "4095" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "26" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("NO_CHANGE"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \gen_wr_a.gen_word_narrow.mem_reg_2 + (.ADDRARDADDR({1'b1,addra,1'b0,1'b0,1'b0}), + .ADDRBWRADDR({1'b1,addrb,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b1), + .CASCADEINB(1'b1), + .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(clka), + .CLKBWRCLK(clka), + .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[25:18]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .DIPADIP({1'b0,1'b0,1'b0,dina[26]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b1}), + .DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOBDO_UNCONNECTED [31:8],doutb[25:18]}), + .DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPBDOP_UNCONNECTED [3:1],doutb[26]}), + .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(wea), + .ENBWREN(enb), + .INJECTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTDBITERR_UNCONNECTED ), + .INJECTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTSBITERR_UNCONNECTED ), + .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(regceb), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(rstb), + .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_2_SBITERR_UNCONNECTED ), + .WEA({wea,wea,wea,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); + (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTA.ADDRESS_END = "4095" *) + (* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTA.DATA_LSB = "27" *) + (* \MEM.PORTA.DATA_MSB = "35" *) + (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTB.ADDRESS_END = "4095" *) + (* \MEM.PORTB.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTB.DATA_LSB = "27" *) + (* \MEM.PORTB.DATA_MSB = "35" *) + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "217088" *) + (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* bram_addr_begin = "0" *) + (* bram_addr_end = "4095" *) + (* bram_slice_begin = "27" *) + (* bram_slice_end = "35" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "4095" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "27" *) + (* ram_slice_end = "35" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("NO_CHANGE"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \gen_wr_a.gen_word_narrow.mem_reg_3 + (.ADDRARDADDR({1'b1,addra,1'b0,1'b0,1'b0}), + .ADDRBWRADDR({1'b1,addrb,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b1), + .CASCADEINB(1'b1), + .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(clka), + .CLKBWRCLK(clka), + .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[34:27]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .DIPADIP({1'b0,1'b0,1'b0,dina[35]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b1}), + .DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOBDO_UNCONNECTED [31:8],doutb[34:27]}), + .DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPBDOP_UNCONNECTED [3:1],doutb[35]}), + .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(wea), + .ENBWREN(enb), + .INJECTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTDBITERR_UNCONNECTED ), + .INJECTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTSBITERR_UNCONNECTED ), + .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(regceb), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(rstb), + .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_3_SBITERR_UNCONNECTED ), + .WEA({wea,wea,wea,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); + (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTA.ADDRESS_END = "4095" *) + (* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTA.DATA_LSB = "36" *) + (* \MEM.PORTA.DATA_MSB = "44" *) + (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTB.ADDRESS_END = "4095" *) + (* \MEM.PORTB.DATA_BIT_LAYOUT = "p1_d8" *) + (* \MEM.PORTB.DATA_LSB = "36" *) + (* \MEM.PORTB.DATA_MSB = "44" *) + (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) + (* RTL_RAM_BITS = "217088" *) + (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* bram_addr_begin = "0" *) + (* bram_addr_end = "4095" *) + (* bram_slice_begin = "36" *) + (* bram_slice_end = "44" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "4095" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "36" *) + (* ram_slice_end = "44" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("NO_CHANGE"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \gen_wr_a.gen_word_narrow.mem_reg_4 + (.ADDRARDADDR({1'b1,addra,1'b0,1'b0,1'b0}), + .ADDRBWRADDR({1'b1,addrb,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b1), + .CASCADEINB(1'b1), + .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(clka), + .CLKBWRCLK(clka), + .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[43:36]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .DIPADIP({1'b0,1'b0,1'b0,dina[44]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b1}), + .DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOBDO_UNCONNECTED [31:8],\gen_wr_a.gen_word_narrow.mem_reg_4_n_60 ,\gen_wr_a.gen_word_narrow.mem_reg_4_n_61 ,\gen_wr_a.gen_word_narrow.mem_reg_4_n_62 ,\gen_wr_a.gen_word_narrow.mem_reg_4_n_63 ,\gen_wr_a.gen_word_narrow.mem_reg_4_n_64 ,\gen_wr_a.gen_word_narrow.mem_reg_4_n_65 ,\gen_wr_a.gen_word_narrow.mem_reg_4_n_66 ,\gen_wr_a.gen_word_narrow.mem_reg_4_n_67 }), + .DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPBDOP_UNCONNECTED [3:1],\gen_wr_a.gen_word_narrow.mem_reg_4_n_75 }), + .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(wea), + .ENBWREN(enb), + .INJECTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTDBITERR_UNCONNECTED ), + .INJECTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTSBITERR_UNCONNECTED ), + .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), - .RSTREGARSTREG(rstb), + .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), - .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({wea,wea,wea,wea,wea,wea,wea,wea})); + .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_4_SBITERR_UNCONNECTED ), + .WEA({wea,wea,wea,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); + (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTA.ADDRESS_END = "4095" *) + (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8" *) + (* \MEM.PORTA.DATA_LSB = "45" *) + (* \MEM.PORTA.DATA_MSB = "52" *) + (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) + (* \MEM.PORTB.ADDRESS_END = "4095" *) + (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8" *) + (* \MEM.PORTB.DATA_LSB = "45" *) + (* \MEM.PORTB.DATA_MSB = "52" *) + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "217088" *) + (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* bram_addr_begin = "0" *) + (* bram_addr_end = "4095" *) + (* bram_slice_begin = "45" *) + (* bram_slice_end = "52" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "4095" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "45" *) + (* ram_slice_end = "52" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("NO_CHANGE"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \gen_wr_a.gen_word_narrow.mem_reg_5 + (.ADDRARDADDR({1'b1,addra,1'b0,1'b0,1'b0}), + .ADDRBWRADDR({1'b1,addrb,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b1), + .CASCADEINB(1'b1), + .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(clka), + .CLKBWRCLK(clka), + .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[52:45]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOBDO_UNCONNECTED [31:8],doutb[52:45]}), + .DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPBDOP_UNCONNECTED [3:0]), + .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(wea), + .ENBWREN(enb), + .INJECTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTDBITERR_UNCONNECTED ), + .INJECTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTSBITERR_UNCONNECTED ), + .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(regceb), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(rstb), + .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_5_SBITERR_UNCONNECTED ), + .WEA({wea,wea,wea,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule `ifndef GLBL `define GLBL diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.vhdl b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.vhdl index a179243..7ba2159 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.vhdl +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 --- Date : Thu Jan 20 22:00:03 2022 +-- Date : Wed May 11 18:46:03 2022 -- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim --- c:/Users/Aleksa/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.vhdl +-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_Rev2/dso_top_Rev2.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.vhdl -- Design : design_1_axi_fifo_mm_s_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -467,11 +467,10 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized0\ is port ( - \count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 8 downto 0 ); - \count_value_i_reg[4]_0\ : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_wr_en_pf : in STD_LOGIC; wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -479,170 +478,94 @@ entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized0\ is end \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized0\; architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized0\ is - signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[5]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[6]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[7]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3\ : STD_LOGIC; - signal \NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \count_value_i[0]_i_1__3\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \count_value_i[5]_i_1__0\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \count_value_i[6]_i_1__0\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \count_value_i[7]_i_1__0\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \count_value_i[8]_i_1__2\ : label is "soft_lutpair17"; + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \count_value_i_reg[11]_i_1__3_n_1\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__3_n_2\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__3_n_3\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__3_n_4\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__3_n_5\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__3_n_6\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__3_n_7\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_0\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_1\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_2\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_3\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_4\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_5\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_6\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__3_n_7\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_0\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_1\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_2\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_3\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_4\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_5\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_6\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__3_n_7\ : STD_LOGIC; + signal \NLW_count_value_i_reg[11]_i_1__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \count_value_i_reg[11]_i_1__3\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[3]_i_1__3\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[7]_i_1__3\ : label is 35; begin -\count_value_i[0]_i_1__3\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - O => \count_value_i[0]_i_1__3_n_0\ - ); -\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \count_value_i_reg_n_0_[1]\, - I1 => \count_value_i_reg_n_0_[0]\, - O => \count_value_i[1]_i_1__1_n_0\ - ); -\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"DF20" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[2]\, - O => \count_value_i[2]_i_1__0_n_0\ - ); -\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"DF20FF00" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[3]\, - I4 => \count_value_i_reg_n_0_[2]\, - O => \count_value_i[3]_i_1__0_n_0\ - ); -\count_value_i[4]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DF20FF00FF00FF00" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[4]\, - I4 => \count_value_i_reg_n_0_[2]\, - I5 => \count_value_i_reg_n_0_[3]\, - O => \count_value_i[4]_i_1__0_n_0\ - ); -\count_value_i[5]_i_1__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \count_value_i[8]_i_2__0_n_0\, - I1 => \count_value_i_reg_n_0_[5]\, - O => \count_value_i[5]_i_1__0_n_0\ - ); -\count_value_i[6]_i_1__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"9A" - ) - port map ( - I0 => \count_value_i_reg_n_0_[6]\, - I1 => \count_value_i[8]_i_2__0_n_0\, - I2 => \count_value_i_reg_n_0_[5]\, - O => \count_value_i[6]_i_1__0_n_0\ - ); -\count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"A6AA" - ) - port map ( - I0 => \count_value_i_reg_n_0_[7]\, - I1 => \count_value_i_reg_n_0_[5]\, - I2 => \count_value_i[8]_i_2__0_n_0\, - I3 => \count_value_i_reg_n_0_[6]\, - O => \count_value_i[7]_i_1__0_n_0\ - ); -\count_value_i[8]_i_1__2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"A6AAAAAA" - ) - port map ( - I0 => \count_value_i_reg_n_0_[8]\, - I1 => \count_value_i_reg_n_0_[6]\, - I2 => \count_value_i[8]_i_2__0_n_0\, - I3 => \count_value_i_reg_n_0_[5]\, - I4 => \count_value_i_reg_n_0_[7]\, - O => \count_value_i[8]_i_1__2_n_0\ - ); -\count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DFFFFFFFFFFFFFFF" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[3]\, - I4 => \count_value_i_reg_n_0_[2]\, - I5 => \count_value_i_reg_n_0_[4]\, - O => \count_value_i[8]_i_2__0_n_0\ - ); + Q(11 downto 0) <= \^q\(11 downto 0); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[0]_i_1__3_n_0\, - Q => \count_value_i_reg_n_0_[0]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__3_n_7\, + Q => \^q\(0), R => \count_value_i_reg[0]_0\(0) ); +\count_value_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__3_n_5\, + Q => \^q\(10), + R => \count_value_i_reg[0]_0\(0) + ); +\count_value_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__3_n_4\, + Q => \^q\(11), + R => \count_value_i_reg[0]_0\(0) + ); +\count_value_i_reg[11]_i_1__3\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[7]_i_1__3_n_0\, + CO(3) => \NLW_count_value_i_reg[11]_i_1__3_CO_UNCONNECTED\(3), + CO(2) => \count_value_i_reg[11]_i_1__3_n_1\, + CO(1) => \count_value_i_reg[11]_i_1__3_n_2\, + CO(0) => \count_value_i_reg[11]_i_1__3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[11]_i_1__3_n_4\, + O(2) => \count_value_i_reg[11]_i_1__3_n_5\, + O(1) => \count_value_i_reg[11]_i_1__3_n_6\, + O(0) => \count_value_i_reg[11]_i_1__3_n_7\, + S(3 downto 0) => \^q\(11 downto 8) + ); \count_value_i_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[1]_i_1__1_n_0\, - Q => \count_value_i_reg_n_0_[1]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__3_n_6\, + Q => \^q\(1), S => \count_value_i_reg[0]_0\(0) ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE @@ -651,9 +574,9 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[2]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[2]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__3_n_5\, + Q => \^q\(2), R => \count_value_i_reg[0]_0\(0) ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE @@ -662,20 +585,37 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[3]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[3]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__3_n_4\, + Q => \^q\(3), R => \count_value_i_reg[0]_0\(0) ); +\count_value_i_reg[3]_i_1__3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \count_value_i_reg[3]_i_1__3_n_0\, + CO(2) => \count_value_i_reg[3]_i_1__3_n_1\, + CO(1) => \count_value_i_reg[3]_i_1__3_n_2\, + CO(0) => \count_value_i_reg[3]_i_1__3_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \^q\(0), + O(3) => \count_value_i_reg[3]_i_1__3_n_4\, + O(2) => \count_value_i_reg[3]_i_1__3_n_5\, + O(1) => \count_value_i_reg[3]_i_1__3_n_6\, + O(0) => \count_value_i_reg[3]_i_1__3_n_7\, + S(3 downto 1) => \^q\(3 downto 1), + S(0) => S(0) + ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[4]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[4]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__3_n_7\, + Q => \^q\(4), R => \count_value_i_reg[0]_0\(0) ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE @@ -684,9 +624,9 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[5]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[5]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__3_n_6\, + Q => \^q\(5), R => \count_value_i_reg[0]_0\(0) ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE @@ -695,9 +635,9 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[6]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[6]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__3_n_5\, + Q => \^q\(6), R => \count_value_i_reg[0]_0\(0) ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE @@ -706,75 +646,47 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[7]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[7]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__3_n_4\, + Q => \^q\(7), R => \count_value_i_reg[0]_0\(0) ); +\count_value_i_reg[7]_i_1__3\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[3]_i_1__3_n_0\, + CO(3) => \count_value_i_reg[7]_i_1__3_n_0\, + CO(2) => \count_value_i_reg[7]_i_1__3_n_1\, + CO(1) => \count_value_i_reg[7]_i_1__3_n_2\, + CO(0) => \count_value_i_reg[7]_i_1__3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[7]_i_1__3_n_4\, + O(2) => \count_value_i_reg[7]_i_1__3_n_5\, + O(1) => \count_value_i_reg[7]_i_1__3_n_6\, + O(0) => \count_value_i_reg[7]_i_1__3_n_7\, + S(3 downto 0) => \^q\(7 downto 4) + ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[8]_i_1__2_n_0\, - Q => \count_value_i_reg_n_0_[8]\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__3_n_7\, + Q => \^q\(8), R => \count_value_i_reg[0]_0\(0) ); -\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4\: unisim.vcomponents.LUT6 +\count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"9009000000009009" + INIT => '0' ) port map ( - I0 => \count_value_i_reg_n_0_[7]\, - I1 => Q(7), - I2 => Q(8), - I3 => \count_value_i_reg_n_0_[8]\, - I4 => Q(6), - I5 => \count_value_i_reg_n_0_[6]\, - O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0\ - ); -\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9009000000009009" - ) - port map ( - I0 => \count_value_i_reg_n_0_[3]\, - I1 => Q(3), - I2 => Q(5), - I3 => \count_value_i_reg_n_0_[5]\, - I4 => Q(4), - I5 => \count_value_i_reg_n_0_[4]\, - O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\ - ); -\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9009000000009009" - ) - port map ( - I0 => \count_value_i_reg_n_0_[1]\, - I1 => Q(1), - I2 => Q(2), - I3 => \count_value_i_reg_n_0_[2]\, - I4 => Q(0), - I5 => \count_value_i_reg_n_0_[0]\, - O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\ - ); -\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_CO_UNCONNECTED\(3), - CO(2) => \count_value_i_reg[7]_0\(0), - CO(1) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2\, - CO(0) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3\, - CYINIT => '1', - DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED\(3 downto 0), - S(3) => '0', - S(2) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0\, - S(1) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\, - S(0) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\ + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__3_n_6\, + Q => \^q\(9), + R => \count_value_i_reg[0]_0\(0) ); end STRUCTURE; library IEEE; @@ -786,9 +698,9 @@ entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized1\ is Q : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 1 downto 0 ); DI : out STD_LOGIC_VECTOR ( 0 to 0 ); - \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; + \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_en : in STD_LOGIC; \grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \grdc.rd_data_count_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); @@ -802,11 +714,11 @@ architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__paramete signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal count_value_i : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC; + signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_3_n_0\ : STD_LOGIC; signal \gen_fwft.count_en\ : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \count_value_i[0]_i_1__0\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \count_value_i[1]_i_3\ : label is "soft_lutpair0"; attribute HLUTNM : string; attribute HLUTNM of \gwdc.wr_data_count_i[3]_i_4\ : label is "lutpair0"; @@ -814,36 +726,40 @@ architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__paramete begin DI(0) <= \^di\(0); Q(0) <= \^q\(0); -\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1 +\count_value_i[0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"1" + INIT => X"5AAAA655" ) port map ( I0 => count_value_i(0), - O => \count_value_i[0]_i_1__0_n_0\ + I1 => \count_value_i_reg[0]_0\(0), + I2 => rd_en, + I3 => \count_value_i_reg[0]_0\(1), + I4 => ram_empty_i, + O => \count_value_i[0]_i_1_n_0\ ); \count_value_i[1]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"9585" + INIT => X"C02F" ) port map ( - I0 => ram_empty_i, + I0 => \count_value_i_reg[0]_0\(0), I1 => rd_en, - I2 => \count_value_i_reg[1]_0\(1), - I3 => \count_value_i_reg[1]_0\(0), + I2 => \count_value_i_reg[0]_0\(1), + I3 => ram_empty_i, O => \gen_fwft.count_en\ ); \count_value_i[1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"AA956AAAAA996AAA" + INIT => X"A999A9A96AAA6AAA" ) port map ( I0 => \^q\(0), - I1 => \count_value_i_reg[1]_0\(1), - I2 => rd_en, - I3 => ram_empty_i, - I4 => count_value_i(0), - I5 => \count_value_i_reg[1]_0\(0), + I1 => ram_empty_i, + I2 => \count_value_i_reg[0]_0\(1), + I3 => rd_en, + I4 => \count_value_i_reg[0]_0\(0), + I5 => count_value_i(0), O => \count_value_i[1]_i_3_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE @@ -853,7 +769,7 @@ begin port map ( C => wr_clk, CE => \gen_fwft.count_en\, - D => \count_value_i[0]_i_1__0_n_0\, + D => \count_value_i[0]_i_1_n_0\, Q => count_value_i(0), R => SR(0) ); @@ -874,7 +790,7 @@ begin ) port map ( I0 => count_value_i(0), - I1 => \grdc.rd_data_count_i_reg[3]_0\(0), + I1 => \grdc.rd_data_count_i_reg[3]\(0), O => \^di\(0) ); \gwdc.wr_data_count_i[3]_i_7\: unisim.vcomponents.LUT4 @@ -884,8 +800,8 @@ begin port map ( I0 => \^di\(0), I1 => \grdc.rd_data_count_i_reg[3]\(1), - I2 => \grdc.rd_data_count_i_reg[3]_0\(1), - I3 => \^q\(0), + I2 => \^q\(0), + I3 => \grdc.rd_data_count_i_reg[3]_0\(1), O => S(1) ); \gwdc.wr_data_count_i[3]_i_8\: unisim.vcomponents.LUT3 @@ -894,8 +810,8 @@ begin ) port map ( I0 => count_value_i(0), - I1 => \grdc.rd_data_count_i_reg[3]_0\(0), - I2 => \grdc.rd_data_count_i_reg[3]\(0), + I1 => \grdc.rd_data_count_i_reg[3]\(0), + I2 => \grdc.rd_data_count_i_reg[3]_0\(0), O => S(0) ); end STRUCTURE; @@ -905,31 +821,34 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2\ is port ( - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ : out STD_LOGIC; - \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : out STD_LOGIC; \syncstages_ff_reg[3]\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - D : out STD_LOGIC_VECTOR ( 8 downto 0 ); - \count_value_i_reg[8]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : out STD_LOGIC; + DI : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \count_value_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \count_value_i_reg[11]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ : out STD_LOGIC; + \count_value_i_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \count_value_i_reg[11]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \count_value_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \count_value_i_reg[1]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\ : out STD_LOGIC; - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\ : in STD_LOGIC; - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0\ : in STD_LOGIC; - CO : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1\ : in STD_LOGIC; + clr_full : in STD_LOGIC; rst : in STD_LOGIC; almost_full : in STD_LOGIC; - \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - ram_empty_i : in STD_LOGIC; + ram_wr_en_pf : in STD_LOGIC; + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \grdc.rd_data_count_i_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\ : in STD_LOGIC; + \count_value_i_reg[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; - S : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); - \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_i : in STD_LOGIC; + \count_value_i_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -937,222 +856,82 @@ entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2\ is end \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2\; architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2\ is - signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\ : STD_LOGIC; - signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[1]_i_1__4_n_0\ : STD_LOGIC; - signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[9]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[9]_i_2_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \count_value_i[3]_i_2__0_n_0\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_0\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_1\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_2\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_3\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_4\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_5\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_6\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__0_n_7\ : STD_LOGIC; + signal \count_value_i_reg[12]_i_1__0_n_7\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_0\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_1\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_2\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_3\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_4\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_5\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_6\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__0_n_7\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_0\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_1\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_2\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_3\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_4\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_5\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_6\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__0_n_7\ : STD_LOGIC; + signal \count_value_i_reg_n_0_[12]\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0\ : STD_LOGIC; signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0\ : STD_LOGIC; signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0\ : STD_LOGIC; signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_3\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_3\ : STD_LOGIC; + signal going_afull1 : STD_LOGIC; signal going_full1 : STD_LOGIC; signal ram_afull_i0 : STD_LOGIC; - signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \count_value_i[1]_i_1__4\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \count_value_i[2]_i_1__2\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \count_value_i[5]_i_1__2\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \count_value_i[6]_i_1__2\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \count_value_i[7]_i_1__2\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair1"; + signal \NLW_count_value_i_reg[12]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_count_value_i_reg[12]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute ADDER_THRESHOLD : integer; - attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1\ : label is 35; - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1\ : label is 35; - attribute METHODOLOGY_DRC_VIOS of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1\ : label is 35; - attribute METHODOLOGY_DRC_VIOS of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1\ : label is 35; - attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1\ : label is 35; - attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[11]_i_1__0\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[12]_i_1__0\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[3]_i_1__0\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[7]_i_1__0\ : label is 35; begin - E(0) <= \^e\(0); + CO(0) <= \^co\(0); \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ <= \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\; - Q(9 downto 0) <= \^q\(9 downto 0); -\count_value_i[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(0), - O => \count_value_i[0]_i_1_n_0\ - ); -\count_value_i[1]_i_1__4\: unisim.vcomponents.LUT2 + Q(11 downto 0) <= \^q\(11 downto 0); +\count_value_i[3]_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( - I0 => \^q\(1), + I0 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, I1 => \^q\(0), - O => \count_value_i[1]_i_1__4_n_0\ - ); -\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"DF20" - ) - port map ( - I0 => \^q\(0), - I1 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I2 => \^q\(1), - I3 => \^q\(2), - O => \count_value_i[2]_i_1__2_n_0\ - ); -\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"DF20FF00" - ) - port map ( - I0 => \^q\(0), - I1 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(2), - O => \count_value_i[3]_i_1__2_n_0\ - ); -\count_value_i[4]_i_1__2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DF20FF00FF00FF00" - ) - port map ( - I0 => \^q\(0), - I1 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I2 => \^q\(1), - I3 => \^q\(4), - I4 => \^q\(3), - I5 => \^q\(2), - O => \count_value_i[4]_i_1__2_n_0\ - ); -\count_value_i[5]_i_1__2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(5), - I1 => \count_value_i[9]_i_2_n_0\, - O => \count_value_i[5]_i_1__2_n_0\ - ); -\count_value_i[6]_i_1__2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"A6" - ) - port map ( - I0 => \^q\(6), - I1 => \^q\(5), - I2 => \count_value_i[9]_i_2_n_0\, - O => \count_value_i[6]_i_1__2_n_0\ - ); -\count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"A6AA" - ) - port map ( - I0 => \^q\(7), - I1 => \^q\(6), - I2 => \count_value_i[9]_i_2_n_0\, - I3 => \^q\(5), - O => \count_value_i[7]_i_1__2_n_0\ - ); -\count_value_i[8]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"A6AAAAAA" - ) - port map ( - I0 => \^q\(8), - I1 => \^q\(5), - I2 => \count_value_i[9]_i_2_n_0\, - I3 => \^q\(6), - I4 => \^q\(7), - O => \count_value_i[8]_i_1_n_0\ - ); -\count_value_i[9]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AAAA6AAAAAAAAAAA" - ) - port map ( - I0 => \^q\(9), - I1 => \^q\(8), - I2 => \^q\(7), - I3 => \^q\(6), - I4 => \count_value_i[9]_i_2_n_0\, - I5 => \^q\(5), - O => \count_value_i[9]_i_1_n_0\ - ); -\count_value_i[9]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DFFFFFFFFFFFFFFF" - ) - port map ( - I0 => \^q\(0), - I1 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(2), - I5 => \^q\(4), - O => \count_value_i[9]_i_2_n_0\ + O => \count_value_i[3]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( @@ -1160,10 +939,69 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[0]_i_1_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[3]_i_1__0_n_7\, Q => \^q\(0), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) + ); +\count_value_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[11]_i_1__0_n_5\, + Q => \^q\(10), + R => \count_value_i_reg[0]_2\(0) + ); +\count_value_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[11]_i_1__0_n_4\, + Q => \^q\(11), + R => \count_value_i_reg[0]_2\(0) + ); +\count_value_i_reg[11]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[7]_i_1__0_n_0\, + CO(3) => \count_value_i_reg[11]_i_1__0_n_0\, + CO(2) => \count_value_i_reg[11]_i_1__0_n_1\, + CO(1) => \count_value_i_reg[11]_i_1__0_n_2\, + CO(0) => \count_value_i_reg[11]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[11]_i_1__0_n_4\, + O(2) => \count_value_i_reg[11]_i_1__0_n_5\, + O(1) => \count_value_i_reg[11]_i_1__0_n_6\, + O(0) => \count_value_i_reg[11]_i_1__0_n_7\, + S(3 downto 0) => \^q\(11 downto 8) + ); +\count_value_i_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[12]_i_1__0_n_7\, + Q => \count_value_i_reg_n_0_[12]\, + R => \count_value_i_reg[0]_2\(0) + ); +\count_value_i_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[11]_i_1__0_n_0\, + CO(3 downto 0) => \NLW_count_value_i_reg[12]_i_1__0_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_count_value_i_reg[12]_i_1__0_O_UNCONNECTED\(3 downto 1), + O(0) => \count_value_i_reg[12]_i_1__0_n_7\, + S(3 downto 1) => B"000", + S(0) => \count_value_i_reg_n_0_[12]\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -1171,10 +1009,10 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[1]_i_1__4_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[3]_i_1__0_n_6\, Q => \^q\(1), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -1182,10 +1020,10 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[2]_i_1__2_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[3]_i_1__0_n_5\, Q => \^q\(2), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( @@ -1193,10 +1031,27 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[3]_i_1__2_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[3]_i_1__0_n_4\, Q => \^q\(3), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) + ); +\count_value_i_reg[3]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \count_value_i_reg[3]_i_1__0_n_0\, + CO(2) => \count_value_i_reg[3]_i_1__0_n_1\, + CO(1) => \count_value_i_reg[3]_i_1__0_n_2\, + CO(0) => \count_value_i_reg[3]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \^q\(0), + O(3) => \count_value_i_reg[3]_i_1__0_n_4\, + O(2) => \count_value_i_reg[3]_i_1__0_n_5\, + O(1) => \count_value_i_reg[3]_i_1__0_n_6\, + O(0) => \count_value_i_reg[3]_i_1__0_n_7\, + S(3 downto 1) => \^q\(3 downto 1), + S(0) => \count_value_i[3]_i_2__0_n_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( @@ -1204,10 +1059,10 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[4]_i_1__2_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[7]_i_1__0_n_7\, Q => \^q\(4), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( @@ -1215,10 +1070,10 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[5]_i_1__2_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[7]_i_1__0_n_6\, Q => \^q\(5), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( @@ -1226,10 +1081,10 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[6]_i_1__2_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[7]_i_1__0_n_5\, Q => \^q\(6), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( @@ -1237,10 +1092,25 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[7]_i_1__2_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[7]_i_1__0_n_4\, Q => \^q\(7), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) + ); +\count_value_i_reg[7]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[3]_i_1__0_n_0\, + CO(3) => \count_value_i_reg[7]_i_1__0_n_0\, + CO(2) => \count_value_i_reg[7]_i_1__0_n_1\, + CO(1) => \count_value_i_reg[7]_i_1__0_n_2\, + CO(0) => \count_value_i_reg[7]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[7]_i_1__0_n_4\, + O(2) => \count_value_i_reg[7]_i_1__0_n_5\, + O(1) => \count_value_i_reg[7]_i_1__0_n_6\, + O(0) => \count_value_i_reg[7]_i_1__0_n_7\, + S(3 downto 0) => \^q\(7 downto 4) ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( @@ -1248,10 +1118,10 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[8]_i_1_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[11]_i_1__0_n_7\, Q => \^q\(8), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) ); \count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( @@ -1259,82 +1129,203 @@ begin ) port map ( C => wr_clk, - CE => \^e\(0), - D => \count_value_i[9]_i_1_n_0\, + CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + D => \count_value_i_reg[11]_i_1__0_n_6\, Q => \^q\(9), - R => \count_value_i_reg[0]_0\(0) + R => \count_value_i_reg[0]_2\(0) ); \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"3202" + INIT => X"F202" ) port map ( I0 => ram_afull_i0, - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1\, + I1 => clr_full, I2 => rst, I3 => almost_full, O => \syncstages_ff_reg[3]\ ); \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"C4FCC4CC" + INIT => X"F3FF00A0" ) port map ( - I0 => going_full1, - I1 => almost_full, - I2 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\, - I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg\(0), + I0 => going_afull1, + I1 => going_full1, + I2 => ram_wr_en_pf, + I3 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + I4 => almost_full, O => ram_afull_i0 ); +\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(9), + I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(9), + I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(11), + I3 => \^q\(11), + I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(10), + I5 => \^q\(10), + O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0\ + ); +\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(6), + I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(6), + I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(8), + I3 => \^q\(8), + I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(7), + I5 => \^q\(7), + O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\ + ); +\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(3), + I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(3), + I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(5), + I3 => \^q\(5), + I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(4), + I5 => \^q\(4), + O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\ + ); +\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(0), + I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(0), + I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(2), + I3 => \^q\(2), + I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(1), + I5 => \^q\(1), + O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0\ + ); +\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => going_afull1, + CO(2) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_1\, + CO(1) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_2\, + CO(0) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_n_3\, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_O_UNCONNECTED\(3 downto 0), + S(3) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4_n_0\, + S(2) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\, + S(1) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\, + S(0) => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0\ + ); \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"00000000F020FF20" + INIT => X"0545044404440444" ) port map ( - I0 => going_full1, + I0 => clr_full, I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\, I2 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0\, - I4 => CO(0), - I5 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1\, + I3 => \^co\(0), + I4 => going_full1, + I5 => ram_wr_en_pf, O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\ ); \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF0FDF00DF" + INIT => X"FABAFBBBFBBBFBBB" ) port map ( - I0 => going_full1, + I0 => clr_full, I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\, I2 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0\, - I4 => CO(0), - I5 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1\, + I3 => \^co\(0), + I4 => going_full1, + I5 => ram_wr_en_pf, O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_4\: unisim.vcomponents.LUT4 +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10\: unisim.vcomponents.LUT6 generic map( - INIT => X"F0F4" + INIT => X"9009000000009009" ) port map ( - I0 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2\(0), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2\(1), - I2 => ram_empty_i, - I3 => rd_en, - O => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\ + I0 => \^q\(6), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(6), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(8), + I3 => \^q\(8), + I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(7), + I5 => \^q\(7), + O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\ + ); +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(3), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(3), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(5), + I3 => \^q\(5), + I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(4), + I5 => \^q\(4), + O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\ + ); +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(0), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(0), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(2), + I3 => \^q\(2), + I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(1), + I5 => \^q\(1), + O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\ + ); +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(9), + I1 => \grdc.rd_data_count_i_reg[12]\(9), + I2 => \grdc.rd_data_count_i_reg[12]\(11), + I3 => \^q\(11), + I4 => \grdc.rd_data_count_i_reg[12]\(10), + I5 => \^q\(10), + O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5_n_0\ + ); +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(6), + I1 => \grdc.rd_data_count_i_reg[12]\(6), + I2 => \grdc.rd_data_count_i_reg[12]\(8), + I3 => \^q\(8), + I4 => \grdc.rd_data_count_i_reg[12]\(7), + I5 => \^q\(7), + O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0\ ); \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( - I0 => \^q\(6), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(6), - I2 => \^q\(7), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(7), - I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(8), - I5 => \^q\(8), + I0 => \^q\(3), + I1 => \grdc.rd_data_count_i_reg[12]\(3), + I2 => \grdc.rd_data_count_i_reg[12]\(5), + I3 => \^q\(5), + I4 => \grdc.rd_data_count_i_reg[12]\(4), + I5 => \^q\(4), O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0\ ); \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8\: unisim.vcomponents.LUT6 @@ -1342,12 +1333,12 @@ begin INIT => X"9009000000009009" ) port map ( - I0 => \^q\(4), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(4), - I2 => \^q\(3), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(3), - I4 => \^q\(5), - I5 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(5), + I0 => \^q\(0), + I1 => \grdc.rd_data_count_i_reg[12]\(0), + I2 => \grdc.rd_data_count_i_reg[12]\(2), + I3 => \^q\(2), + I4 => \grdc.rd_data_count_i_reg[12]\(1), + I5 => \^q\(1), O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0\ ); \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9\: unisim.vcomponents.LUT6 @@ -1355,399 +1346,221 @@ begin INIT => X"9009000000009009" ) port map ( - I0 => \^q\(2), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(2), - I2 => \^q\(1), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(1), - I4 => \^q\(0), - I5 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(0), + I0 => \^q\(9), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(9), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(11), + I3 => \^q\(11), + I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(10), + I5 => \^q\(10), O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0\ ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2\: unisim.vcomponents.CARRY4 +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', - CO(3) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_CO_UNCONNECTED\(3), - CO(2) => going_full1, - CO(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_2\, - CO(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_n_3\, + CO(3) => \^co\(0), + CO(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_1\, + CO(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_2\, + CO(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_n_3\, CYINIT => '1', DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_O_UNCONNECTED\(3 downto 0), - S(3) => '0', - S(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0\, - S(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0\, - S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0\ + O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_O_UNCONNECTED\(3 downto 0), + S(3) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_5_n_0\, + S(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0\, + S(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_7_n_0\, + S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0\ ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2\: unisim.vcomponents.LUT1 +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => going_full1, + CO(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_1\, + CO(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_2\, + CO(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_n_3\, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_O_UNCONNECTED\(3 downto 0), + S(3) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0\, + S(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\, + S(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\, + S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"1" + INIT => X"9" + ) + port map ( + I0 => \^q\(11), + I1 => \grdc.rd_data_count_i_reg[12]\(11), + O => \count_value_i_reg[11]_1\(3) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(10), + I1 => \grdc.rd_data_count_i_reg[12]\(10), + O => \count_value_i_reg[11]_1\(2) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(9), + I1 => \grdc.rd_data_count_i_reg[12]\(9), + O => \count_value_i_reg[11]_1\(1) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[11]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(8), + I1 => \grdc.rd_data_count_i_reg[12]\(8), + O => \count_value_i_reg[11]_1\(0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" ) port map ( I0 => \^q\(3), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2_n_0\ + I1 => \grdc.rd_data_count_i_reg[12]\(3), + O => \count_value_i_reg[3]_0\(2) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3\: unisim.vcomponents.LUT1 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"1" + INIT => X"9" ) port map ( I0 => \^q\(2), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3_n_0\ + I1 => \grdc.rd_data_count_i_reg[12]\(2), + O => \count_value_i_reg[3]_0\(1) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4\: unisim.vcomponents.LUT1 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => X"1" + INIT => X"9" ) port map ( I0 => \^q\(1), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4_n_0\ + I1 => \grdc.rd_data_count_i_reg[12]\(1), + O => \count_value_i_reg[3]_0\(0) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5\: unisim.vcomponents.LUT1 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"1" + INIT => X"9" + ) + port map ( + I0 => \^q\(7), + I1 => \grdc.rd_data_count_i_reg[12]\(7), + O => \count_value_i_reg[7]_0\(3) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(6), + I1 => \grdc.rd_data_count_i_reg[12]\(6), + O => \count_value_i_reg[7]_0\(2) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(5), + I1 => \grdc.rd_data_count_i_reg[12]\(5), + O => \count_value_i_reg[7]_0\(1) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(4), + I1 => \grdc.rd_data_count_i_reg[12]\(4), + O => \count_value_i_reg[7]_0\(0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B44B" + ) + port map ( + I0 => \^q\(10), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(10), + I2 => \^q\(11), + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(11), + O => S(0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7510" ) port map ( I0 => \^q\(0), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(3), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(3), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(2), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(2), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(1), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(1), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(7), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(6), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(5), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(4), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(7), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(7), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(6), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(6), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(5), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(5), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(4), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(4), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0\, - CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1\, - CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2\, - CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3\, - CYINIT => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(0), - DI(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2_n_0\, - DI(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_3_n_0\, - DI(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_4_n_0\, - DI(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_5_n_0\, - O(3 downto 0) => \count_value_i_reg[8]_0\(3 downto 0), - S(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6_n_0\, - S(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_7_n_0\, - S(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_8_n_0\, - S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\(0) - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0\, - CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0\, - CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1\, - CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2\, - CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3\, - CYINIT => '0', - DI(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_2_n_0\, - DI(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_3_n_0\, - DI(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_4_n_0\, - DI(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_5_n_0\, - O(3 downto 0) => \count_value_i_reg[8]_0\(7 downto 4), - S(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_6_n_0\, - S(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_7_n_0\, - S(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_8_n_0\, - S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[7]_i_9_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0\, - CO(3 downto 0) => \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED\(3 downto 0), - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3 downto 1) => \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED\(3 downto 1), - O(0) => \count_value_i_reg[8]_0\(8), - S(3 downto 1) => B"000", - S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]\(0) - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(3), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(3), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(2), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(2), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(1), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(1), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(3), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(3), - I2 => \^q\(2), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(2), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(2), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(2), - I2 => \^q\(1), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(1), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0\ + I1 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + I2 => ram_wr_en_pf, + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(0), + O => DI(0) ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7\: unisim.vcomponents.LUT6 generic map( - INIT => X"9699999966669699" + INIT => X"8AEF751075108AEF" + ) + port map ( + I0 => \^q\(0), + I1 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, + I2 => ram_wr_en_pf, + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(0), + I4 => \^q\(1), + I5 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(1), + O => \count_value_i_reg[0]_0\(0) + ); +\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00FB" + ) + port map ( + I0 => \count_value_i_reg[0]_1\(0), + I1 => \count_value_i_reg[0]_1\(1), + I2 => rd_en, + I3 => ram_empty_i, + O => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\ + ); +\gwdc.wr_data_count_i[12]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B44B" + ) + port map ( + I0 => \^q\(11), + I1 => \grdc.rd_data_count_i_reg[12]\(11), + I2 => \count_value_i_reg_n_0_[12]\, + I3 => \grdc.rd_data_count_i_reg[12]\(12), + O => \count_value_i_reg[11]_0\(0) + ); +\gwdc.wr_data_count_i[3]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D4" ) port map ( I0 => \^q\(1), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(1), - I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\, - I3 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(0), - I5 => \^q\(0), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7_n_0\ + I1 => \grdc.rd_data_count_i_reg[3]\(0), + I2 => \grdc.rd_data_count_i_reg[12]\(1), + O => \count_value_i_reg[1]_0\(0) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2 +\gwdc.wr_data_count_i[3]_i_6\: unisim.vcomponents.LUT5 generic map( - INIT => X"9" + INIT => X"2BD4D42B" ) port map ( - I0 => \^q\(7), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(7), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(6), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(6), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(5), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(5), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(4), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(4), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(7), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(7), - I2 => \^q\(6), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(6), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(6), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(6), - I2 => \^q\(5), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(5), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(5), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(5), - I2 => \^q\(4), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(4), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(4), - I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(4), - I2 => \^q\(3), - I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(3), - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0\, - CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1\, - CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2\, - CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3\, - CYINIT => '0', - DI(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0\, - DI(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0\, - DI(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_4_n_0\, - DI(0) => '0', - O(3 downto 0) => D(3 downto 0), - S(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0\, - S(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0\, - S(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_7_n_0\, - S(0) => S(0) - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0\, - CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0\, - CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1\, - CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2\, - CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3\, - CYINIT => '0', - DI(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0\, - DI(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0\, - DI(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0\, - DI(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0\, - O(3 downto 0) => D(7 downto 4), - S(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0\, - S(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0\, - S(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0\, - S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0\ - ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0\, - CO(3 downto 0) => \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED\(3 downto 0), - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3 downto 1) => \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED\(3 downto 1), - O(0) => D(8), - S(3 downto 1) => B"000", - S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\(0) - ); -\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[0]\, - O => \^e\(0) + I0 => \^q\(1), + I1 => \grdc.rd_data_count_i_reg[3]\(0), + I2 => \grdc.rd_data_count_i_reg[12]\(1), + I3 => \^q\(2), + I4 => \grdc.rd_data_count_i_reg[12]\(2), + O => \count_value_i_reg[1]_1\(0) ); end STRUCTURE; library IEEE; @@ -1757,20 +1570,24 @@ use UNISIM.VCOMPONENTS.ALL; entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0\ is port ( ram_empty_i0 : out STD_LOGIC; - CO : out STD_LOGIC_VECTOR ( 0 to 0 ); - Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); - D : out STD_LOGIC_VECTOR ( 9 downto 0 ); - \count_value_i_reg[8]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_empty_i : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \count_value_i_reg[10]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC; - \gen_pntr_flags_cc.ram_empty_i_reg_0\ : in STD_LOGIC; - \gen_pntr_flags_cc.ram_empty_i_reg_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \grdc.rd_data_count_i_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); - DI : in STD_LOGIC_VECTOR ( 0 to 0 ); - S : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \count_value_i_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_wr_en_pf : in STD_LOGIC; + ram_empty_i : in STD_LOGIC; + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + DI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \grdc.rd_data_count_i_reg[12]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grdc.rd_data_count_i_reg[11]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \count_value_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -1778,29 +1595,61 @@ entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0\ is end \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0\; architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0\ is - signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[9]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[9]_i_2__0_n_0\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[9]\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_3\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \count_value_i_reg[11]_i_1_n_0\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1_n_4\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1_n_5\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1_n_6\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1_n_7\ : STD_LOGIC; + signal \count_value_i_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_4\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_5\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_6\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1_n_7\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_3\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_4\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_5\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_6\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1_n_7\ : STD_LOGIC; + signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.ram_empty_i_i_6_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC; + signal going_empty1 : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_2_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_3_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_4_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_5_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_6_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_7_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_8_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i[11]_i_9_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[3]_i_2_n_0\ : STD_LOGIC; - signal \gwdc.wr_data_count_i[3]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[3]_i_5_n_0\ : STD_LOGIC; - signal \gwdc.wr_data_count_i[3]_i_6_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC; @@ -1809,9 +1658,10 @@ architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__paramete signal \gwdc.wr_data_count_i[7]_i_7_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_8_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_9_n_0\ : STD_LOGIC; - signal \gwdc.wr_data_count_i[9]_i_2_n_0\ : STD_LOGIC; - signal \gwdc.wr_data_count_i[9]_i_3_n_0\ : STD_LOGIC; - signal \gwdc.wr_data_count_i[9]_i_4_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i_reg[11]_i_1_n_0\ : STD_LOGIC; + signal \gwdc.wr_data_count_i_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \gwdc.wr_data_count_i_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \gwdc.wr_data_count_i_reg[11]_i_1_n_3\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[3]_i_1_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[3]_i_1_n_1\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[3]_i_1_n_2\ : STD_LOGIC; @@ -1820,158 +1670,99 @@ architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__paramete signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; - signal \gwdc.wr_data_count_i_reg[9]_i_1_n_3\ : STD_LOGIC; - signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \count_value_i[0]_i_1__1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \count_value_i[1]_i_1__3\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \count_value_i[5]_i_1__3\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \count_value_i[6]_i_1__3\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \count_value_i[7]_i_1__3\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \count_value_i[8]_i_1__1\ : label is "soft_lutpair9"; + signal \NLW_count_value_i_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_count_value_i_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gwdc.wr_data_count_i_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gwdc.wr_data_count_i_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \count_value_i_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[12]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[3]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[7]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1\ : label is 35; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[12]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[3]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35; - attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[9]_i_1\ : label is 35; begin - CO(0) <= \^co\(0); - Q(8 downto 0) <= \^q\(8 downto 0); -\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(0), - O => \count_value_i[0]_i_1__1_n_0\ - ); -\count_value_i[1]_i_1__3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^q\(1), - I1 => \^q\(0), - O => \count_value_i[1]_i_1__3_n_0\ - ); -\count_value_i[2]_i_1__3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"DF20" - ) - port map ( - I0 => \^q\(0), - I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\, - I2 => \^q\(1), - I3 => \^q\(2), - O => \count_value_i[2]_i_1__3_n_0\ - ); -\count_value_i[3]_i_1__3\: unisim.vcomponents.LUT5 - generic map( - INIT => X"DF20FF00" - ) - port map ( - I0 => \^q\(0), - I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\, - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(2), - O => \count_value_i[3]_i_1__3_n_0\ - ); -\count_value_i[4]_i_1__3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DF20FF00FF00FF00" - ) - port map ( - I0 => \^q\(0), - I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\, - I2 => \^q\(1), - I3 => \^q\(4), - I4 => \^q\(3), - I5 => \^q\(2), - O => \count_value_i[4]_i_1__3_n_0\ - ); -\count_value_i[5]_i_1__3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(5), - I1 => \count_value_i[9]_i_2__0_n_0\, - O => \count_value_i[5]_i_1__3_n_0\ - ); -\count_value_i[6]_i_1__3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"A6" - ) - port map ( - I0 => \^q\(6), - I1 => \^q\(5), - I2 => \count_value_i[9]_i_2__0_n_0\, - O => \count_value_i[6]_i_1__3_n_0\ - ); -\count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"A6AA" - ) - port map ( - I0 => \^q\(7), - I1 => \^q\(6), - I2 => \count_value_i[9]_i_2__0_n_0\, - I3 => \^q\(5), - O => \count_value_i[7]_i_1__3_n_0\ - ); -\count_value_i[8]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"A6AAAAAA" - ) - port map ( - I0 => \^q\(8), - I1 => \^q\(5), - I2 => \count_value_i[9]_i_2__0_n_0\, - I3 => \^q\(6), - I4 => \^q\(7), - O => \count_value_i[8]_i_1__1_n_0\ - ); -\count_value_i[9]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AA6AAAAAAAAAAAAA" - ) - port map ( - I0 => \count_value_i_reg_n_0_[9]\, - I1 => \^q\(7), - I2 => \^q\(6), - I3 => \count_value_i[9]_i_2__0_n_0\, - I4 => \^q\(5), - I5 => \^q\(8), - O => \count_value_i[9]_i_1__0_n_0\ - ); -\count_value_i[9]_i_2__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DFFFFFFFFFFFFFFF" - ) - port map ( - I0 => \^q\(0), - I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\, - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(2), - I5 => \^q\(4), - O => \count_value_i[9]_i_2__0_n_0\ - ); + Q(12 downto 0) <= \^q\(12 downto 0); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[0]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1_n_7\, Q => \^q\(0), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) + ); +\count_value_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1_n_5\, + Q => \^q\(10), + R => \count_value_i_reg[12]_0\(0) + ); +\count_value_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1_n_4\, + Q => \^q\(11), + R => \count_value_i_reg[12]_0\(0) + ); +\count_value_i_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[7]_i_1_n_0\, + CO(3) => \count_value_i_reg[11]_i_1_n_0\, + CO(2) => \count_value_i_reg[11]_i_1_n_1\, + CO(1) => \count_value_i_reg[11]_i_1_n_2\, + CO(0) => \count_value_i_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[11]_i_1_n_4\, + O(2) => \count_value_i_reg[11]_i_1_n_5\, + O(1) => \count_value_i_reg[11]_i_1_n_6\, + O(0) => \count_value_i_reg[11]_i_1_n_7\, + S(3 downto 0) => \^q\(11 downto 8) + ); +\count_value_i_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[12]_i_1_n_7\, + Q => \^q\(12), + R => \count_value_i_reg[12]_0\(0) + ); +\count_value_i_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[11]_i_1_n_0\, + CO(3 downto 0) => \NLW_count_value_i_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_count_value_i_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), + O(0) => \count_value_i_reg[12]_i_1_n_7\, + S(3 downto 1) => B"000", + S(0) => \^q\(12) ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -1979,10 +1770,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[1]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1_n_6\, Q => \^q\(1), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -1990,10 +1781,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[2]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1_n_5\, Q => \^q\(2), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( @@ -2001,10 +1792,27 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[3]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1_n_4\, Q => \^q\(3), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) + ); +\count_value_i_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \count_value_i_reg[3]_i_1_n_0\, + CO(2) => \count_value_i_reg[3]_i_1_n_1\, + CO(1) => \count_value_i_reg[3]_i_1_n_2\, + CO(0) => \count_value_i_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \^q\(0), + O(3) => \count_value_i_reg[3]_i_1_n_4\, + O(2) => \count_value_i_reg[3]_i_1_n_5\, + O(1) => \count_value_i_reg[3]_i_1_n_6\, + O(0) => \count_value_i_reg[3]_i_1_n_7\, + S(3 downto 1) => \^q\(3 downto 1), + S(0) => S(0) ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( @@ -2012,10 +1820,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[4]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1_n_7\, Q => \^q\(4), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( @@ -2023,10 +1831,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[5]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1_n_6\, Q => \^q\(5), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( @@ -2034,10 +1842,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[6]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1_n_5\, Q => \^q\(6), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( @@ -2045,10 +1853,25 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[7]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1_n_4\, Q => \^q\(7), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) + ); +\count_value_i_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[3]_i_1_n_0\, + CO(3) => \count_value_i_reg[7]_i_1_n_0\, + CO(2) => \count_value_i_reg[7]_i_1_n_1\, + CO(1) => \count_value_i_reg[7]_i_1_n_2\, + CO(0) => \count_value_i_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[7]_i_1_n_4\, + O(2) => \count_value_i_reg[7]_i_1_n_5\, + O(1) => \count_value_i_reg[7]_i_1_n_6\, + O(0) => \count_value_i_reg[7]_i_1_n_7\, + S(3 downto 0) => \^q\(7 downto 4) ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( @@ -2056,10 +1879,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[8]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1_n_7\, Q => \^q\(8), - R => \count_value_i_reg[9]_0\(0) + R => \count_value_i_reg[12]_0\(0) ); \count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( @@ -2067,237 +1890,336 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[9]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[9]\, - R => \count_value_i_reg[9]_0\(0) - ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9009000000009009" - ) - port map ( - I0 => \^q\(7), - I1 => \grdc.rd_data_count_i_reg[9]\(7), - I2 => \^q\(6), - I3 => \grdc.rd_data_count_i_reg[9]\(6), - I4 => \^q\(8), - I5 => \grdc.rd_data_count_i_reg[9]\(8), - O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\ - ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9009000000009009" - ) - port map ( - I0 => \^q\(5), - I1 => \grdc.rd_data_count_i_reg[9]\(5), - I2 => \^q\(3), - I3 => \grdc.rd_data_count_i_reg[9]\(3), - I4 => \^q\(4), - I5 => \grdc.rd_data_count_i_reg[9]\(4), - O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\ - ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9009000000009009" - ) - port map ( - I0 => \^q\(2), - I1 => \grdc.rd_data_count_i_reg[9]\(2), - I2 => \grdc.rd_data_count_i_reg[9]\(1), - I3 => \^q\(1), - I4 => \^q\(0), - I5 => \grdc.rd_data_count_i_reg[9]\(0), - O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\ - ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_CO_UNCONNECTED\(3), - CO(2) => \^co\(0), - CO(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_2\, - CO(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_3\, - CYINIT => '1', - DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_O_UNCONNECTED\(3 downto 0), - S(3) => '0', - S(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\, - S(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\, - S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\ + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1_n_6\, + Q => \^q\(9), + R => \count_value_i_reg[12]_0\(0) ); \gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"CF44CC44" + INIT => X"0FFF0088" ) port map ( - I0 => \^co\(0), - I1 => ram_empty_i, - I2 => \gen_pntr_flags_cc.ram_empty_i_reg\, - I3 => \gen_pntr_flags_cc.ram_empty_i_reg_0\, - I4 => \gen_pntr_flags_cc.ram_empty_i_reg_1\(0), + I0 => \gen_pntr_flags_cc.ram_empty_i_reg\, + I1 => going_empty1, + I2 => CO(0), + I3 => ram_wr_en_pf, + I4 => ram_empty_i, O => ram_empty_i0 ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[8]_i_2\: unisim.vcomponents.LUT2 +\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"9" + INIT => X"9009000000009009" ) port map ( - I0 => \^q\(8), - I1 => \grdc.rd_data_count_i_reg[9]\(8), - O => \count_value_i_reg[8]_0\(0) + I0 => \^q\(9), + I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(9), + I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(11), + I3 => \^q\(11), + I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(10), + I5 => \^q\(10), + O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ ); -\gwdc.wr_data_count_i[3]_i_2\: unisim.vcomponents.LUT2 +\gen_pntr_flags_cc.ram_empty_i_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(3), - I1 => \grdc.rd_data_count_i_reg[9]\(3), - O => \gwdc.wr_data_count_i[3]_i_2_n_0\ - ); -\gwdc.wr_data_count_i[3]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(2), - I1 => \grdc.rd_data_count_i_reg[9]\(2), - O => \gwdc.wr_data_count_i[3]_i_3_n_0\ - ); -\gwdc.wr_data_count_i[3]_i_5\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(3), - I1 => \grdc.rd_data_count_i_reg[9]\(3), - I2 => \grdc.rd_data_count_i_reg[9]\(2), - I3 => \^q\(2), - O => \gwdc.wr_data_count_i[3]_i_5_n_0\ - ); -\gwdc.wr_data_count_i[3]_i_6\: unisim.vcomponents.LUT5 - generic map( - INIT => X"69669969" - ) - port map ( - I0 => \^q\(2), - I1 => \grdc.rd_data_count_i_reg[9]\(2), - I2 => \^q\(1), - I3 => \grdc.rd_data_count_i_reg[9]\(1), - I4 => \grdc.rd_data_count_i_reg[3]\(0), - O => \gwdc.wr_data_count_i[3]_i_6_n_0\ - ); -\gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(7), - I1 => \grdc.rd_data_count_i_reg[9]\(7), - O => \gwdc.wr_data_count_i[7]_i_2_n_0\ - ); -\gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" + INIT => X"9009000000009009" ) port map ( I0 => \^q\(6), - I1 => \grdc.rd_data_count_i_reg[9]\(6), - O => \gwdc.wr_data_count_i[7]_i_3_n_0\ + I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(6), + I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(8), + I3 => \^q\(8), + I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(7), + I5 => \^q\(7), + O => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\ ); -\gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 +\gen_pntr_flags_cc.ram_empty_i_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"9" + INIT => X"9009000000009009" ) port map ( - I0 => \^q\(5), - I1 => \grdc.rd_data_count_i_reg[9]\(5), - O => \gwdc.wr_data_count_i[7]_i_4_n_0\ - ); -\gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(4), - I1 => \grdc.rd_data_count_i_reg[9]\(4), - O => \gwdc.wr_data_count_i[7]_i_5_n_0\ - ); -\gwdc.wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(7), - I1 => \grdc.rd_data_count_i_reg[9]\(7), - I2 => \grdc.rd_data_count_i_reg[9]\(6), - I3 => \^q\(6), - O => \gwdc.wr_data_count_i[7]_i_6_n_0\ - ); -\gwdc.wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9699" - ) - port map ( - I0 => \^q\(6), - I1 => \grdc.rd_data_count_i_reg[9]\(6), - I2 => \grdc.rd_data_count_i_reg[9]\(5), + I0 => \^q\(3), + I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(3), + I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(5), I3 => \^q\(5), - O => \gwdc.wr_data_count_i[7]_i_7_n_0\ + I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(4), + I5 => \^q\(4), + O => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\ ); -\gwdc.wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT4 +\gen_pntr_flags_cc.ram_empty_i_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"9699" + INIT => X"9009000000009009" ) port map ( - I0 => \^q\(5), - I1 => \grdc.rd_data_count_i_reg[9]\(5), - I2 => \grdc.rd_data_count_i_reg[9]\(4), - I3 => \^q\(4), - O => \gwdc.wr_data_count_i[7]_i_8_n_0\ + I0 => \^q\(0), + I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(0), + I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(2), + I3 => \^q\(2), + I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(1), + I5 => \^q\(1), + O => \gen_pntr_flags_cc.ram_empty_i_i_6_n_0\ ); -\gwdc.wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT4 +\gen_pntr_flags_cc.ram_empty_i_reg_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => going_empty1, + CO(2) => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_1\, + CO(1) => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2\, + CO(0) => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3\, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED\(3 downto 0), + S(3) => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\, + S(2) => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\, + S(1) => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\, + S(0) => \gen_pntr_flags_cc.ram_empty_i_i_6_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0\, + CO(3) => \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_CO_UNCONNECTED\(3), + CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_1\, + CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_2\, + CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => \^q\(10 downto 8), + O(3 downto 0) => \count_value_i_reg[10]_0\(11 downto 8), + S(3 downto 0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]\(3 downto 0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0\, + CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_1\, + CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_2\, + CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_3\, + CYINIT => \^q\(0), + DI(3 downto 1) => \^q\(3 downto 1), + DI(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\(0), + O(3 downto 0) => \count_value_i_reg[10]_0\(3 downto 0), + S(3 downto 0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0\(3 downto 0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_i_1_n_0\, + CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_0\, + CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_1\, + CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_2\, + CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^q\(7 downto 4), + O(3 downto 0) => \count_value_i_reg[10]_0\(7 downto 4), + S(3 downto 0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(3 downto 0) + ); +\gwdc.wr_data_count_i[11]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"9699" + INIT => X"2" ) port map ( - I0 => \^q\(4), - I1 => \grdc.rd_data_count_i_reg[9]\(4), - I2 => \grdc.rd_data_count_i_reg[9]\(3), - I3 => \^q\(3), - O => \gwdc.wr_data_count_i[7]_i_9_n_0\ + I0 => \^q\(10), + I1 => \grdc.rd_data_count_i_reg[11]\(8), + O => \gwdc.wr_data_count_i[11]_i_2_n_0\ ); -\gwdc.wr_data_count_i[9]_i_2\: unisim.vcomponents.LUT2 +\gwdc.wr_data_count_i[11]_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"9" + INIT => X"2" + ) + port map ( + I0 => \^q\(9), + I1 => \grdc.rd_data_count_i_reg[11]\(7), + O => \gwdc.wr_data_count_i[11]_i_3_n_0\ + ); +\gwdc.wr_data_count_i[11]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" ) port map ( I0 => \^q\(8), - I1 => \grdc.rd_data_count_i_reg[9]\(8), - O => \gwdc.wr_data_count_i[9]_i_2_n_0\ + I1 => \grdc.rd_data_count_i_reg[11]\(6), + O => \gwdc.wr_data_count_i[11]_i_4_n_0\ ); -\gwdc.wr_data_count_i[9]_i_3\: unisim.vcomponents.LUT4 +\gwdc.wr_data_count_i[11]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(7), + I1 => \grdc.rd_data_count_i_reg[11]\(5), + O => \gwdc.wr_data_count_i[11]_i_5_n_0\ + ); +\gwdc.wr_data_count_i[11]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(10), + I1 => \grdc.rd_data_count_i_reg[11]\(8), + I2 => \grdc.rd_data_count_i_reg[11]\(9), + I3 => \^q\(11), + O => \gwdc.wr_data_count_i[11]_i_6_n_0\ + ); +\gwdc.wr_data_count_i[11]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(9), + I1 => \grdc.rd_data_count_i_reg[11]\(7), + I2 => \grdc.rd_data_count_i_reg[11]\(8), + I3 => \^q\(10), + O => \gwdc.wr_data_count_i[11]_i_7_n_0\ + ); +\gwdc.wr_data_count_i[11]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => \^q\(8), - I1 => \grdc.rd_data_count_i_reg[9]\(8), - I2 => \count_value_i_reg_n_0_[9]\, - I3 => \grdc.rd_data_count_i_reg[9]\(9), - O => \gwdc.wr_data_count_i[9]_i_3_n_0\ + I1 => \grdc.rd_data_count_i_reg[11]\(6), + I2 => \grdc.rd_data_count_i_reg[11]\(7), + I3 => \^q\(9), + O => \gwdc.wr_data_count_i[11]_i_8_n_0\ ); -\gwdc.wr_data_count_i[9]_i_4\: unisim.vcomponents.LUT4 +\gwdc.wr_data_count_i[11]_i_9\: unisim.vcomponents.LUT4 generic map( - INIT => X"9699" + INIT => X"D22D" ) port map ( - I0 => \^q\(8), - I1 => \grdc.rd_data_count_i_reg[9]\(8), - I2 => \grdc.rd_data_count_i_reg[9]\(7), + I0 => \^q\(7), + I1 => \grdc.rd_data_count_i_reg[11]\(5), + I2 => \grdc.rd_data_count_i_reg[11]\(6), + I3 => \^q\(8), + O => \gwdc.wr_data_count_i[11]_i_9_n_0\ + ); +\gwdc.wr_data_count_i[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(2), + I1 => \grdc.rd_data_count_i_reg[11]\(0), + O => \gwdc.wr_data_count_i[3]_i_2_n_0\ + ); +\gwdc.wr_data_count_i[3]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(2), + I1 => \grdc.rd_data_count_i_reg[11]\(0), + I2 => \grdc.rd_data_count_i_reg[11]\(1), + I3 => \^q\(3), + O => \gwdc.wr_data_count_i[3]_i_5_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(6), + I1 => \grdc.rd_data_count_i_reg[11]\(4), + O => \gwdc.wr_data_count_i[7]_i_2_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(5), + I1 => \grdc.rd_data_count_i_reg[11]\(3), + O => \gwdc.wr_data_count_i[7]_i_3_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(4), + I1 => \grdc.rd_data_count_i_reg[11]\(2), + O => \gwdc.wr_data_count_i[7]_i_4_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(3), + I1 => \grdc.rd_data_count_i_reg[11]\(1), + O => \gwdc.wr_data_count_i[7]_i_5_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(6), + I1 => \grdc.rd_data_count_i_reg[11]\(4), + I2 => \grdc.rd_data_count_i_reg[11]\(5), I3 => \^q\(7), - O => \gwdc.wr_data_count_i[9]_i_4_n_0\ + O => \gwdc.wr_data_count_i[7]_i_6_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(5), + I1 => \grdc.rd_data_count_i_reg[11]\(3), + I2 => \grdc.rd_data_count_i_reg[11]\(4), + I3 => \^q\(6), + O => \gwdc.wr_data_count_i[7]_i_7_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(4), + I1 => \grdc.rd_data_count_i_reg[11]\(2), + I2 => \grdc.rd_data_count_i_reg[11]\(3), + I3 => \^q\(5), + O => \gwdc.wr_data_count_i[7]_i_8_n_0\ + ); +\gwdc.wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(3), + I1 => \grdc.rd_data_count_i_reg[11]\(1), + I2 => \grdc.rd_data_count_i_reg[11]\(2), + I3 => \^q\(4), + O => \gwdc.wr_data_count_i[7]_i_9_n_0\ + ); +\gwdc.wr_data_count_i_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, + CO(3) => \gwdc.wr_data_count_i_reg[11]_i_1_n_0\, + CO(2) => \gwdc.wr_data_count_i_reg[11]_i_1_n_1\, + CO(1) => \gwdc.wr_data_count_i_reg[11]_i_1_n_2\, + CO(0) => \gwdc.wr_data_count_i_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3) => \gwdc.wr_data_count_i[11]_i_2_n_0\, + DI(2) => \gwdc.wr_data_count_i[11]_i_3_n_0\, + DI(1) => \gwdc.wr_data_count_i[11]_i_4_n_0\, + DI(0) => \gwdc.wr_data_count_i[11]_i_5_n_0\, + O(3 downto 0) => D(11 downto 8), + S(3) => \gwdc.wr_data_count_i[11]_i_6_n_0\, + S(2) => \gwdc.wr_data_count_i[11]_i_7_n_0\, + S(1) => \gwdc.wr_data_count_i[11]_i_8_n_0\, + S(0) => \gwdc.wr_data_count_i[11]_i_9_n_0\ + ); +\gwdc.wr_data_count_i_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gwdc.wr_data_count_i_reg[11]_i_1_n_0\, + CO(3 downto 0) => \NLW_gwdc.wr_data_count_i_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_gwdc.wr_data_count_i_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), + O(0) => D(12), + S(3 downto 1) => B"000", + S(0) => \grdc.rd_data_count_i_reg[12]\(0) ); \gwdc.wr_data_count_i_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( @@ -2308,13 +2230,11 @@ begin CO(0) => \gwdc.wr_data_count_i_reg[3]_i_1_n_3\, CYINIT => '0', DI(3) => \gwdc.wr_data_count_i[3]_i_2_n_0\, - DI(2) => \gwdc.wr_data_count_i[3]_i_3_n_0\, - DI(1) => DI(0), + DI(2 downto 1) => DI(1 downto 0), DI(0) => \^q\(0), O(3 downto 0) => D(3 downto 0), S(3) => \gwdc.wr_data_count_i[3]_i_5_n_0\, - S(2) => \gwdc.wr_data_count_i[3]_i_6_n_0\, - S(1 downto 0) => S(1 downto 0) + S(2 downto 0) => \grdc.rd_data_count_i_reg[3]\(2 downto 0) ); \gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( @@ -2334,20 +2254,6 @@ begin S(1) => \gwdc.wr_data_count_i[7]_i_8_n_0\, S(0) => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); -\gwdc.wr_data_count_i_reg[9]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, - CO(3 downto 1) => \NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED\(3 downto 1), - CO(0) => \gwdc.wr_data_count_i_reg[9]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 1) => B"000", - DI(0) => \gwdc.wr_data_count_i[9]_i_2_n_0\, - O(3 downto 2) => \NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED\(3 downto 2), - O(1 downto 0) => D(9 downto 8), - S(3 downto 2) => B"00", - S(1) => \gwdc.wr_data_count_i[9]_i_3_n_0\, - S(0) => \gwdc.wr_data_count_i[9]_i_4_n_0\ - ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -2355,11 +2261,9 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3\ is port ( - CO : out STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 8 downto 0 ); - \count_value_i_reg[4]_0\ : in STD_LOGIC; - \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \count_value_i_reg[0]_0\ : in STD_LOGIC; + \count_value_i_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -2367,149 +2271,46 @@ entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3\ is end \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3\; architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3\ is - signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC; - signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[5]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[6]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[7]\ : STD_LOGIC; - signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC; - signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\ : STD_LOGIC; - signal \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2\ : STD_LOGIC; - signal \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3\ : STD_LOGIC; - signal \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \count_value_i[0]_i_1__4\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \count_value_i[1]_i_1__2\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \count_value_i[5]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \count_value_i[6]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \count_value_i[7]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair5"; + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \count_value_i[3]_i_2__1_n_0\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__1_n_1\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__1_n_2\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__1_n_3\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__1_n_4\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__1_n_5\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__1_n_6\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__1_n_7\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_0\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_1\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_2\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_3\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_4\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_5\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_6\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__1_n_7\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_0\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_1\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_2\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_3\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_4\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_5\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_6\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__1_n_7\ : STD_LOGIC; + signal \NLW_count_value_i_reg[11]_i_1__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \count_value_i_reg[11]_i_1__1\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[3]_i_1__1\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[7]_i_1__1\ : label is 35; begin -\count_value_i[0]_i_1__4\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - O => \count_value_i[0]_i_1__4_n_0\ - ); -\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT2 + Q(11 downto 0) <= \^q\(11 downto 0); +\count_value_i[3]_i_2__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( - I0 => \count_value_i_reg_n_0_[1]\, - I1 => \count_value_i_reg_n_0_[0]\, - O => \count_value_i[1]_i_1__2_n_0\ - ); -\count_value_i[2]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"DF20" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[2]\, - O => \count_value_i[2]_i_1_n_0\ - ); -\count_value_i[3]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"DF20FF00" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[3]\, - I4 => \count_value_i_reg_n_0_[2]\, - O => \count_value_i[3]_i_1_n_0\ - ); -\count_value_i[4]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DFFFFFFF20000000" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[2]\, - I4 => \count_value_i_reg_n_0_[3]\, - I5 => \count_value_i_reg_n_0_[4]\, - O => \count_value_i[4]_i_1_n_0\ - ); -\count_value_i[5]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \count_value_i_reg_n_0_[5]\, - I1 => \count_value_i[8]_i_2_n_0\, - O => \count_value_i[5]_i_1_n_0\ - ); -\count_value_i[6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"6A" - ) - port map ( - I0 => \count_value_i_reg_n_0_[6]\, - I1 => \count_value_i[8]_i_2_n_0\, - I2 => \count_value_i_reg_n_0_[5]\, - O => \count_value_i[6]_i_1_n_0\ - ); -\count_value_i[7]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6AAA" - ) - port map ( - I0 => \count_value_i_reg_n_0_[7]\, - I1 => \count_value_i_reg_n_0_[5]\, - I2 => \count_value_i[8]_i_2_n_0\, - I3 => \count_value_i_reg_n_0_[6]\, - O => \count_value_i[7]_i_1_n_0\ - ); -\count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"6AAAAAAA" - ) - port map ( - I0 => \count_value_i_reg_n_0_[8]\, - I1 => \count_value_i_reg_n_0_[6]\, - I2 => \count_value_i[8]_i_2_n_0\, - I3 => \count_value_i_reg_n_0_[5]\, - I4 => \count_value_i_reg_n_0_[7]\, - O => \count_value_i[8]_i_1__0_n_0\ - ); -\count_value_i[8]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"2000000000000000" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => \count_value_i_reg[4]_0\, - I2 => \count_value_i_reg_n_0_[1]\, - I3 => \count_value_i_reg_n_0_[4]\, - I4 => \count_value_i_reg_n_0_[3]\, - I5 => \count_value_i_reg_n_0_[2]\, - O => \count_value_i[8]_i_2_n_0\ + I0 => \count_value_i_reg[0]_0\, + I1 => \^q\(0), + O => \count_value_i[3]_i_2__1_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( @@ -2517,10 +2318,47 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[0]_i_1__4_n_0\, - Q => \count_value_i_reg_n_0_[0]\, - S => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[3]_i_1__1_n_7\, + Q => \^q\(0), + S => \count_value_i_reg[0]_1\(0) + ); +\count_value_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[11]_i_1__1_n_5\, + Q => \^q\(10), + R => \count_value_i_reg[0]_1\(0) + ); +\count_value_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[11]_i_1__1_n_4\, + Q => \^q\(11), + R => \count_value_i_reg[0]_1\(0) + ); +\count_value_i_reg[11]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[7]_i_1__1_n_0\, + CO(3) => \NLW_count_value_i_reg[11]_i_1__1_CO_UNCONNECTED\(3), + CO(2) => \count_value_i_reg[11]_i_1__1_n_1\, + CO(1) => \count_value_i_reg[11]_i_1__1_n_2\, + CO(0) => \count_value_i_reg[11]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[11]_i_1__1_n_4\, + O(2) => \count_value_i_reg[11]_i_1__1_n_5\, + O(1) => \count_value_i_reg[11]_i_1__1_n_6\, + O(0) => \count_value_i_reg[11]_i_1__1_n_7\, + S(3 downto 0) => \^q\(11 downto 8) ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -2528,10 +2366,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[1]_i_1__2_n_0\, - Q => \count_value_i_reg_n_0_[1]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[3]_i_1__1_n_6\, + Q => \^q\(1), + R => \count_value_i_reg[0]_1\(0) ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -2539,10 +2377,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[2]_i_1_n_0\, - Q => \count_value_i_reg_n_0_[2]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[3]_i_1__1_n_5\, + Q => \^q\(2), + R => \count_value_i_reg[0]_1\(0) ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( @@ -2550,10 +2388,27 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[3]_i_1_n_0\, - Q => \count_value_i_reg_n_0_[3]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[3]_i_1__1_n_4\, + Q => \^q\(3), + R => \count_value_i_reg[0]_1\(0) + ); +\count_value_i_reg[3]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \count_value_i_reg[3]_i_1__1_n_0\, + CO(2) => \count_value_i_reg[3]_i_1__1_n_1\, + CO(1) => \count_value_i_reg[3]_i_1__1_n_2\, + CO(0) => \count_value_i_reg[3]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \^q\(0), + O(3) => \count_value_i_reg[3]_i_1__1_n_4\, + O(2) => \count_value_i_reg[3]_i_1__1_n_5\, + O(1) => \count_value_i_reg[3]_i_1__1_n_6\, + O(0) => \count_value_i_reg[3]_i_1__1_n_7\, + S(3 downto 1) => \^q\(3 downto 1), + S(0) => \count_value_i[3]_i_2__1_n_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( @@ -2561,10 +2416,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[4]_i_1_n_0\, - Q => \count_value_i_reg_n_0_[4]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[7]_i_1__1_n_7\, + Q => \^q\(4), + R => \count_value_i_reg[0]_1\(0) ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( @@ -2572,10 +2427,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[5]_i_1_n_0\, - Q => \count_value_i_reg_n_0_[5]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[7]_i_1__1_n_6\, + Q => \^q\(5), + R => \count_value_i_reg[0]_1\(0) ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( @@ -2583,10 +2438,10 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[6]_i_1_n_0\, - Q => \count_value_i_reg_n_0_[6]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[7]_i_1__1_n_5\, + Q => \^q\(6), + R => \count_value_i_reg[0]_1\(0) ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( @@ -2594,10 +2449,25 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[7]_i_1_n_0\, - Q => \count_value_i_reg_n_0_[7]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[7]_i_1__1_n_4\, + Q => \^q\(7), + R => \count_value_i_reg[0]_1\(0) + ); +\count_value_i_reg[7]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[3]_i_1__1_n_0\, + CO(3) => \count_value_i_reg[7]_i_1__1_n_0\, + CO(2) => \count_value_i_reg[7]_i_1__1_n_1\, + CO(1) => \count_value_i_reg[7]_i_1__1_n_2\, + CO(0) => \count_value_i_reg[7]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[7]_i_1__1_n_4\, + O(2) => \count_value_i_reg[7]_i_1__1_n_5\, + O(1) => \count_value_i_reg[7]_i_1__1_n_6\, + O(0) => \count_value_i_reg[7]_i_1__1_n_7\, + S(3 downto 0) => \^q\(7 downto 4) ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( @@ -2605,64 +2475,21 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[8]_i_1__0_n_0\, - Q => \count_value_i_reg_n_0_[8]\, - R => \count_value_i_reg[0]_0\(0) + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[11]_i_1__1_n_7\, + Q => \^q\(8), + R => \count_value_i_reg[0]_1\(0) ); -\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT6 +\count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"9009000000009009" + INIT => '0' ) port map ( - I0 => \count_value_i_reg_n_0_[7]\, - I1 => Q(7), - I2 => Q(8), - I3 => \count_value_i_reg_n_0_[8]\, - I4 => Q(6), - I5 => \count_value_i_reg_n_0_[6]\, - O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ - ); -\gen_pntr_flags_cc.ram_empty_i_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9009000000009009" - ) - port map ( - I0 => \count_value_i_reg_n_0_[3]\, - I1 => Q(3), - I2 => Q(5), - I3 => \count_value_i_reg_n_0_[5]\, - I4 => Q(4), - I5 => \count_value_i_reg_n_0_[4]\, - O => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\ - ); -\gen_pntr_flags_cc.ram_empty_i_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9009000000009009" - ) - port map ( - I0 => \count_value_i_reg_n_0_[0]\, - I1 => Q(0), - I2 => Q(2), - I3 => \count_value_i_reg_n_0_[2]\, - I4 => Q(1), - I5 => \count_value_i_reg_n_0_[1]\, - O => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\ - ); -\gen_pntr_flags_cc.ram_empty_i_reg_i_2\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_CO_UNCONNECTED\(3), - CO(2) => CO(0), - CO(1) => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_2\, - CO(0) => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_n_3\, - CYINIT => '1', - DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED\(3 downto 0), - S(3) => '0', - S(2) => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\, - S(1) => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\, - S(0) => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\ + C => wr_clk, + CE => \count_value_i_reg[0]_0\, + D => \count_value_i_reg[11]_i_1__1_n_6\, + Q => \^q\(9), + R => \count_value_i_reg[0]_1\(0) ); end STRUCTURE; library IEEE; @@ -2671,14 +2498,16 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3_1\ is port ( - Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); - \count_value_i_reg[8]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - S : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\ : in STD_LOGIC; - \count_value_i_reg[4]_0\ : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + DI : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); + ram_wr_en_pf : in STD_LOGIC; + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0\ : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -2686,155 +2515,127 @@ entity \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3_1\ is end \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3_1\; architecture STRUCTURE of \design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3_1\ is - signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC; - signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC; - signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_1__3_n_0\ : STD_LOGIC; - signal \count_value_i[8]_i_2__1_n_0\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \count_value_i[0]_i_1__2\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \count_value_i[5]_i_1__1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \count_value_i[6]_i_1__1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \count_value_i[8]_i_1__3\ : label is "soft_lutpair13"; + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \count_value_i_reg[11]_i_1__2_n_1\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__2_n_2\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__2_n_3\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__2_n_4\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__2_n_5\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__2_n_6\ : STD_LOGIC; + signal \count_value_i_reg[11]_i_1__2_n_7\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_0\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_1\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_2\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_3\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_4\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_5\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_6\ : STD_LOGIC; + signal \count_value_i_reg[3]_i_1__2_n_7\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_0\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_1\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_2\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_3\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_4\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_5\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_6\ : STD_LOGIC; + signal \count_value_i_reg[7]_i_1__2_n_7\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \NLW_count_value_i_reg[11]_i_1__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \count_value_i_reg[11]_i_1__2\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[3]_i_1__2\ : label is 35; + attribute ADDER_THRESHOLD of \count_value_i_reg[7]_i_1__2\ : label is 35; + attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1\ : label is 35; begin - Q(8 downto 0) <= \^q\(8 downto 0); -\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(0), - O => \count_value_i[0]_i_1__2_n_0\ - ); -\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^q\(1), - I1 => \^q\(0), - O => \count_value_i[1]_i_1__0_n_0\ - ); -\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"DF20" - ) - port map ( - I0 => \^q\(0), - I1 => \count_value_i_reg[4]_0\, - I2 => \^q\(1), - I3 => \^q\(2), - O => \count_value_i[2]_i_1__1_n_0\ - ); -\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"DF20FF00" - ) - port map ( - I0 => \^q\(0), - I1 => \count_value_i_reg[4]_0\, - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(2), - O => \count_value_i[3]_i_1__1_n_0\ - ); -\count_value_i[4]_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DF20FF00FF00FF00" - ) - port map ( - I0 => \^q\(0), - I1 => \count_value_i_reg[4]_0\, - I2 => \^q\(1), - I3 => \^q\(4), - I4 => \^q\(2), - I5 => \^q\(3), - O => \count_value_i[4]_i_1__1_n_0\ - ); -\count_value_i[5]_i_1__1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \count_value_i[8]_i_2__1_n_0\, - I1 => \^q\(5), - O => \count_value_i[5]_i_1__1_n_0\ - ); -\count_value_i[6]_i_1__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"9A" - ) - port map ( - I0 => \^q\(6), - I1 => \count_value_i[8]_i_2__1_n_0\, - I2 => \^q\(5), - O => \count_value_i[6]_i_1__1_n_0\ - ); -\count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"A6AA" - ) - port map ( - I0 => \^q\(7), - I1 => \^q\(5), - I2 => \count_value_i[8]_i_2__1_n_0\, - I3 => \^q\(6), - O => \count_value_i[7]_i_1__1_n_0\ - ); -\count_value_i[8]_i_1__3\: unisim.vcomponents.LUT5 - generic map( - INIT => X"A6AAAAAA" - ) - port map ( - I0 => \^q\(8), - I1 => \^q\(6), - I2 => \count_value_i[8]_i_2__1_n_0\, - I3 => \^q\(5), - I4 => \^q\(7), - O => \count_value_i[8]_i_1__3_n_0\ - ); -\count_value_i[8]_i_2__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DFFFFFFFFFFFFFFF" - ) - port map ( - I0 => \^q\(0), - I1 => \count_value_i_reg[4]_0\, - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(2), - I5 => \^q\(4), - O => \count_value_i[8]_i_2__1_n_0\ - ); + Q(11 downto 0) <= \^q\(11 downto 0); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[0]_i_1__2_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__2_n_7\, Q => \^q\(0), S => \count_value_i_reg[0]_0\(0) ); +\count_value_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__2_n_5\, + Q => \^q\(10), + R => \count_value_i_reg[0]_0\(0) + ); +\count_value_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__2_n_4\, + Q => \^q\(11), + R => \count_value_i_reg[0]_0\(0) + ); +\count_value_i_reg[11]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[7]_i_1__2_n_0\, + CO(3) => \NLW_count_value_i_reg[11]_i_1__2_CO_UNCONNECTED\(3), + CO(2) => \count_value_i_reg[11]_i_1__2_n_1\, + CO(1) => \count_value_i_reg[11]_i_1__2_n_2\, + CO(0) => \count_value_i_reg[11]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[11]_i_1__2_n_4\, + O(2) => \count_value_i_reg[11]_i_1__2_n_5\, + O(1) => \count_value_i_reg[11]_i_1__2_n_6\, + O(0) => \count_value_i_reg[11]_i_1__2_n_7\, + S(3 downto 0) => \^q\(11 downto 8) + ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[1]_i_1__0_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__2_n_6\, Q => \^q\(1), R => \count_value_i_reg[0]_0\(0) ); @@ -2844,8 +2645,8 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[2]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__2_n_5\, Q => \^q\(2), R => \count_value_i_reg[0]_0\(0) ); @@ -2855,19 +2656,36 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[3]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[3]_i_1__2_n_4\, Q => \^q\(3), R => \count_value_i_reg[0]_0\(0) ); +\count_value_i_reg[3]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \count_value_i_reg[3]_i_1__2_n_0\, + CO(2) => \count_value_i_reg[3]_i_1__2_n_1\, + CO(1) => \count_value_i_reg[3]_i_1__2_n_2\, + CO(0) => \count_value_i_reg[3]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \^q\(0), + O(3) => \count_value_i_reg[3]_i_1__2_n_4\, + O(2) => \count_value_i_reg[3]_i_1__2_n_5\, + O(1) => \count_value_i_reg[3]_i_1__2_n_6\, + O(0) => \count_value_i_reg[3]_i_1__2_n_7\, + S(3 downto 1) => \^q\(3 downto 1), + S(0) => S(0) + ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[4]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__2_n_7\, Q => \^q\(4), R => \count_value_i_reg[0]_0\(0) ); @@ -2877,8 +2695,8 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[5]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__2_n_6\, Q => \^q\(5), R => \count_value_i_reg[0]_0\(0) ); @@ -2888,8 +2706,8 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[6]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__2_n_5\, Q => \^q\(6), R => \count_value_i_reg[0]_0\(0) ); @@ -2899,43 +2717,292 @@ begin ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[7]_i_1__1_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[7]_i_1__2_n_4\, Q => \^q\(7), R => \count_value_i_reg[0]_0\(0) ); +\count_value_i_reg[7]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_value_i_reg[3]_i_1__2_n_0\, + CO(3) => \count_value_i_reg[7]_i_1__2_n_0\, + CO(2) => \count_value_i_reg[7]_i_1__2_n_1\, + CO(1) => \count_value_i_reg[7]_i_1__2_n_2\, + CO(0) => \count_value_i_reg[7]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \count_value_i_reg[7]_i_1__2_n_4\, + O(2) => \count_value_i_reg[7]_i_1__2_n_5\, + O(1) => \count_value_i_reg[7]_i_1__2_n_6\, + O(0) => \count_value_i_reg[7]_i_1__2_n_7\, + S(3 downto 0) => \^q\(7 downto 4) + ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, - CE => E(0), - D => \count_value_i[8]_i_1__3_n_0\, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__2_n_7\, Q => \^q\(8), R => \count_value_i_reg[0]_0\(0) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8\: unisim.vcomponents.LUT4 +\count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"A659" + INIT => '0' ) port map ( - I0 => \^q\(0), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\, - I2 => \count_value_i_reg[4]_0\, - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\(0), - O => S(0) + C => wr_clk, + CE => ram_wr_en_pf, + D => \count_value_i_reg[11]_i_1__2_n_6\, + Q => \^q\(9), + R => \count_value_i_reg[0]_0\(0) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[9]_i_2\: unisim.vcomponents.LUT4 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"9699" + INIT => X"2" + ) + port map ( + I0 => \^q\(9), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(9), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" ) port map ( I0 => \^q\(8), - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\(2), - I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\(1), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(8), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(7), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(7), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(9), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(9), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(10), + I3 => \^q\(10), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(8), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(8), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(9), + I3 => \^q\(9), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(7), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(7), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(8), + I3 => \^q\(8), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(2), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(2), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(1), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(1), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(2), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(2), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(3), + I3 => \^q\(3), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(1), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(1), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(2), + I3 => \^q\(2), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9969" + ) + port map ( + I0 => \^q\(0), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(0), + I2 => ram_wr_en_pf, + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0\, + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(6), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(6), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(5), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(5), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(4), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(4), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^q\(3), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(3), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(6), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(6), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(7), I3 => \^q\(7), - O => \count_value_i_reg[8]_0\(0) + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(5), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(5), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(6), + I3 => \^q\(6), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(4), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(4), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(5), + I3 => \^q\(5), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D22D" + ) + port map ( + I0 => \^q\(3), + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(3), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(4), + I3 => \^q\(4), + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0\, + CO(3) => \NLW_gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_CO_UNCONNECTED\(3), + CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_1\, + CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_2\, + CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_2_n_0\, + DI(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_3_n_0\, + DI(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_4_n_0\, + O(3 downto 0) => D(11 downto 8), + S(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(0), + S(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_6_n_0\, + S(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_7_n_0\, + S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[12]_i_8_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0\, + CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_1\, + CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_2\, + CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_2_n_0\, + DI(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_3_n_0\, + DI(1) => DI(0), + DI(0) => '0', + O(3 downto 0) => D(3 downto 0), + S(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_5_n_0\, + S(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_6_n_0\, + S(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\(0), + S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_8_n_0\ + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_i_1_n_0\, + CO(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_0\, + CO(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_1\, + CO(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_2\, + CO(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_2_n_0\, + DI(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_3_n_0\, + DI(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_4_n_0\, + DI(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_5_n_0\, + O(3 downto 0) => D(7 downto 4), + S(3) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_6_n_0\, + S(2) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_7_n_0\, + S(1) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_8_n_0\, + S(0) => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[8]_i_9_n_0\ ); end STRUCTURE; library IEEE; @@ -2945,26 +3012,27 @@ use UNISIM.VCOMPONENTS.ALL; entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit is port ( rst_d1 : out STD_LOGIC; - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg\ : out STD_LOGIC; - \syncstages_ff_reg[3]\ : out STD_LOGIC; + clr_full : out STD_LOGIC; + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg\ : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_clk : in STD_LOGIC; - ram_rd_en_pf_q : in STD_LOGIC; - ram_wr_en_pf_q : in STD_LOGIC; + rst : in STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ : in STD_LOGIC; - prog_full : in STD_LOGIC; - rst : in STD_LOGIC + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0\ : in STD_LOGIC; + ram_wr_en_pf_q : in STD_LOGIC; + ram_rd_en_pf_q : in STD_LOGIC; + prog_full : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit : entity is "xpm_fifo_reg_bit"; end design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit; architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit is + signal \^clr_full\ : STD_LOGIC; signal \^rst_d1\ : STD_LOGIC; - signal \^syncstages_ff_reg[3]\ : STD_LOGIC; begin + clr_full <= \^clr_full\; rst_d1 <= \^rst_d1\; - \syncstages_ff_reg[3]\ <= \^syncstages_ff_reg[3]\; d_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -2976,7 +3044,7 @@ d_out_reg: unisim.vcomponents.FDRE Q => \^rst_d1\, R => '0' ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6\: unisim.vcomponents.LUT3 +\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) @@ -2984,19 +3052,20 @@ d_out_reg: unisim.vcomponents.FDRE I0 => rst, I1 => \^rst_d1\, I2 => Q(0), - O => \^syncstages_ff_reg[3]\ + O => \^clr_full\ ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_1\: unisim.vcomponents.LUT5 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"51551000" + INIT => X"5545555500001000" ) port map ( - I0 => \^syncstages_ff_reg[3]\, - I1 => ram_rd_en_pf_q, - I2 => ram_wr_en_pf_q, - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\, - I4 => prog_full, - O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg\ + I0 => \^clr_full\, + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\, + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0\, + I3 => ram_wr_en_pf_q, + I4 => ram_rd_en_pf_q, + I5 => prog_full, + O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg\ ); end STRUCTURE; library IEEE; @@ -3007,25 +3076,32 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst is port ( \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ : out STD_LOGIC; + write_only : out STD_LOGIC; + ram_wr_en_pf : out STD_LOGIC; + read_only : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_rst_cc.fifo_wr_rst_cc_reg[2]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_fwft.empty_fwft_i_reg\ : out STD_LOGIC; - \gen_fwft.empty_fwft_i_reg_0\ : out STD_LOGIC; - \gen_fwft.empty_fwft_i_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \count_value_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \count_value_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_fwft.empty_fwft_i_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_fwft.empty_fwft_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); prog_empty : in STD_LOGIC; write_only_q : in STD_LOGIC; - read_only_q : in STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0\ : in STD_LOGIC; + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1\ : in STD_LOGIC; + read_only_q : in STD_LOGIC; rst : in STD_LOGIC; - wr_en : in STD_LOGIC; - rst_d1 : in STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\ : in STD_LOGIC; - \count_value_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - ram_empty_i : in STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\ : in STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\ : in STD_LOGIC; + wr_en : in STD_LOGIC; + rst_d1 : in STD_LOGIC; + \grdc.rd_data_count_i_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + ram_empty_i : in STD_LOGIC; + \count_value_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \count_value_i_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_clk : in STD_LOGIC ); @@ -3036,90 +3112,121 @@ end design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst; architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst is signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC; + signal \^ram_wr_en_pf\ : STD_LOGIC; signal rst_i : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \grdc.rd_data_count_i[9]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \grdc.rd_data_count_i[12]_i_1\ : label is "soft_lutpair2"; begin Q(0) <= \^q\(0); - \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ <= \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\; + ram_wr_en_pf <= \^ram_wr_en_pf\; \count_value_i[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"ABAA" + INIT => X"AAAE" ) port map ( I0 => \^q\(0), - I1 => \count_value_i_reg[1]\(0), - I2 => \count_value_i_reg[1]\(1), - I3 => ram_empty_i, - O => SR(0) + I1 => ram_empty_i, + I2 => \grdc.rd_data_count_i_reg[0]\(1), + I3 => \grdc.rd_data_count_i_reg[0]\(0), + O => \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\(0) ); -\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_3\: unisim.vcomponents.LUT4 +\count_value_i[3]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFD" + INIT => X"6" ) port map ( - I0 => wr_en, - I1 => \^q\(0), - I2 => rst_d1, - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\, - O => \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ + I0 => \^ram_wr_en_pf\, + I1 => \count_value_i_reg[3]\(0), + O => S(0) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_9\: unisim.vcomponents.LUT4 +\count_value_i[3]_i_2__2\: unisim.vcomponents.LUT2 generic map( - INIT => X"FB04" + INIT => X"6" ) port map ( - I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\, - I1 => \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\, - I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\, - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\(0), - O => \gen_fwft.empty_fwft_i_reg_1\(0) + I0 => \^ram_wr_en_pf\, + I1 => \count_value_i_reg[3]_0\(0), + O => \count_value_i_reg[0]\(0) ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_1\: unisim.vcomponents.LUT5 +\count_value_i[3]_i_2__3\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFAAF2" + INIT => X"6" + ) + port map ( + I0 => \^ram_wr_en_pf\, + I1 => \count_value_i_reg[3]_1\(0), + O => \count_value_i_reg[0]_0\(0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFBB" + ) + port map ( + I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\, + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\, + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\, + I3 => \^ram_wr_en_pf\, + O => \gen_fwft.empty_fwft_i_reg\(0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFBB4044" + ) + port map ( + I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\, + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\, + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\, + I3 => \^ram_wr_en_pf\, + I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\(0), + O => \gen_fwft.empty_fwft_i_reg_0\(0) + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFAFAAA2AA" ) port map ( I0 => prog_empty, I1 => write_only_q, - I2 => read_only_q, - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0\, - I4 => \^q\(0), + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0\, + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1\, + I4 => read_only_q, + I5 => \^q\(0), O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_i_1\: unisim.vcomponents.LUT3 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"04" + INIT => X"4044" ) port map ( - I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\, - I1 => \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\, - I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\, - O => \gen_fwft.empty_fwft_i_reg_0\ + I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\, + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\, + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\, + I3 => \^ram_wr_en_pf\, + O => read_only ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_i_1\: unisim.vcomponents.LUT3 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"54" + INIT => X"4044" ) port map ( - I0 => \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\, - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\, - I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\, - O => \gen_fwft.empty_fwft_i_reg\ + I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\, + I1 => \^ram_wr_en_pf\, + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\, + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\, + O => write_only ); \gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( - I0 => rst, - I1 => p_0_in, + I0 => p_0_in, + I1 => rst, O => rst_i ); \gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE @@ -3155,23 +3262,26 @@ begin Q => \^q\(0), S => rst_i ); -\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT1 +\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"1" + INIT => X"0002" ) port map ( - I0 => \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\, - O => E(0) + I0 => wr_en, + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\, + I2 => \^q\(0), + I3 => rst_d1, + O => \^ram_wr_en_pf\ ); -\grdc.rd_data_count_i[9]_i_1\: unisim.vcomponents.LUT3 +\grdc.rd_data_count_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AB" ) port map ( I0 => \^q\(0), - I1 => \count_value_i_reg[1]\(1), - I2 => \count_value_i_reg[1]\(0), - O => \gen_rst_cc.fifo_wr_rst_cc_reg[2]_1\(0) + I1 => \grdc.rd_data_count_i_reg[0]\(1), + I2 => \grdc.rd_data_count_i_reg[0]\(0), + O => SR(0) ); \power_on_rst_reg[0]\: unisim.vcomponents.FDRE generic map( @@ -3208,7 +3318,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_memory_base is ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 8 downto 0 ); + addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 52 downto 0 ); injectsbiterra : in STD_LOGIC; injectdbiterra : in STD_LOGIC; @@ -3220,7 +3330,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_memory_base is enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); - addrb : in STD_LOGIC_VECTOR ( 8 downto 0 ); + addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 52 downto 0 ); injectsbiterrb : in STD_LOGIC; injectdbiterrb : in STD_LOGIC; @@ -3229,9 +3339,9 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_memory_base is dbiterrb : out STD_LOGIC ); attribute ADDR_WIDTH_A : integer; - attribute ADDR_WIDTH_A of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 9; + attribute ADDR_WIDTH_A of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 12; attribute ADDR_WIDTH_B : integer; - attribute ADDR_WIDTH_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 9; + attribute ADDR_WIDTH_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 12; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 0; attribute BYTE_WRITE_WIDTH_A : integer; @@ -3255,7 +3365,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_memory_base is attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 2; attribute MEMORY_SIZE : integer; - attribute MEMORY_SIZE of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 27136; + attribute MEMORY_SIZE of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 217088; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 1; attribute MESSAGE_CONTROL : integer; @@ -3271,7 +3381,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_memory_base is attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 0; attribute P_MAX_DEPTH_DATA : integer; - attribute P_MAX_DEPTH_DATA of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 512; + attribute P_MAX_DEPTH_DATA of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 4096; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is "yes"; attribute P_MEMORY_PRIMITIVE : string; @@ -3311,13 +3421,13 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_memory_base is attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 0; attribute P_WIDTH_ADDR_READ_A : integer; - attribute P_WIDTH_ADDR_READ_A of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 9; + attribute P_WIDTH_ADDR_READ_A of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 12; attribute P_WIDTH_ADDR_READ_B : integer; - attribute P_WIDTH_ADDR_READ_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 9; + attribute P_WIDTH_ADDR_READ_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 12; attribute P_WIDTH_ADDR_WRITE_A : integer; - attribute P_WIDTH_ADDR_WRITE_A of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 9; + attribute P_WIDTH_ADDR_WRITE_A of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 12; attribute P_WIDTH_ADDR_WRITE_B : integer; - attribute P_WIDTH_ADDR_WRITE_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 9; + attribute P_WIDTH_ADDR_WRITE_B of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 12; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of design_1_axi_fifo_mm_s_0_0_xpm_memory_base : entity is 53; attribute P_WIDTH_COL_WRITE_B : integer; @@ -3372,61 +3482,248 @@ end design_1_axi_fifo_mm_s_0_0_xpm_memory_base; architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_memory_base is signal \\ : STD_LOGIC; - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 21 ); - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_60\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_61\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_62\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_63\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_64\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_65\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_66\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_67\ : STD_LOGIC; + signal \gen_wr_a.gen_word_narrow.mem_reg_4_n_75\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer; - attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute \MEM.PORTA.ADDRESS_END\ : integer; - attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; + attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 4095; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; - attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d53"; + attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is "p1_d8"; attribute \MEM.PORTA.DATA_LSB\ : integer; - attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute \MEM.PORTA.DATA_MSB\ : integer; - attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 52; + attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 8; attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer; - attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute \MEM.PORTB.ADDRESS_END\ : integer; - attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; + attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 4095; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string; - attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d53"; + attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is "p1_d8"; attribute \MEM.PORTB.DATA_LSB\ : integer; - attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute \MEM.PORTB.DATA_MSB\ : integer; - attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 52; + attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 8; attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is ""; attribute RTL_RAM_BITS : integer; - attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 27136; + attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 217088; attribute RTL_RAM_NAME : string; - attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "gen_wr_a.gen_word_narrow.mem"; + attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE : string; - attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "RAM_SDP"; + attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is "RAM_SDP"; attribute bram_addr_begin : integer; - attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute bram_addr_end : integer; - attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; + attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 4095; attribute bram_slice_begin : integer; - attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute bram_slice_end : integer; - attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 52; + attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 8; attribute ram_addr_begin : integer; - attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute ram_addr_end : integer; - attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; + attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 4095; attribute ram_offset : integer; - attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute ram_slice_begin : integer; - attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; + attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 0; attribute ram_slice_end : integer; - attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 52; + attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0\ : label is 8; + attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 0; + attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 4095; + attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is "p1_d8"; + attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 9; + attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 17; + attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 0; + attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 4095; + attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is "p1_d8"; + attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 9; + attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 17; + attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is ""; + attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 217088; + attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is "gen_wr_a.gen_word_narrow.mem"; + attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is "RAM_SDP"; + attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 0; + attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 4095; + attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 9; + attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 17; + attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 0; + attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 4095; + attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 0; + attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 9; + attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_1\ : label is 17; + attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 0; + attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 4095; + attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is "p1_d8"; + attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 18; + attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 26; + attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 0; + attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 4095; + attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is "p1_d8"; + attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 18; + attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 26; + attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is ""; + attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 217088; + attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is "gen_wr_a.gen_word_narrow.mem"; + attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is "RAM_SDP"; + attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 0; + attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 4095; + attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 18; + attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 26; + attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 0; + attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 4095; + attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 0; + attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 18; + attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_2\ : label is 26; + attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 0; + attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 4095; + attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is "p1_d8"; + attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 27; + attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 35; + attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 0; + attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 4095; + attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is "p1_d8"; + attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 27; + attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is ""; + attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 217088; + attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is "gen_wr_a.gen_word_narrow.mem"; + attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is "RAM_SDP"; + attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 0; + attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 4095; + attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 27; + attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 35; + attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 0; + attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 4095; + attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 0; + attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 27; + attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_3\ : label is 35; + attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 0; + attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 4095; + attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is "p1_d8"; + attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 36; + attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 44; + attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 0; + attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 4095; + attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is "p1_d8"; + attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 36; + attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 44; + attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is "{SYNTH-6 {cell *THIS*}}"; + attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 217088; + attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is "gen_wr_a.gen_word_narrow.mem"; + attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is "RAM_SDP"; + attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 0; + attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 4095; + attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 36; + attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 44; + attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 0; + attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 4095; + attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 0; + attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 36; + attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_4\ : label is 44; + attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 0; + attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 4095; + attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is "p0_d8"; + attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 45; + attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 52; + attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 0; + attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 4095; + attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is "p0_d8"; + attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 45; + attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 52; + attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is ""; + attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 217088; + attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is "gen_wr_a.gen_word_narrow.mem"; + attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is "RAM_SDP"; + attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 0; + attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 4095; + attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 45; + attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 52; + attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 0; + attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 4095; + attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 0; + attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 45; + attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_5\ : label is 52; begin dbiterra <= \\; dbiterrb <= \\; @@ -3489,9 +3786,108 @@ GND: unisim.vcomponents.GND port map ( G => \\ ); -\gen_wr_a.gen_word_narrow.mem_reg\: unisim.vcomponents.RAMB36E1 +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][36]\: unisim.vcomponents.FDRE generic map( - DOA_REG => 1, + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_67\, + Q => doutb(36), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][37]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_66\, + Q => doutb(37), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][38]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_65\, + Q => doutb(38), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][39]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_64\, + Q => doutb(39), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][40]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_63\, + Q => doutb(40), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][41]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_62\, + Q => doutb(41), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][42]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_61\, + Q => doutb(42), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][43]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_60\, + Q => doutb(43), + R => rstb + ); +\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][44]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clka, + CE => regceb, + D => \gen_wr_a.gen_word_narrow.mem_reg_4_n_75\, + Q => doutb(44), + R => rstb + ); +\gen_wr_a.gen_word_narrow.mem_reg_0\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, @@ -3643,67 +4039,1140 @@ GND: unisim.vcomponents.GND INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", - RAM_MODE => "SDP", + RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 72, - READ_WIDTH_B => 0, + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 0, - WRITE_WIDTH_B => 72 + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "NO_CHANGE", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 6) => addrb(8 downto 0), - ADDRARDADDR(5 downto 0) => B"111111", + ADDRARDADDR(14 downto 3) => addra(11 downto 0), + ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 6) => addra(8 downto 0), - ADDRBWRADDR(5 downto 0) => B"111111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED\, + ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"000", + CASCADEINA => '1', + CASCADEINB => '1', + CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, - DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => dina(31 downto 0), - DIBDI(31 downto 21) => B"11111111111", - DIBDI(20 downto 0) => dina(52 downto 32), - DIPADIP(3 downto 0) => B"1111", - DIPBDIP(3 downto 0) => B"1111", - DOADO(31 downto 0) => doutb(31 downto 0), - DOBDO(31 downto 21) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED\(31 downto 21), - DOBDO(20 downto 0) => doutb(52 downto 32), - DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0), - DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0), - ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => enb, - ENBWREN => '1', - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => regceb, + DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => dina(7 downto 0), + DIBDI(31 downto 0) => B"00000000000000000000000011111111", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => dina(8), + DIPBDIP(3 downto 0) => B"0001", + DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => doutb(7 downto 0), + DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => doutb(8), + ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => wea(0), + ENBWREN => enb, + INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTDBITERR_UNCONNECTED\, + INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_INJECTSBITERR_UNCONNECTED\, + RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => regceb, + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => rstb, + SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_SBITERR_UNCONNECTED\, + WEA(3) => wea(0), + WEA(2) => wea(0), + WEA(1) => wea(0), + WEA(0) => '1', + WEBWE(7 downto 0) => B"00000000" + ); +\gen_wr_a.gen_word_narrow.mem_reg_1\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "NO_CHANGE", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => addra(11 downto 0), + ADDRARDADDR(2 downto 0) => B"000", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"000", + CASCADEINA => '1', + CASCADEINB => '1', + CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => clka, + CLKBWRCLK => clka, + DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => dina(16 downto 9), + DIBDI(31 downto 0) => B"00000000000000000000000011111111", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => dina(17), + DIPBDIP(3 downto 0) => B"0001", + DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_1_DOBDO_UNCONNECTED\(31 downto 8), + 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); +\gen_wr_a.gen_word_narrow.mem_reg_2\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "NO_CHANGE", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => addra(11 downto 0), + ADDRARDADDR(2 downto 0) => B"000", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"000", + CASCADEINA => '1', + CASCADEINB => '1', + CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => clka, + CLKBWRCLK => clka, + DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => dina(25 downto 18), + DIBDI(31 downto 0) => B"00000000000000000000000011111111", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => dina(26), + DIPBDIP(3 downto 0) => B"0001", + DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => doutb(25 downto 18), + DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => doutb(26), + ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => wea(0), + ENBWREN => enb, + INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTDBITERR_UNCONNECTED\, + INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_INJECTSBITERR_UNCONNECTED\, + RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => regceb, + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => rstb, + SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_2_SBITERR_UNCONNECTED\, + WEA(3) => wea(0), + WEA(2) => wea(0), + WEA(1) => wea(0), + WEA(0) => '1', + WEBWE(7 downto 0) => B"00000000" + ); +\gen_wr_a.gen_word_narrow.mem_reg_3\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "NO_CHANGE", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => addra(11 downto 0), + ADDRARDADDR(2 downto 0) => B"000", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"000", + CASCADEINA => '1', + CASCADEINB => '1', + CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => clka, + CLKBWRCLK => clka, + DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => dina(34 downto 27), + DIBDI(31 downto 0) => B"00000000000000000000000011111111", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => dina(35), + DIPBDIP(3 downto 0) => B"0001", + DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => doutb(34 downto 27), + DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => doutb(35), + ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => wea(0), + ENBWREN => enb, + INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTDBITERR_UNCONNECTED\, + INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_INJECTSBITERR_UNCONNECTED\, + RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => regceb, + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => rstb, + SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_3_SBITERR_UNCONNECTED\, + WEA(3) => wea(0), + WEA(2) => wea(0), + WEA(1) => wea(0), + WEA(0) => '1', + WEBWE(7 downto 0) => B"00000000" + ); +\gen_wr_a.gen_word_narrow.mem_reg_4\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 0, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "NO_CHANGE", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => addra(11 downto 0), + ADDRARDADDR(2 downto 0) => B"000", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"000", + CASCADEINA => '1', + CASCADEINB => '1', + CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => clka, + CLKBWRCLK => clka, + DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => dina(43 downto 36), + DIBDI(31 downto 0) => B"00000000000000000000000011111111", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => dina(44), + DIPBDIP(3 downto 0) => B"0001", + DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_60\, + DOBDO(6) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_61\, + DOBDO(5) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_62\, + DOBDO(4) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_63\, + DOBDO(3) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_64\, + DOBDO(2) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_65\, + DOBDO(1) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_66\, + DOBDO(0) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_67\, + DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \gen_wr_a.gen_word_narrow.mem_reg_4_n_75\, + ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => wea(0), + ENBWREN => enb, + INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTDBITERR_UNCONNECTED\, + INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_INJECTSBITERR_UNCONNECTED\, + RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', - RSTREGARSTREG => rstb, + RSTREGARSTREG => '0', RSTREGB => '0', - SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7) => wea(0), - WEBWE(6) => wea(0), - WEBWE(5) => wea(0), - WEBWE(4) => wea(0), - WEBWE(3) => wea(0), - WEBWE(2) => wea(0), - WEBWE(1) => wea(0), - WEBWE(0) => wea(0) + SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_4_SBITERR_UNCONNECTED\, + WEA(3) => wea(0), + WEA(2) => wea(0), + WEA(1) => wea(0), + WEA(0) => '1', + WEBWE(7 downto 0) => B"00000000" + ); +\gen_wr_a.gen_word_narrow.mem_reg_5\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "NO_CHANGE", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => addra(11 downto 0), + ADDRARDADDR(2 downto 0) => B"000", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"000", + CASCADEINA => '1', + CASCADEINB => '1', + CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => clka, + CLKBWRCLK => clka, + DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => dina(52 downto 45), + DIBDI(31 downto 0) => B"00000000000000000000000011111111", + DIPADIP(3 downto 0) => B"0000", + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => doutb(52 downto 45), + DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_DOPBDOP_UNCONNECTED\(3 downto 0), + ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => wea(0), + ENBWREN => enb, + INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTDBITERR_UNCONNECTED\, + INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_INJECTSBITERR_UNCONNECTED\, + RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => regceb, + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => rstb, + SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_5_SBITERR_UNCONNECTED\, + WEA(3) => wea(0), + WEA(2) => wea(0), + WEA(1) => wea(0), + WEA(0) => '1', + WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; @@ -3716,26 +5185,25 @@ entity design_1_axi_fifo_mm_s_0_0_address_decoder is \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : out STD_LOGIC; Bus_RNW_reg_reg_0 : out STD_LOGIC; - \s_axi_wdata[25]\ : out STD_LOGIC; + \s_axi_wdata[27]\ : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2\ : out STD_LOGIC; - sig_tx_channel_reset_reg : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3\ : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ : out STD_LOGIC; - sig_txd_sb_wr_en : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 6 downto 0 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1\ : out STD_LOGIC; - Bus_RNW_reg_reg_1 : out STD_LOGIC_VECTOR ( 12 downto 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_tx_channel_reset_reg : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1\ : out STD_LOGIC; + \s_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); cs_ce_clr : in STD_LOGIC; start2 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 12 downto 0 ); - \sig_register_array_reg[0][6]\ : in STD_LOGIC; - sig_txd_sb_wr_en_reg : in STD_LOGIC; + axi_str_txd_tvalid : in STD_LOGIC; + axi_str_txd_tlast : in STD_LOGIC; + IP2Bus_Error1_in : in STD_LOGIC; sig_str_rst_reg : in STD_LOGIC; \sig_ip2bus_data_reg[10]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); @@ -3745,8 +5213,7 @@ entity design_1_axi_fifo_mm_s_0_0_address_decoder is \sig_ip2bus_data_reg[6]\ : in STD_LOGIC; \sig_ip2bus_data_reg[4]\ : in STD_LOGIC; \sig_ip2bus_data_reg[3]\ : in STD_LOGIC; - sig_txd_sb_wr_en_reg_0 : in STD_LOGIC; - IP2Bus_Error1_in : in STD_LOGIC; + IP2Bus_Error_reg : in STD_LOGIC; sig_Bus2IP_RNW : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); @@ -3760,15 +5227,14 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_address_decoder is signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC; signal \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\ : STD_LOGIC; signal \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\ : STD_LOGIC; - signal \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_2\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC; - signal \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\ : STD_LOGIC; signal \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_1\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC; + signal \^gen_bkend_ce_registers[4].ce_out_i_reg[4]_0\ : STD_LOGIC; signal \^gen_bkend_ce_registers[5].ce_out_i_reg[5]_0\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC; @@ -3790,40 +5256,41 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_address_decoder is signal \sig_ip2bus_data[3]_i_2_n_0\ : STD_LOGIC; signal \sig_register_array[1][0]_i_3_n_0\ : STD_LOGIC; signal \sig_register_array[1][0]_i_4_n_0\ : STD_LOGIC; + signal \sig_register_array[1][0]_i_5_n_0\ : STD_LOGIC; + signal \sig_register_array[1][0]_i_6_n_0\ : STD_LOGIC; signal sig_str_rst_i_3_n_0 : STD_LOGIC; - signal \^sig_tx_channel_reset_reg\ : STD_LOGIC; + signal \sig_txd_wr_data[31]_i_4_n_0\ : STD_LOGIC; signal \sig_txd_wr_data[31]_i_5_n_0\ : STD_LOGIC; - signal sig_txd_wr_en_i_3_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[0]_i_2\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[3]_i_2\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \sig_register_array[1][0]_i_2\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \sig_register_array[1][0]_i_4\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \sig_register_array[1][10]_i_1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \sig_register_array[1][11]_i_1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \sig_register_array[1][1]_i_1\ : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of \sig_register_array[1][2]_i_1\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \sig_register_array[1][3]_i_1\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \sig_register_array[1][4]_i_1\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \sig_register_array[1][5]_i_1\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \sig_register_array[1][6]_i_1\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \sig_register_array[1][7]_i_1\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \sig_register_array[1][8]_i_1\ : label is "soft_lutpair46"; - attribute SOFT_HLUTNM of \sig_register_array[1][9]_i_1\ : label is "soft_lutpair46"; - attribute SOFT_HLUTNM of sig_str_rst_i_3 : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \sig_txd_wr_data[31]_i_2\ : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \sig_txd_wr_data[31]_i_4\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of sig_txd_wr_en_i_3 : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \sig_register_array[0][3]_i_2\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \sig_register_array[0][4]_i_2\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \sig_register_array[0][4]_i_3\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \sig_register_array[1][0]_i_3\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \sig_register_array[1][0]_i_4\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \sig_register_array[1][0]_i_5\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \sig_register_array[1][0]_i_6\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \sig_register_array[1][10]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \sig_register_array[1][11]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \sig_register_array[1][12]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \sig_register_array[1][1]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \sig_register_array[1][2]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \sig_register_array[1][3]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \sig_register_array[1][4]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \sig_register_array[1][5]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \sig_register_array[1][6]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \sig_register_array[1][7]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \sig_register_array[1][8]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \sig_register_array[1][9]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of sig_str_rst_i_3 : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \sig_txd_wr_data[31]_i_3\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \sig_txd_wr_data[31]_i_5\ : label is "soft_lutpair20"; begin Bus_RNW_reg_reg_0 <= \^bus_rnw_reg_reg_0\; \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\ <= \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\; \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\ <= \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\; - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2\ <= \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_2\; - \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ <= \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ <= \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_1\; + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ <= \^gen_bkend_ce_registers[4].ce_out_i_reg[4]_0\; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ <= \^gen_bkend_ce_registers[5].ce_out_i_reg[5]_0\; - sig_tx_channel_reset_reg <= \^sig_tx_channel_reset_reg\; Bus_RNW_reg_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" @@ -4019,15 +5486,16 @@ Bus_RNW_reg_reg: unisim.vcomponents.FDRE Q => sig_Bus2IP_CS, R => cs_ce_clr ); -\sig_ip2bus_data[0]_i_2\: unisim.vcomponents.LUT4 +\sig_ip2bus_data[0]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"FBFF" + INIT => X"FFFFFBFF" ) port map ( - I0 => \sig_register_array[1][0]_i_3_n_0\, + I0 => \sig_register_array[1][0]_i_5_n_0\, I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => \sig_register_array[1][0]_i_4_n_0\, + I2 => \sig_register_array[1][0]_i_3_n_0\, I3 => \^bus_rnw_reg_reg_0\, + I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, O => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_1\ ); \sig_ip2bus_data[10]_i_1\: unisim.vcomponents.LUT4 @@ -4041,18 +5509,18 @@ Bus_RNW_reg_reg: unisim.vcomponents.FDRE I3 => Q(0), O => D(0) ); -\sig_ip2bus_data[22]_i_2\: unisim.vcomponents.LUT6 +\sig_ip2bus_data[19]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFBFFFFFFFF" + INIT => X"FFFFFFFFFFEFFFFF" ) port map ( - I0 => sig_str_rst_i_3_n_0, - I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, - I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, - I4 => \sig_register_array[1][0]_i_4_n_0\, - I5 => \^bus_rnw_reg_reg_0\, - O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ + I0 => \sig_register_array[1][0]_i_6_n_0\, + I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, + I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, + I3 => \sig_register_array[1][0]_i_3_n_0\, + I4 => \^bus_rnw_reg_reg_0\, + I5 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, + O => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ ); \sig_ip2bus_data[3]_i_1\: unisim.vcomponents.LUT4 generic map( @@ -4065,16 +5533,17 @@ Bus_RNW_reg_reg: unisim.vcomponents.FDRE I3 => Q(6), O => D(6) ); -\sig_ip2bus_data[3]_i_2\: unisim.vcomponents.LUT5 +\sig_ip2bus_data[3]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFEFFFFF" + INIT => X"FFFFFFEFFFFFFFFF" ) port map ( - I0 => \sig_register_array[1][0]_i_3_n_0\, + I0 => \sig_register_array[1][0]_i_5_n_0\, I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, I2 => \^bus_rnw_reg_reg_0\, - I3 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\, - I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, + I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, + I4 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\, + I5 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, O => \sig_ip2bus_data[3]_i_2_n_0\ ); \sig_ip2bus_data[4]_i_1\: unisim.vcomponents.LUT4 @@ -4132,271 +5601,256 @@ Bus_RNW_reg_reg: unisim.vcomponents.FDRE I3 => Q(1), O => D(1) ); -\sig_register_array[0][3]_i_2\: unisim.vcomponents.LUT4 +\sig_register_array[0][3]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFEF" + INIT => X"FFFFFFEF" ) port map ( I0 => sig_str_rst_i_3_n_0, I1 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, - I3 => \sig_register_array_reg[0][6]\, - O => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_2\ + I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, + I4 => IP2Bus_Error1_in, + O => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\ ); \sig_register_array[0][4]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( - I0 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\, - I1 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_2\, - O => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3\ + I0 => \^gen_bkend_ce_registers[4].ce_out_i_reg[4]_0\, + I1 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\, + O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1\ ); -\sig_register_array[0][6]_i_2\: unisim.vcomponents.LUT6 +\sig_register_array[0][4]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"AEAEAEAEAEAEFFAE" + INIT => X"FFAEAEAE" ) port map ( - I0 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\, - I1 => s_axi_wdata(6), - I2 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_2\, - I3 => \^sig_tx_channel_reset_reg\, - I4 => \sig_register_array_reg[0][6]\, - I5 => sig_txd_sb_wr_en_reg, - O => \s_axi_wdata[25]\ + I0 => \^gen_bkend_ce_registers[4].ce_out_i_reg[4]_0\, + I1 => s_axi_wdata(8), + I2 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\, + I3 => axi_str_txd_tvalid, + I4 => axi_str_txd_tlast, + O => \s_axi_wdata[27]\ ); \sig_register_array[1][0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"F0F0F0F0F0F0F0F4" + INIT => X"AAAAAAAAAAAAAAAB" ) port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\, + I0 => \^gen_bkend_ce_registers[4].ce_out_i_reg[4]_0\, + I1 => IP2Bus_Error1_in, + I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I3 => \sig_register_array[1][0]_i_3_n_0\, - I4 => IP2Bus_Error1_in, - I5 => \sig_register_array[1][0]_i_4_n_0\, + I4 => \sig_register_array[1][0]_i_4_n_0\, + I5 => \sig_register_array[1][0]_i_5_n_0\, O => E(0) ); -\sig_register_array[1][0]_i_2\: unisim.vcomponents.LUT3 +\sig_register_array[1][0]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"40" + INIT => X"2" ) port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(12), - O => Bus_RNW_reg_reg_1(12) + I0 => s_axi_wdata(12), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(12) ); -\sig_register_array[1][0]_i_3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FE" - ) - port map ( - I0 => sig_str_rst_i_3_n_0, - I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, - I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, - O => \sig_register_array[1][0]_i_3_n_0\ - ); -\sig_register_array[1][0]_i_4\: unisim.vcomponents.LUT2 +\sig_register_array[1][0]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\, + O => \sig_register_array[1][0]_i_3_n_0\ + ); +\sig_register_array[1][0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^bus_rnw_reg_reg_0\, + I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, O => \sig_register_array[1][0]_i_4_n_0\ ); -\sig_register_array[1][10]_i_1\: unisim.vcomponents.LUT3 +\sig_register_array[1][0]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => X"40" + INIT => X"E" ) port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(2), - O => Bus_RNW_reg_reg_1(2) + I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, + I1 => \sig_register_array[1][0]_i_6_n_0\, + O => \sig_register_array[1][0]_i_5_n_0\ ); -\sig_register_array[1][11]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(1), - O => Bus_RNW_reg_reg_1(1) - ); -\sig_register_array[1][12]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(0), - O => Bus_RNW_reg_reg_1(0) - ); -\sig_register_array[1][1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(11), - O => Bus_RNW_reg_reg_1(11) - ); -\sig_register_array[1][2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(10), - O => Bus_RNW_reg_reg_1(10) - ); -\sig_register_array[1][3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(9), - O => Bus_RNW_reg_reg_1(9) - ); -\sig_register_array[1][4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(8), - O => Bus_RNW_reg_reg_1(8) - ); -\sig_register_array[1][5]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(7), - O => Bus_RNW_reg_reg_1(7) - ); -\sig_register_array[1][6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(6), - O => Bus_RNW_reg_reg_1(6) - ); -\sig_register_array[1][7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(5), - O => Bus_RNW_reg_reg_1(5) - ); -\sig_register_array[1][8]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(4), - O => Bus_RNW_reg_reg_1(4) - ); -\sig_register_array[1][9]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^bus_rnw_reg_reg_0\, - I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I2 => s_axi_wdata(3), - O => Bus_RNW_reg_reg_1(3) - ); -sig_str_rst_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000400" - ) - port map ( - I0 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\, - I1 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\, - I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, - I3 => sig_str_rst_reg, - I4 => sig_str_rst_i_3_n_0, - I5 => IP2Bus_Error1_in, - O => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_1\ - ); -sig_str_rst_i_3: unisim.vcomponents.LUT3 +\sig_register_array[1][0]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \^gen_bkend_ce_registers[5].ce_out_i_reg[5]_0\, - I1 => \sig_txd_wr_data[31]_i_5_n_0\, + I1 => \sig_txd_wr_data[31]_i_4_n_0\, I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, - O => sig_str_rst_i_3_n_0 + O => \sig_register_array[1][0]_i_6_n_0\ ); -sig_tx_channel_reset_i_2: unisim.vcomponents.LUT6 +\sig_register_array[1][10]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000000000000400" + INIT => X"2" ) port map ( - I0 => \sig_register_array[1][0]_i_4_n_0\, - I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, - I2 => \^gen_bkend_ce_registers[5].ce_out_i_reg[5]_0\, - I3 => sig_str_rst_reg, - I4 => \sig_register_array_reg[0][6]\, - I5 => \sig_txd_wr_data[31]_i_5_n_0\, - O => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ - ); -sig_txd_sb_wr_en_i_1: unisim.vcomponents.LUT3 - generic map( - INIT => X"08" - ) - port map ( - I0 => \^sig_tx_channel_reset_reg\, - I1 => sig_txd_sb_wr_en_reg, - I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\, - O => sig_txd_sb_wr_en - ); -\sig_txd_wr_data[31]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00000010" - ) - port map ( - I0 => sig_txd_sb_wr_en_reg_0, + I0 => s_axi_wdata(2), I1 => \sig_register_array[1][0]_i_4_n_0\, - I2 => \^gen_bkend_ce_registers[5].ce_out_i_reg[5]_0\, - I3 => \sig_txd_wr_data[31]_i_5_n_0\, - I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, - O => \^sig_tx_channel_reset_reg\ + O => \s_axi_wdata[31]\(2) ); -\sig_txd_wr_data[31]_i_4\: unisim.vcomponents.LUT4 +\sig_register_array[1][11]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(1), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(1) + ); +\sig_register_array[1][12]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(0), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(0) + ); +\sig_register_array[1][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(11), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(11) + ); +\sig_register_array[1][2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(10), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(10) + ); +\sig_register_array[1][3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(9), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(9) + ); +\sig_register_array[1][4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(8), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(8) + ); +\sig_register_array[1][5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(7), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(7) + ); +\sig_register_array[1][6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(6), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(6) + ); +\sig_register_array[1][7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(5), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(5) + ); +\sig_register_array[1][8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(4), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(4) + ); +\sig_register_array[1][9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wdata(3), + I1 => \sig_register_array[1][0]_i_4_n_0\, + O => \s_axi_wdata[31]\(3) + ); +sig_str_rst_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => sig_str_rst_reg, + I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, + I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, + I3 => \^gen_bkend_ce_registers[10].ce_out_i_reg[10]_0\, + I4 => sig_str_rst_i_3_n_0, + I5 => IP2Bus_Error1_in, + O => \^gen_bkend_ce_registers[4].ce_out_i_reg[4]_0\ + ); +sig_str_rst_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( - I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, + I0 => \sig_register_array[1][0]_i_6_n_0\, I1 => \^bus_rnw_reg_reg_0\, - I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, + I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, - O => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\ + O => sig_str_rst_i_3_n_0 ); -\sig_txd_wr_data[31]_i_5\: unisim.vcomponents.LUT6 +sig_tx_channel_reset_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => sig_str_rst_reg, + I1 => IP2Bus_Error1_in, + I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, + I3 => \^gen_bkend_ce_registers[5].ce_out_i_reg[5]_0\, + I4 => \sig_txd_wr_data[31]_i_5_n_0\, + I5 => \sig_txd_wr_data[31]_i_4_n_0\, + O => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ + ); +\sig_txd_wr_data[31]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000100" + ) + port map ( + I0 => \sig_txd_wr_data[31]_i_4_n_0\, + I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, + I2 => IP2Bus_Error_reg, + I3 => \^gen_bkend_ce_registers[5].ce_out_i_reg[5]_0\, + I4 => \sig_txd_wr_data[31]_i_5_n_0\, + O => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1\ + ); +\sig_txd_wr_data[31]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) @@ -4407,29 +5861,30 @@ sig_txd_sb_wr_en_i_1: unisim.vcomponents.LUT3 I3 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg\, I4 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, I5 => \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg\, - O => \sig_txd_wr_data[31]_i_5_n_0\ + O => \sig_txd_wr_data[31]_i_4_n_0\ ); -sig_txd_wr_en_i_2: unisim.vcomponents.LUT5 +\sig_txd_wr_data[31]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( - I0 => sig_str_rst_i_3_n_0, - I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, - I2 => sig_txd_wr_en_i_3_n_0, - I3 => sig_txd_sb_wr_en_reg_0, - I4 => \sig_register_array[1][0]_i_4_n_0\, - O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1\ + I0 => \^bus_rnw_reg_reg_0\, + I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, + I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, + I3 => \sig_register_array[1][0]_i_3_n_0\, + I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, + O => \sig_txd_wr_data[31]_i_5_n_0\ ); -sig_txd_wr_en_i_3: unisim.vcomponents.LUT3 +sig_txd_wr_en_i_2: unisim.vcomponents.LUT4 generic map( - INIT => X"EF" + INIT => X"FFEF" ) port map ( - I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, - I1 => \^bus_rnw_reg_reg_0\, + I0 => sig_str_rst_i_3_n_0, + I1 => IP2Bus_Error_reg, I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, - O => sig_txd_wr_en_i_3_n_0 + I3 => \sig_register_array[1][0]_i_3_n_0\, + O => sig_tx_channel_reset_reg ); end STRUCTURE; library IEEE; @@ -4446,7 +5901,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is full : out STD_LOGIC; full_n : out STD_LOGIC; prog_full : out STD_LOGIC; - wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 ); + wr_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; @@ -4456,7 +5911,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is dout : out STD_LOGIC_VECTOR ( 52 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; - rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 ); + rd_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; @@ -4507,13 +5962,13 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 2; attribute FIFO_READ_DEPTH : integer; - attribute FIFO_READ_DEPTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 512; + attribute FIFO_READ_DEPTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 4096; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 0; attribute FIFO_SIZE : integer; - attribute FIFO_SIZE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 27136; + attribute FIFO_SIZE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 217088; attribute FIFO_WRITE_DEPTH : integer; - attribute FIFO_WRITE_DEPTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 512; + attribute FIFO_WRITE_DEPTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 4096; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 1; attribute FULL_RST_VAL : string; @@ -4523,29 +5978,29 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 3; attribute PE_THRESH_MAX : integer; - attribute PE_THRESH_MAX of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 507; + attribute PE_THRESH_MAX of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 4091; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 5; attribute PF_THRESH_ADJ : integer; - attribute PF_THRESH_ADJ of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 505; + attribute PF_THRESH_ADJ of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 4089; attribute PF_THRESH_MAX : integer; - attribute PF_THRESH_MAX of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 507; + attribute PF_THRESH_MAX of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 4091; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 5; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 5; attribute PROG_FULL_THRESH : integer; - attribute PROG_FULL_THRESH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 507; + attribute PROG_FULL_THRESH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 4091; attribute RD_DATA_COUNT_WIDTH : integer; - attribute RD_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 10; + attribute RD_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 13; attribute RD_DC_WIDTH_EXT : integer; - attribute RD_DC_WIDTH_EXT of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 10; + attribute RD_DC_WIDTH_EXT of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 13; attribute RD_LATENCY : integer; attribute RD_LATENCY of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 2; attribute RD_MODE : integer; attribute RD_MODE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 1; attribute RD_PNTR_WIDTH : integer; - attribute RD_PNTR_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 9; + attribute RD_PNTR_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 12; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 53; attribute READ_MODE : integer; @@ -4567,13 +6022,13 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 53; attribute WR_DATA_COUNT_WIDTH : integer; - attribute WR_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 10; + attribute WR_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 13; attribute WR_DC_WIDTH_EXT : integer; - attribute WR_DC_WIDTH_EXT of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 10; + attribute WR_DC_WIDTH_EXT of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 13; attribute WR_DEPTH_LOG : integer; - attribute WR_DEPTH_LOG of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 9; + attribute WR_DEPTH_LOG of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 12; attribute WR_PNTR_WIDTH : integer; - attribute WR_PNTR_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 9; + attribute WR_PNTR_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 12; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base : entity is 0; attribute WR_WIDTH_LOG : integer; @@ -4597,12 +6052,13 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is signal aempty_fwft_i0 : STD_LOGIC; signal \^almost_empty\ : STD_LOGIC; signal \^almost_full\ : STD_LOGIC; + signal clr_full : STD_LOGIC; signal count_value_i : STD_LOGIC_VECTOR ( 1 to 1 ); signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal data_valid_fwft1 : STD_LOGIC; - signal diff_pntr_pe : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 9 downto 1 ); - signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 9 downto 1 ); + signal diff_pntr_pe : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 12 downto 1 ); + signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 12 downto 1 ); signal \gen_fwft.count_rst\ : STD_LOGIC; signal \gen_fwft.empty_fwft_i_reg_n_0\ : STD_LOGIC; signal \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\ : STD_LOGIC; @@ -4612,6 +6068,8 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC; signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[10]\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[11]\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC; @@ -4620,40 +6078,69 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8]\ : STD_LOGIC; + signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[9]\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2_n_0\ : STD_LOGIC; signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0\ : STD_LOGIC; - signal going_afull1 : STD_LOGIC; - signal going_empty1 : STD_LOGIC; - signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 12 downto 0 ); signal \grdc.rd_data_count_i0\ : STD_LOGIC; signal leaving_empty0 : STD_LOGIC; signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \p_1_in__0\ : STD_LOGIC; signal \^prog_empty\ : STD_LOGIC; signal \^prog_full\ : STD_LOGIC; signal ram_empty_i : STD_LOGIC; signal ram_empty_i0 : STD_LOGIC; - signal ram_rd_en_pf : STD_LOGIC; signal ram_rd_en_pf_q : STD_LOGIC; signal ram_wr_en_pf : STD_LOGIC; signal ram_wr_en_pf_q : STD_LOGIC; - signal rd_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal rd_pntr_ext : STD_LOGIC_VECTOR ( 11 downto 0 ); signal rdp_inst_n_0 : STD_LOGIC; signal rdp_inst_n_1 : STD_LOGIC; + signal rdp_inst_n_15 : STD_LOGIC; + signal rdp_inst_n_16 : STD_LOGIC; + signal rdp_inst_n_17 : STD_LOGIC; + signal rdp_inst_n_19 : STD_LOGIC; signal rdp_inst_n_2 : STD_LOGIC; - signal rdp_inst_n_3 : STD_LOGIC; + signal rdp_inst_n_20 : STD_LOGIC; + signal rdp_inst_n_21 : STD_LOGIC; + signal rdp_inst_n_22 : STD_LOGIC; + signal rdp_inst_n_23 : STD_LOGIC; + signal rdp_inst_n_24 : STD_LOGIC; + signal rdp_inst_n_25 : STD_LOGIC; + signal rdp_inst_n_26 : STD_LOGIC; + signal rdp_inst_n_27 : STD_LOGIC; + signal rdp_inst_n_28 : STD_LOGIC; + signal rdp_inst_n_29 : STD_LOGIC; + signal rdp_inst_n_30 : STD_LOGIC; + signal rdp_inst_n_31 : STD_LOGIC; signal rdp_inst_n_32 : STD_LOGIC; + signal rdp_inst_n_33 : STD_LOGIC; + signal rdpp1_inst_n_0 : STD_LOGIC; + signal rdpp1_inst_n_1 : STD_LOGIC; + signal rdpp1_inst_n_10 : STD_LOGIC; + signal rdpp1_inst_n_11 : STD_LOGIC; + signal rdpp1_inst_n_2 : STD_LOGIC; + signal rdpp1_inst_n_3 : STD_LOGIC; + signal rdpp1_inst_n_4 : STD_LOGIC; + signal rdpp1_inst_n_5 : STD_LOGIC; + signal rdpp1_inst_n_6 : STD_LOGIC; + signal rdpp1_inst_n_7 : STD_LOGIC; + signal rdpp1_inst_n_8 : STD_LOGIC; + signal rdpp1_inst_n_9 : STD_LOGIC; + signal read_only : STD_LOGIC; signal read_only_q : STD_LOGIC; signal rst_d1 : STD_LOGIC; - signal rst_d1_inst_n_1 : STD_LOGIC; signal rst_d1_inst_n_2 : STD_LOGIC; - signal wr_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal wr_pntr_ext : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal write_only : STD_LOGIC; signal write_only_q : STD_LOGIC; - signal wrp_inst_n_21 : STD_LOGIC; + signal wrp_inst_n_1 : STD_LOGIC; signal wrpp1_inst_n_0 : STD_LOGIC; signal wrpp1_inst_n_1 : STD_LOGIC; signal wrpp1_inst_n_10 : STD_LOGIC; + signal wrpp1_inst_n_11 : STD_LOGIC; signal wrpp1_inst_n_2 : STD_LOGIC; signal wrpp1_inst_n_3 : STD_LOGIC; signal wrpp1_inst_n_4 : STD_LOGIC; @@ -4662,29 +6149,41 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is signal wrpp1_inst_n_7 : STD_LOGIC; signal wrpp1_inst_n_8 : STD_LOGIC; signal wrpp1_inst_n_9 : STD_LOGIC; + signal wrpp2_inst_n_0 : STD_LOGIC; + signal wrpp2_inst_n_1 : STD_LOGIC; + signal wrpp2_inst_n_10 : STD_LOGIC; + signal wrpp2_inst_n_11 : STD_LOGIC; + signal wrpp2_inst_n_2 : STD_LOGIC; + signal wrpp2_inst_n_3 : STD_LOGIC; + signal wrpp2_inst_n_4 : STD_LOGIC; + signal wrpp2_inst_n_5 : STD_LOGIC; + signal wrpp2_inst_n_6 : STD_LOGIC; + signal wrpp2_inst_n_7 : STD_LOGIC; + signal wrpp2_inst_n_8 : STD_LOGIC; + signal wrpp2_inst_n_9 : STD_LOGIC; signal xpm_fifo_rst_inst_n_0 : STD_LOGIC; signal xpm_fifo_rst_inst_n_1 : STD_LOGIC; - signal xpm_fifo_rst_inst_n_3 : STD_LOGIC; - signal xpm_fifo_rst_inst_n_6 : STD_LOGIC; + signal xpm_fifo_rst_inst_n_11 : STD_LOGIC; signal xpm_fifo_rst_inst_n_7 : STD_LOGIC; signal xpm_fifo_rst_inst_n_8 : STD_LOGIC; + signal xpm_fifo_rst_inst_n_9 : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 52 downto 0 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair3"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; - attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \gen_fwft.gae_fwft.aempty_fwft_i_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \gen_fwft.gdvld_fwft.data_valid_fwft_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \gen_fwft.gae_fwft.aempty_fwft_i_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \gen_fwft.gdvld_fwft.data_valid_fwft_i_1\ : label is "soft_lutpair4"; attribute ADDR_WIDTH_A : integer; - attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; + attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12; attribute ADDR_WIDTH_B : integer; - attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; + attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute BYTE_WRITE_WIDTH_A : integer; @@ -4707,7 +6206,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 52; attribute \MEM.ADDRESS_SPACE_END\ : integer; - attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 511; + attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 4095; attribute \MEM.CORE_MEMORY_WIDTH\ : integer; attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 53; attribute MEMORY_INIT_FILE : string; @@ -4719,7 +6218,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute MEMORY_SIZE : integer; - attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 27136; + attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 217088; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute MESSAGE_CONTROL : integer; @@ -4733,7 +6232,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_MAX_DEPTH_DATA : integer; - attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 512; + attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 4096; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes"; attribute P_MEMORY_PRIMITIVE : string; @@ -4773,13 +6272,13 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_base is attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_READ_A : integer; - attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; + attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12; attribute P_WIDTH_ADDR_READ_B : integer; - attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; + attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12; attribute P_WIDTH_ADDR_WRITE_A : integer; - attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; + attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12; attribute P_WIDTH_ADDR_WRITE_B : integer; - attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; + attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 53; attribute P_WIDTH_COL_WRITE_B : integer; @@ -4840,23 +6339,23 @@ begin wr_rst_busy <= \\; \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"6899" - ) - port map ( - I0 => curr_fwft_state(0), - I1 => ram_empty_i, - I2 => rd_en, - I3 => curr_fwft_state(1), - O => \next_fwft_state__0\(0) - ); -\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"7C" + INIT => X"7883" ) port map ( I0 => rd_en, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), + I3 => ram_empty_i, + O => \next_fwft_state__0\(0) + ); +\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7A" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => rd_en, + I2 => curr_fwft_state(1), O => \next_fwft_state__0\(1) ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE @@ -4887,12 +6386,12 @@ GND: unisim.vcomponents.GND ); \gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BB80" + INIT => X"F380" ) port map ( - I0 => curr_fwft_state(1), + I0 => rd_en, I1 => curr_fwft_state(0), - I2 => rd_en, + I2 => curr_fwft_state(1), I3 => \gen_fwft.empty_fwft_i_reg_n_0\, O => data_valid_fwft1 ); @@ -4909,14 +6408,14 @@ GND: unisim.vcomponents.GND ); \gen_fwft.gae_fwft.aempty_fwft_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"A888EAAA" + INIT => X"FDDD4000" ) port map ( - I0 => \^almost_empty\, + I0 => curr_fwft_state(0), I1 => ram_empty_i, - I2 => rd_en, - I3 => curr_fwft_state(1), - I4 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => rd_en, + I4 => \^almost_empty\, O => aempty_fwft_i0 ); \gen_fwft.gae_fwft.aempty_fwft_i_reg\: unisim.vcomponents.FDSE @@ -4932,12 +6431,12 @@ GND: unisim.vcomponents.GND ); \gen_fwft.gdvld_fwft.data_valid_fwft_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"447F" + INIT => X"0C7F" ) port map ( - I0 => curr_fwft_state(1), + I0 => rd_en, I1 => curr_fwft_state(0), - I2 => rd_en, + I2 => curr_fwft_state(1), I3 => \gen_fwft.empty_fwft_i_reg_n_0\, O => \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\ ); @@ -4959,9 +6458,9 @@ GND: unisim.vcomponents.GND S(1) => \gen_fwft.rdpp1_inst_n_1\, S(0) => \gen_fwft.rdpp1_inst_n_2\, SR(0) => \gen_fwft.count_rst\, - \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0), - \grdc.rd_data_count_i_reg[3]\(1 downto 0) => wr_pntr_ext(1 downto 0), - \grdc.rd_data_count_i_reg[3]_0\(1 downto 0) => rd_pntr_ext(1 downto 0), + \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), + \grdc.rd_data_count_i_reg[3]\(1 downto 0) => rd_pntr_ext(1 downto 0), + \grdc.rd_data_count_i_reg[3]_0\(1 downto 0) => wr_pntr_ext(1 downto 0), ram_empty_i => ram_empty_i, rd_en => rd_en, wr_clk => wr_clk @@ -4973,7 +6472,7 @@ GND: unisim.vcomponents.GND port map ( C => wr_clk, CE => '1', - D => rdp_inst_n_2, + D => rdp_inst_n_0, Q => \^almost_full\, S => xpm_fifo_rst_inst_n_1 ); @@ -4984,7 +6483,7 @@ GND: unisim.vcomponents.GND port map ( C => wr_clk, CE => '1', - D => rdp_inst_n_32, + D => rdp_inst_n_33, Q => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\, S => xpm_fifo_rst_inst_n_1 ); @@ -4995,7 +6494,7 @@ GND: unisim.vcomponents.GND port map ( C => wr_clk, CE => '1', - D => rdp_inst_n_0, + D => rdp_inst_n_19, Q => full_n, R => xpm_fifo_rst_inst_n_1 ); @@ -5021,6 +6520,28 @@ GND: unisim.vcomponents.GND Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0]\, R => xpm_fifo_rst_inst_n_1 ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => diff_pntr_pe(10), + Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[10]\, + R => xpm_fifo_rst_inst_n_1 + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => diff_pntr_pe(11), + Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[11]\, + R => xpm_fifo_rst_inst_n_1 + ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -5109,28 +6630,41 @@ GND: unisim.vcomponents.GND Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8]\, R => xpm_fifo_rst_inst_n_1 ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2\: unisim.vcomponents.LUT4 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFEF" + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => diff_pntr_pe(9), + Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[9]\, + R => xpm_fifo_rst_inst_n_1 + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" ) port map ( I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[2]\, - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[5]\, - I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0]\, - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0\, + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0]\, + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1]\, + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[5]\, + I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3]\, + I5 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[4]\, O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2_n_0\ ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFFFFD" + INIT => X"0000000000000001" ) port map ( - I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1]\, - I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8]\, - I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[4]\, - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[7]\, - I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3]\, - I5 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[6]\, + I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[10]\, + I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[9]\, + I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[11]\, + I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[6]\, + I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[7]\, + I5 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[8]\, O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0\ ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\: unisim.vcomponents.FDRE @@ -5148,7 +6682,7 @@ GND: unisim.vcomponents.GND port map ( C => wr_clk, CE => '1', - D => xpm_fifo_rst_inst_n_7, + D => read_only, Q => read_only_q, R => xpm_fifo_rst_inst_n_1 ); @@ -5156,10 +6690,43 @@ GND: unisim.vcomponents.GND port map ( C => wr_clk, CE => '1', - D => xpm_fifo_rst_inst_n_6, + D => write_only, Q => write_only_q, R => xpm_fifo_rst_inst_n_1 ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => diff_pntr_pf_q0(10), + Q => diff_pntr_pf_q(10), + R => xpm_fifo_rst_inst_n_1 + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => diff_pntr_pf_q0(11), + Q => diff_pntr_pf_q(11), + R => xpm_fifo_rst_inst_n_1 + ); +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => diff_pntr_pf_q0(12), + Q => diff_pntr_pf_q(12), + R => xpm_fifo_rst_inst_n_1 + ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -5259,28 +6826,30 @@ GND: unisim.vcomponents.GND Q => diff_pntr_pf_q(9), R => xpm_fifo_rst_inst_n_1 ); -\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2\: unisim.vcomponents.LUT4 +\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0080" + INIT => X"7FFFFFFFFFFFFFFF" ) port map ( - I0 => diff_pntr_pf_q(8), - I1 => diff_pntr_pf_q(9), - I2 => diff_pntr_pf_q(1), - I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0\, + I0 => diff_pntr_pf_q(1), + I1 => diff_pntr_pf_q(4), + I2 => diff_pntr_pf_q(5), + I3 => diff_pntr_pf_q(6), + I4 => diff_pntr_pf_q(7), + I5 => diff_pntr_pf_q(8), O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2_n_0\ ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FDFFFFFFFFFFFFFF" + INIT => X"0400000000000000" ) port map ( - I0 => diff_pntr_pf_q(7), - I1 => diff_pntr_pf_q(2), - I2 => diff_pntr_pf_q(3), - I3 => diff_pntr_pf_q(4), - I4 => diff_pntr_pf_q(5), - I5 => diff_pntr_pf_q(6), + I0 => diff_pntr_pf_q(3), + I1 => diff_pntr_pf_q(11), + I2 => diff_pntr_pf_q(2), + I3 => diff_pntr_pf_q(12), + I4 => diff_pntr_pf_q(9), + I5 => diff_pntr_pf_q(10), O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0\ ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\: unisim.vcomponents.FDSE @@ -5290,7 +6859,7 @@ GND: unisim.vcomponents.GND port map ( C => wr_clk, CE => '1', - D => rst_d1_inst_n_1, + D => rst_d1_inst_n_2, Q => \^prog_full\, S => xpm_fifo_rst_inst_n_1 ); @@ -5301,7 +6870,7 @@ GND: unisim.vcomponents.GND port map ( C => wr_clk, CE => '1', - D => ram_rd_en_pf, + D => rdp_inst_n_1, Q => ram_rd_en_pf_q, R => xpm_fifo_rst_inst_n_1 ); @@ -5318,8 +6887,8 @@ GND: unisim.vcomponents.GND ); \gen_sdpram.xpm_memory_base_inst\: entity work.design_1_axi_fifo_mm_s_0_0_xpm_memory_base port map ( - addra(8 downto 0) => wr_pntr_ext(8 downto 0), - addrb(8 downto 0) => rd_pntr_ext(8 downto 0), + addra(11 downto 0) => wr_pntr_ext(11 downto 0), + addrb(11 downto 0) => rd_pntr_ext(11 downto 0), clka => wr_clk, clkb => '0', dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\, @@ -5329,7 +6898,7 @@ GND: unisim.vcomponents.GND douta(52 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(52 downto 0), doutb(52 downto 0) => dout(52 downto 0), ena => '0', - enb => ram_rd_en_pf, + enb => rdp_inst_n_1, injectdbiterra => '0', injectdbiterrb => '0', injectsbiterra => '0', @@ -5346,11 +6915,11 @@ GND: unisim.vcomponents.GND ); \gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"4A" + INIT => X"2C" ) port map ( - I0 => curr_fwft_state(0), - I1 => rd_en, + I0 => rd_en, + I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), O => \gen_fwft.ram_regout_en\ ); @@ -5362,6 +6931,30 @@ GND: unisim.vcomponents.GND Q => rd_data_count(0), R => \grdc.rd_data_count_i0\ ); +\grdc.rd_data_count_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => wr_clk, + CE => '1', + D => \grdc.diff_wr_rd_pntr_rdc\(10), + Q => rd_data_count(10), + R => \grdc.rd_data_count_i0\ + ); +\grdc.rd_data_count_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => wr_clk, + CE => '1', + D => \grdc.diff_wr_rd_pntr_rdc\(11), + Q => rd_data_count(11), + R => \grdc.rd_data_count_i0\ + ); +\grdc.rd_data_count_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => wr_clk, + CE => '1', + D => \grdc.diff_wr_rd_pntr_rdc\(12), + Q => rd_data_count(12), + R => \grdc.rd_data_count_i0\ + ); \grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => wr_clk, @@ -5442,6 +7035,30 @@ GND: unisim.vcomponents.GND Q => wr_data_count(0), R => xpm_fifo_rst_inst_n_1 ); +\gwdc.wr_data_count_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => wr_clk, + CE => '1', + D => \grdc.diff_wr_rd_pntr_rdc\(10), + Q => wr_data_count(10), + R => xpm_fifo_rst_inst_n_1 + ); +\gwdc.wr_data_count_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => wr_clk, + CE => '1', + D => \grdc.diff_wr_rd_pntr_rdc\(11), + Q => wr_data_count(11), + R => xpm_fifo_rst_inst_n_1 + ); +\gwdc.wr_data_count_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => wr_clk, + CE => '1', + D => \grdc.diff_wr_rd_pntr_rdc\(12), + Q => wr_data_count(12), + R => xpm_fifo_rst_inst_n_1 + ); \gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => wr_clk, @@ -5517,138 +7134,220 @@ GND: unisim.vcomponents.GND rdp_inst: entity work.\design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2\ port map ( CO(0) => leaving_empty0, - D(8 downto 0) => diff_pntr_pf_q0(9 downto 1), - E(0) => ram_rd_en_pf, + DI(0) => rdp_inst_n_2, \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ => rdp_inst_n_1, - Q(9) => rdp_inst_n_3, - Q(8 downto 0) => rd_pntr_ext(8 downto 0), - S(0) => wrpp1_inst_n_10, + Q(11 downto 0) => rd_pntr_ext(11 downto 0), + S(0) => rdp_inst_n_15, almost_full => \^almost_full\, - \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1, - \count_value_i_reg[8]_0\(8 downto 0) => diff_pntr_pe(8 downto 0), - \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg\(0) => going_afull1, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ => rdp_inst_n_0, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\ => rdp_inst_n_32, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\ => xpm_fifo_rst_inst_n_3, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_0\ => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_1\ => rst_d1_inst_n_2, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_2\(1 downto 0) => curr_fwft_state(1 downto 0), - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(8) => wrpp1_inst_n_0, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(7) => wrpp1_inst_n_1, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(6) => wrpp1_inst_n_2, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(5) => wrpp1_inst_n_3, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(4) => wrpp1_inst_n_4, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(3) => wrpp1_inst_n_5, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(2) => wrpp1_inst_n_6, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(1) => wrpp1_inst_n_7, - \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_2_0\(0) => wrpp1_inst_n_8, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\(0) => xpm_fifo_rst_inst_n_8, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(7 downto 0) => wr_pntr_ext(7 downto 0), - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[8]\(0) => wrp_inst_n_21, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\(0) => wrpp1_inst_n_9, + clr_full => clr_full, + \count_value_i_reg[0]_0\(0) => rdp_inst_n_31, + \count_value_i_reg[0]_1\(1 downto 0) => curr_fwft_state(1 downto 0), + \count_value_i_reg[0]_2\(0) => xpm_fifo_rst_inst_n_1, + \count_value_i_reg[11]_0\(0) => rdp_inst_n_17, + \count_value_i_reg[11]_1\(3) => rdp_inst_n_27, + \count_value_i_reg[11]_1\(2) => rdp_inst_n_28, + \count_value_i_reg[11]_1\(1) => rdp_inst_n_29, + \count_value_i_reg[11]_1\(0) => rdp_inst_n_30, + \count_value_i_reg[1]_0\(0) => rdp_inst_n_16, + \count_value_i_reg[1]_1\(0) => rdp_inst_n_32, + \count_value_i_reg[3]_0\(2) => rdp_inst_n_20, + \count_value_i_reg[3]_0\(1) => rdp_inst_n_21, + \count_value_i_reg[3]_0\(0) => rdp_inst_n_22, + \count_value_i_reg[7]_0\(3) => rdp_inst_n_23, + \count_value_i_reg[7]_0\(2) => rdp_inst_n_24, + \count_value_i_reg[7]_0\(1) => rdp_inst_n_25, + \count_value_i_reg[7]_0\(0) => rdp_inst_n_26, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(11) => wrpp2_inst_n_0, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(10) => wrpp2_inst_n_1, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(9) => wrpp2_inst_n_2, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(8) => wrpp2_inst_n_3, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(7) => wrpp2_inst_n_4, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(6) => wrpp2_inst_n_5, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(5) => wrpp2_inst_n_6, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(4) => wrpp2_inst_n_7, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(3) => wrpp2_inst_n_8, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(2) => wrpp2_inst_n_9, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(1) => wrpp2_inst_n_10, + \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_i_3_0\(0) => wrpp2_inst_n_11, + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ => rdp_inst_n_19, + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\ => rdp_inst_n_33, + \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\ => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(11) => wrpp1_inst_n_0, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(10) => wrpp1_inst_n_1, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(9) => wrpp1_inst_n_2, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(8) => wrpp1_inst_n_3, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(7) => wrpp1_inst_n_4, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(6) => wrpp1_inst_n_5, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(5) => wrpp1_inst_n_6, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(4) => wrpp1_inst_n_7, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(3) => wrpp1_inst_n_8, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(2) => wrpp1_inst_n_9, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(1) => wrpp1_inst_n_10, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(0) => wrpp1_inst_n_11, + \grdc.rd_data_count_i_reg[12]\(12) => wrp_inst_n_1, + \grdc.rd_data_count_i_reg[12]\(11 downto 0) => wr_pntr_ext(11 downto 0), + \grdc.rd_data_count_i_reg[3]\(0) => count_value_i(1), ram_empty_i => ram_empty_i, + ram_wr_en_pf => ram_wr_en_pf, rd_en => rd_en, rst => rst, - \syncstages_ff_reg[3]\ => rdp_inst_n_2, + \syncstages_ff_reg[3]\ => rdp_inst_n_0, wr_clk => wr_clk ); rdpp1_inst: entity work.\design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3\ port map ( - CO(0) => going_empty1, - E(0) => ram_rd_en_pf, - Q(8 downto 0) => wr_pntr_ext(8 downto 0), - \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1, - \count_value_i_reg[4]_0\ => rdp_inst_n_1, + Q(11) => rdpp1_inst_n_0, + Q(10) => rdpp1_inst_n_1, + Q(9) => rdpp1_inst_n_2, + Q(8) => rdpp1_inst_n_3, + Q(7) => rdpp1_inst_n_4, + Q(6) => rdpp1_inst_n_5, + Q(5) => rdpp1_inst_n_6, + Q(4) => rdpp1_inst_n_7, + Q(3) => rdpp1_inst_n_8, + Q(2) => rdpp1_inst_n_9, + Q(1) => rdpp1_inst_n_10, + Q(0) => rdpp1_inst_n_11, + \count_value_i_reg[0]_0\ => rdp_inst_n_1, + \count_value_i_reg[0]_1\(0) => xpm_fifo_rst_inst_n_1, wr_clk => wr_clk ); rst_d1_inst: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_reg_bit port map ( Q(0) => xpm_fifo_rst_inst_n_1, + clr_full => clr_full, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2_n_0\, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg\ => rst_d1_inst_n_1, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg_0\ => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_3_n_0\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg\ => rst_d1_inst_n_2, prog_full => \^prog_full\, ram_rd_en_pf_q => ram_rd_en_pf_q, ram_wr_en_pf_q => ram_wr_en_pf_q, rst => rst, rst_d1 => rst_d1, - \syncstages_ff_reg[3]\ => rst_d1_inst_n_2, wr_clk => wr_clk ); wrp_inst: entity work.\design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized2_0\ port map ( CO(0) => leaving_empty0, - D(9 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(9 downto 0), + D(12 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(12 downto 0), + DI(1) => rdp_inst_n_16, DI(0) => \gen_fwft.rdpp1_inst_n_3\, - E(0) => ram_wr_en_pf, - Q(8 downto 0) => wr_pntr_ext(8 downto 0), - S(1) => \gen_fwft.rdpp1_inst_n_1\, - S(0) => \gen_fwft.rdpp1_inst_n_2\, - \count_value_i_reg[8]_0\(0) => wrp_inst_n_21, - \count_value_i_reg[9]_0\(0) => xpm_fifo_rst_inst_n_1, + Q(12) => wrp_inst_n_1, + Q(11 downto 0) => wr_pntr_ext(11 downto 0), + S(0) => xpm_fifo_rst_inst_n_7, + \count_value_i_reg[10]_0\(11 downto 0) => diff_pntr_pe(11 downto 0), + \count_value_i_reg[12]_0\(0) => xpm_fifo_rst_inst_n_1, \gen_pntr_flags_cc.ram_empty_i_reg\ => rdp_inst_n_1, - \gen_pntr_flags_cc.ram_empty_i_reg_0\ => xpm_fifo_rst_inst_n_3, - \gen_pntr_flags_cc.ram_empty_i_reg_1\(0) => going_empty1, - \grdc.rd_data_count_i_reg[3]\(0) => count_value_i(1), - \grdc.rd_data_count_i_reg[9]\(9) => rdp_inst_n_3, - \grdc.rd_data_count_i_reg[9]\(8 downto 0) => rd_pntr_ext(8 downto 0), + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(11) => rdpp1_inst_n_0, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(10) => rdpp1_inst_n_1, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(9) => rdpp1_inst_n_2, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(8) => rdpp1_inst_n_3, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(7) => rdpp1_inst_n_4, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(6) => rdpp1_inst_n_5, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(5) => rdpp1_inst_n_6, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(4) => rdpp1_inst_n_7, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(3) => rdpp1_inst_n_8, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(2) => rdpp1_inst_n_9, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(1) => rdpp1_inst_n_10, + \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(0) => rdpp1_inst_n_11, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]\(3) => rdp_inst_n_27, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]\(2) => rdp_inst_n_28, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]\(1) => rdp_inst_n_29, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[11]\(0) => rdp_inst_n_30, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\(0) => \p_1_in__0\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0\(3) => rdp_inst_n_20, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0\(2) => rdp_inst_n_21, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0\(1) => rdp_inst_n_22, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]_0\(0) => xpm_fifo_rst_inst_n_11, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(3) => rdp_inst_n_23, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(2) => rdp_inst_n_24, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(1) => rdp_inst_n_25, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[7]\(0) => rdp_inst_n_26, + \grdc.rd_data_count_i_reg[11]\(9 downto 0) => rd_pntr_ext(11 downto 2), + \grdc.rd_data_count_i_reg[12]\(0) => rdp_inst_n_17, + \grdc.rd_data_count_i_reg[3]\(2) => rdp_inst_n_32, + \grdc.rd_data_count_i_reg[3]\(1) => \gen_fwft.rdpp1_inst_n_1\, + \grdc.rd_data_count_i_reg[3]\(0) => \gen_fwft.rdpp1_inst_n_2\, ram_empty_i => ram_empty_i, ram_empty_i0 => ram_empty_i0, + ram_wr_en_pf => ram_wr_en_pf, wr_clk => wr_clk ); wrpp1_inst: entity work.\design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized3_1\ port map ( - E(0) => ram_wr_en_pf, - Q(8) => wrpp1_inst_n_0, - Q(7) => wrpp1_inst_n_1, - Q(6) => wrpp1_inst_n_2, - Q(5) => wrpp1_inst_n_3, - Q(4) => wrpp1_inst_n_4, - Q(3) => wrpp1_inst_n_5, - Q(2) => wrpp1_inst_n_6, - Q(1) => wrpp1_inst_n_7, - Q(0) => wrpp1_inst_n_8, - S(0) => wrpp1_inst_n_10, + D(11 downto 0) => diff_pntr_pf_q0(12 downto 1), + DI(0) => rdp_inst_n_2, + Q(11) => wrpp1_inst_n_0, + Q(10) => wrpp1_inst_n_1, + Q(9) => wrpp1_inst_n_2, + Q(8) => wrpp1_inst_n_3, + Q(7) => wrpp1_inst_n_4, + Q(6) => wrpp1_inst_n_5, + Q(5) => wrpp1_inst_n_6, + Q(4) => wrpp1_inst_n_7, + Q(3) => wrpp1_inst_n_8, + Q(2) => wrpp1_inst_n_9, + Q(1) => wrpp1_inst_n_10, + Q(0) => wrpp1_inst_n_11, + S(0) => xpm_fifo_rst_inst_n_8, \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1, - \count_value_i_reg[4]_0\ => xpm_fifo_rst_inst_n_3, - \count_value_i_reg[8]_0\(0) => wrpp1_inst_n_9, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\ => rdp_inst_n_1, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\(2 downto 1) => rd_pntr_ext(8 downto 7), - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[9]\(0) => rd_pntr_ext(0), + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]\(0) => rdp_inst_n_15, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[12]_0\(10 downto 0) => rd_pntr_ext(10 downto 0), + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\(0) => rdp_inst_n_31, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]_0\ => rdp_inst_n_1, + ram_wr_en_pf => ram_wr_en_pf, wr_clk => wr_clk ); wrpp2_inst: entity work.\design_1_axi_fifo_mm_s_0_0_xpm_counter_updn__parameterized0\ port map ( - E(0) => ram_wr_en_pf, - Q(8 downto 0) => rd_pntr_ext(8 downto 0), + Q(11) => wrpp2_inst_n_0, + Q(10) => wrpp2_inst_n_1, + Q(9) => wrpp2_inst_n_2, + Q(8) => wrpp2_inst_n_3, + Q(7) => wrpp2_inst_n_4, + Q(6) => wrpp2_inst_n_5, + Q(5) => wrpp2_inst_n_6, + Q(4) => wrpp2_inst_n_7, + Q(3) => wrpp2_inst_n_8, + Q(2) => wrpp2_inst_n_9, + Q(1) => wrpp2_inst_n_10, + Q(0) => wrpp2_inst_n_11, + S(0) => xpm_fifo_rst_inst_n_9, \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1, - \count_value_i_reg[4]_0\ => xpm_fifo_rst_inst_n_3, - \count_value_i_reg[7]_0\(0) => going_afull1, + ram_wr_en_pf => ram_wr_en_pf, wr_clk => wr_clk ); xpm_fifo_rst_inst: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_rst port map ( - E(0) => ram_wr_en_pf, Q(0) => xpm_fifo_rst_inst_n_1, - SR(0) => \gen_fwft.count_rst\, - \count_value_i_reg[1]\(1 downto 0) => curr_fwft_state(1 downto 0), - \gen_fwft.empty_fwft_i_reg\ => xpm_fifo_rst_inst_n_6, - \gen_fwft.empty_fwft_i_reg_0\ => xpm_fifo_rst_inst_n_7, - \gen_fwft.empty_fwft_i_reg_1\(0) => xpm_fifo_rst_inst_n_8, + S(0) => xpm_fifo_rst_inst_n_7, + SR(0) => \grdc.rd_data_count_i0\, + \count_value_i_reg[0]\(0) => xpm_fifo_rst_inst_n_8, + \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_9, + \count_value_i_reg[3]\(0) => wr_pntr_ext(0), + \count_value_i_reg[3]_0\(0) => wrpp1_inst_n_11, + \count_value_i_reg[3]_1\(0) => wrpp2_inst_n_11, + \gen_fwft.empty_fwft_i_reg\(0) => \p_1_in__0\, + \gen_fwft.empty_fwft_i_reg_0\(0) => xpm_fifo_rst_inst_n_11, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\(0) => rd_pntr_ext(0), \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ => xpm_fifo_rst_inst_n_0, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_0\ => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2_n_0\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg_1\ => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_3_n_0\, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\ => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\ => rdp_inst_n_1, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\ => \gen_fwft.empty_fwft_i_reg_n_0\, - \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ => xpm_fifo_rst_inst_n_3, - \gen_rst_cc.fifo_wr_rst_cc_reg[2]_1\(0) => \grdc.rd_data_count_i0\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\ => \gen_fwft.empty_fwft_i_reg_n_0\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_1\ => rdp_inst_n_1, + \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\(0) => \gen_fwft.count_rst\, + \grdc.rd_data_count_i_reg[0]\(1 downto 0) => curr_fwft_state(1 downto 0), prog_empty => \^prog_empty\, ram_empty_i => ram_empty_i, + ram_wr_en_pf => ram_wr_en_pf, + read_only => read_only, read_only_q => read_only_q, rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, + write_only => write_only, write_only_q => write_only_q ); end STRUCTURE; @@ -5666,23 +7365,21 @@ entity design_1_axi_fifo_mm_s_0_0_slave_attachment is s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 ); - \s_axi_wdata[25]\ : out STD_LOGIC; + \s_axi_wdata[27]\ : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\ : out STD_LOGIC; - sig_tx_channel_reset_reg : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2\ : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_rnw_i_reg_0 : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : out STD_LOGIC; - sig_txd_sb_wr_en : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 6 downto 0 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ : out STD_LOGIC; + sig_tx_channel_reset_reg : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ : out STD_LOGIC; + \s_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); bus2ip_rnw_i_reg_1 : out STD_LOGIC; - Bus_RNW_reg_reg_0 : out STD_LOGIC_VECTOR ( 12 downto 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 21 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 24 downto 0 ); sig_Bus2IP_Reset : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; cs_ce_clr : in STD_LOGIC; @@ -5693,8 +7390,8 @@ entity design_1_axi_fifo_mm_s_0_0_slave_attachment is s_axi_wvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 12 downto 0 ); - \sig_register_array_reg[0][6]\ : in STD_LOGIC; - sig_txd_sb_wr_en_reg : in STD_LOGIC; + axi_str_txd_tvalid : in STD_LOGIC; + axi_str_txd_tlast : in STD_LOGIC; IP2Bus_Error1_in : in STD_LOGIC; sig_str_rst_reg : in STD_LOGIC; \sig_ip2bus_data_reg[10]\ : in STD_LOGIC; @@ -5705,12 +7402,12 @@ entity design_1_axi_fifo_mm_s_0_0_slave_attachment is \sig_ip2bus_data_reg[6]\ : in STD_LOGIC; \sig_ip2bus_data_reg[4]\ : in STD_LOGIC; \sig_ip2bus_data_reg[3]\ : in STD_LOGIC; - sig_txd_sb_wr_en_reg_0 : in STD_LOGIC; + IP2Bus_Error_reg : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \s_axi_rdata_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 21 downto 0 ) + \s_axi_rdata_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 24 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_axi_fifo_mm_s_0_0_slave_attachment : entity is "slave_attachment"; @@ -5752,10 +7449,10 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_slave_attachment is attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[2]\ : label is "sm_read:1000,sm_write:0100,sm_resp:0001,sm_idle:0010"; attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[3]\ : label is "sm_read:1000,sm_write:0100,sm_resp:0001,sm_idle:0010"; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of IP2Bus_RdAck_i_2 : label is "soft_lutpair49"; - attribute SOFT_HLUTNM of IP2Bus_WrAck_i_2 : label is "soft_lutpair49"; - attribute SOFT_HLUTNM of \bus2ip_addr_i[2]_i_1\ : label is "soft_lutpair48"; - attribute SOFT_HLUTNM of bus2ip_rnw_i_i_2 : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of IP2Bus_RdAck_i_2 : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of IP2Bus_WrAck_i_2 : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \bus2ip_addr_i[2]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of bus2ip_rnw_i_i_2 : label is "soft_lutpair28"; begin s_axi_bresp(0) <= \^s_axi_bresp\(0); s_axi_bvalid <= \^s_axi_bvalid\; @@ -5885,29 +7582,31 @@ IP2Bus_WrAck_i_2: unisim.vcomponents.LUT1 I_DECODER: entity work.design_1_axi_fifo_mm_s_0_0_address_decoder port map ( Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg, - Bus_RNW_reg_reg_1(12 downto 0) => Bus_RNW_reg_reg_0(12 downto 0), D(6 downto 0) => D(6 downto 0), E(0) => E(0), \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\, \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_3\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\, - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_1\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\, + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_1\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\, + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_1\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0\(3) => \bus2ip_addr_i_reg_n_0_[5]\, \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0\(2) => \bus2ip_addr_i_reg_n_0_[4]\, \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0\(1) => \bus2ip_addr_i_reg_n_0_[3]\, \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]_0\(0) => \bus2ip_addr_i_reg_n_0_[2]\, IP2Bus_Error1_in => IP2Bus_Error1_in, + IP2Bus_Error_reg => IP2Bus_Error_reg, Q(6 downto 0) => Q(6 downto 0), + axi_str_txd_tlast => axi_str_txd_tlast, + axi_str_txd_tvalid => axi_str_txd_tvalid, cs_ce_clr => cs_ce_clr, s_axi_aclk => s_axi_aclk, s_axi_wdata(12 downto 0) => s_axi_wdata(12 downto 0), - \s_axi_wdata[25]\ => \s_axi_wdata[25]\, + \s_axi_wdata[27]\ => \s_axi_wdata[27]\, + \s_axi_wdata[31]\(12 downto 0) => \s_axi_wdata[31]\(12 downto 0), sig_Bus2IP_CS => sig_Bus2IP_CS, sig_Bus2IP_RNW => sig_Bus2IP_RNW, \sig_ip2bus_data_reg[10]\ => \sig_ip2bus_data_reg[10]\, @@ -5917,12 +7616,8 @@ I_DECODER: entity work.design_1_axi_fifo_mm_s_0_0_address_decoder \sig_ip2bus_data_reg[7]\ => \sig_ip2bus_data_reg[7]\, \sig_ip2bus_data_reg[8]\ => \sig_ip2bus_data_reg[8]\, \sig_ip2bus_data_reg[9]\ => \sig_ip2bus_data_reg[9]\, - \sig_register_array_reg[0][6]\ => \sig_register_array_reg[0][6]\, sig_str_rst_reg => sig_str_rst_reg, sig_tx_channel_reset_reg => sig_tx_channel_reset_reg, - sig_txd_sb_wr_en => sig_txd_sb_wr_en, - sig_txd_sb_wr_en_reg => sig_txd_sb_wr_en_reg, - sig_txd_sb_wr_en_reg_0 => sig_txd_sb_wr_en_reg_0, start2 => start2 ); \bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT4 @@ -6080,7 +7775,7 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => \^s_axi_bvalid\, R => rst ); -\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE +\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6091,6 +7786,39 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(9), R => rst ); +\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => \s_axi_rdata_i_reg[31]_0\(10), + Q => s_axi_rdata(10), + R => rst + ); +\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => \s_axi_rdata_i_reg[31]_0\(11), + Q => s_axi_rdata(11), + R => rst + ); +\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => \s_axi_rdata_i_reg[31]_0\(12), + Q => s_axi_rdata(12), + R => rst + ); \s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -6103,39 +7831,6 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE R => rst ); \s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => s_axi_rresp_i, - D => \s_axi_rdata_i_reg[31]_0\(10), - Q => s_axi_rdata(10), - R => rst - ); -\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => s_axi_rresp_i, - D => \s_axi_rdata_i_reg[31]_0\(11), - Q => s_axi_rdata(11), - R => rst - ); -\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => s_axi_rresp_i, - D => \s_axi_rdata_i_reg[31]_0\(12), - Q => s_axi_rdata(12), - R => rst - ); -\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6146,7 +7841,7 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(13), R => rst ); -\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE +\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6157,7 +7852,7 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(14), R => rst ); -\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE +\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6168,7 +7863,7 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(15), R => rst ); -\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE +\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6179,7 +7874,7 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(16), R => rst ); -\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE +\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6190,7 +7885,7 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(17), R => rst ); -\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE +\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6201,7 +7896,7 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(18), R => rst ); -\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE +\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) @@ -6212,6 +7907,39 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE Q => s_axi_rdata(19), R => rst ); +\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => \s_axi_rdata_i_reg[31]_0\(20), + Q => s_axi_rdata(20), + R => rst + ); +\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => \s_axi_rdata_i_reg[31]_0\(21), + Q => s_axi_rdata(21), + R => rst + ); +\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => \s_axi_rdata_i_reg[31]_0\(22), + Q => s_axi_rdata(22), + R => rst + ); \s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -6230,8 +7958,8 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => s_axi_rresp_i, - D => \s_axi_rdata_i_reg[31]_0\(20), - Q => s_axi_rdata(20), + D => \s_axi_rdata_i_reg[31]_0\(23), + Q => s_axi_rdata(23), R => rst ); \s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE @@ -6241,8 +7969,8 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => s_axi_rresp_i, - D => \s_axi_rdata_i_reg[31]_0\(21), - Q => s_axi_rdata(21), + D => \s_axi_rdata_i_reg[31]_0\(24), + Q => s_axi_rdata(24), R => rst ); \s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE @@ -6403,10 +8131,10 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); prog_full_axis : out STD_LOGIC; - wr_data_count_axis : out STD_LOGIC_VECTOR ( 9 downto 0 ); + wr_data_count_axis : out STD_LOGIC_VECTOR ( 12 downto 0 ); almost_full_axis : out STD_LOGIC; prog_empty_axis : out STD_LOGIC; - rd_data_count_axis : out STD_LOGIC_VECTOR ( 9 downto 0 ); + rd_data_count_axis : out STD_LOGIC_VECTOR ( 12 downto 0 ); almost_empty_axis : out STD_LOGIC; injectsbiterr_axis : in STD_LOGIC; injectdbiterr_axis : in STD_LOGIC; @@ -6436,11 +8164,11 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute EN_DATA_VALID_INT : string; attribute EN_DATA_VALID_INT of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is "1'b1"; attribute FIFO_DEPTH : integer; - attribute FIFO_DEPTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 512; + attribute FIFO_DEPTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 4096; attribute FIFO_MEMORY_TYPE : string; attribute FIFO_MEMORY_TYPE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is "BRAM"; attribute LOG_DEPTH_AXIS : integer; - attribute LOG_DEPTH_AXIS of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 9; + attribute LOG_DEPTH_AXIS of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 12; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is "xpm_fifo_axis"; attribute PACKET_FIFO : string; @@ -6450,7 +8178,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 5; attribute PROG_FULL_THRESH : integer; - attribute PROG_FULL_THRESH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 507; + attribute PROG_FULL_THRESH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 4091; attribute P_COMMON_CLOCK : integer; attribute P_COMMON_CLOCK of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 1; attribute P_ECC_MODE : integer; @@ -6460,7 +8188,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute P_PKT_MODE : integer; attribute P_PKT_MODE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 1; attribute RD_DATA_COUNT_WIDTH : integer; - attribute RD_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 10; + attribute RD_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 13; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 0; attribute SIM_ASSERT_CHK : integer; @@ -6492,7 +8220,7 @@ entity design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute USE_ADV_FEATURES_INT : integer; attribute USE_ADV_FEATURES_INT of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 826617925; attribute WR_DATA_COUNT_WIDTH : integer; - attribute WR_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 10; + attribute WR_DATA_COUNT_WIDTH of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is 13; attribute XPM_MODULE : string; attribute XPM_MODULE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis : entity is "TRUE"; attribute dont_touch : string; @@ -6689,7 +8417,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute ADDER_THRESHOLD of \gaxis_pkt_fifo_cc.axis_pkt_cnt_reg[4]_i_1\ : label is 11; attribute ADDER_THRESHOLD of \gaxis_pkt_fifo_cc.axis_pkt_cnt_reg[8]_i_1\ : label is 11; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gaxis_pkt_fifo_cc.axis_pkt_read_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \gaxis_pkt_fifo_cc.axis_pkt_read_i_1\ : label is "soft_lutpair5"; attribute COMPARATOR_THRESHOLD : integer; attribute COMPARATOR_THRESHOLD of \gaxis_pkt_fifo_cc.axis_pkt_read_reg_i_15\ : label is 6; attribute COMPARATOR_THRESHOLD of \gaxis_pkt_fifo_cc.axis_pkt_read_reg_i_2\ : label is 6; @@ -6711,7 +8439,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute XPM_CDC : string; attribute XPM_CDC of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is "SYNC_RST"; attribute XPM_MODULE of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is "TRUE"; - attribute SOFT_HLUTNM of m_axis_tvalid_INST_0 : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of m_axis_tvalid_INST_0 : label is "soft_lutpair5"; attribute CASCADE_HEIGHT of xpm_fifo_base_inst : label is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 2; @@ -6752,13 +8480,13 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 2; attribute FIFO_READ_DEPTH : integer; - attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 512; + attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 4096; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 0; attribute FIFO_SIZE : integer; - attribute FIFO_SIZE of xpm_fifo_base_inst : label is 27136; + attribute FIFO_SIZE of xpm_fifo_base_inst : label is 217088; attribute FIFO_WRITE_DEPTH : integer; - attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 512; + attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 4096; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 1; attribute FULL_RST_VAL : string; @@ -6767,26 +8495,26 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 3; attribute PE_THRESH_MAX : integer; - attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 507; + attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 4091; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5; attribute PF_THRESH_ADJ : integer; - attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 505; + attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 4089; attribute PF_THRESH_MAX : integer; - attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 507; + attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 4091; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5; attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 5; - attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 507; - attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 10; + attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 4091; + attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 13; attribute RD_DC_WIDTH_EXT : integer; - attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 10; + attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 13; attribute RD_LATENCY : integer; attribute RD_LATENCY of xpm_fifo_base_inst : label is 2; attribute RD_MODE : integer; attribute RD_MODE of xpm_fifo_base_inst : label is 1; attribute RD_PNTR_WIDTH : integer; - attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 9; + attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 12; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 53; attribute READ_MODE : integer; @@ -6804,13 +8532,13 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis is attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 53; - attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 10; + attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 13; attribute WR_DC_WIDTH_EXT : integer; - attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 10; + attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 13; attribute WR_DEPTH_LOG : integer; - attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 9; + attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 12; attribute WR_PNTR_WIDTH : integer; - attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 9; + attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 12; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0; attribute WR_WIDTH_LOG : integer; @@ -8121,7 +9849,7 @@ xpm_fifo_base_inst: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_base prog_empty => prog_empty_axis, prog_full => prog_full_axis, rd_clk => '0', - rd_data_count(9 downto 0) => rd_data_count_axis(9 downto 0), + rd_data_count(12 downto 0) => rd_data_count_axis(12 downto 0), rd_en => axis_rd_eop1, rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED, rst => rst_axis, @@ -8130,7 +9858,7 @@ xpm_fifo_base_inst: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_base underflow => NLW_xpm_fifo_base_inst_underflow_UNCONNECTED, wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED, wr_clk => s_aclk, - wr_data_count(9 downto 0) => wr_data_count_axis(9 downto 0), + wr_data_count(12 downto 0) => wr_data_count_axis(12 downto 0), wr_en => s_axis_tvalid, wr_rst_busy => NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED ); @@ -8159,23 +9887,21 @@ entity design_1_axi_fifo_mm_s_0_0_axi_lite_ipif is s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 ); - \s_axi_wdata[25]\ : out STD_LOGIC; + \s_axi_wdata[27]\ : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\ : out STD_LOGIC; - sig_tx_channel_reset_reg : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\ : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_rnw_i_reg : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : out STD_LOGIC; - sig_txd_sb_wr_en : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 6 downto 0 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ : out STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ : out STD_LOGIC; + sig_tx_channel_reset_reg : out STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ : out STD_LOGIC; + \s_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); bus2ip_rnw_i_reg_0 : out STD_LOGIC; - Bus_RNW_reg_reg : out STD_LOGIC_VECTOR ( 12 downto 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 21 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 24 downto 0 ); sig_Bus2IP_Reset : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; cs_ce_clr : in STD_LOGIC; @@ -8186,8 +9912,8 @@ entity design_1_axi_fifo_mm_s_0_0_axi_lite_ipif is s_axi_wvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 12 downto 0 ); - \sig_register_array_reg[0][6]\ : in STD_LOGIC; - sig_txd_sb_wr_en_reg : in STD_LOGIC; + axi_str_txd_tvalid : in STD_LOGIC; + axi_str_txd_tlast : in STD_LOGIC; IP2Bus_Error1_in : in STD_LOGIC; sig_str_rst_reg : in STD_LOGIC; \sig_ip2bus_data_reg[10]\ : in STD_LOGIC; @@ -8198,12 +9924,12 @@ entity design_1_axi_fifo_mm_s_0_0_axi_lite_ipif is \sig_ip2bus_data_reg[6]\ : in STD_LOGIC; \sig_ip2bus_data_reg[4]\ : in STD_LOGIC; \sig_ip2bus_data_reg[3]\ : in STD_LOGIC; - sig_txd_sb_wr_en_reg_0 : in STD_LOGIC; + IP2Bus_Error_reg : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \s_axi_rdata_i_reg[31]\ : in STD_LOGIC_VECTOR ( 21 downto 0 ) + \s_axi_rdata_i_reg[31]\ : in STD_LOGIC_VECTOR ( 24 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_axi_fifo_mm_s_0_0_axi_lite_ipif : entity is "axi_lite_ipif"; @@ -8214,23 +9940,24 @@ begin I_SLAVE_ATTACHMENT: entity work.design_1_axi_fifo_mm_s_0_0_slave_attachment port map ( Bus_RNW_reg_reg => Bus_RNW_reg, - Bus_RNW_reg_reg_0(12 downto 0) => Bus_RNW_reg_reg(12 downto 0), D(6 downto 0) => D(6 downto 0), E(0) => E(0), \FSM_onehot_state_reg[2]_0\ => \FSM_onehot_state_reg[2]\, \FSM_onehot_state_reg[3]_0\ => \FSM_onehot_state_reg[3]\, \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_2\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\, - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\, + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\, + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, IP2Bus_Error1_in => IP2Bus_Error1_in, + IP2Bus_Error_reg => IP2Bus_Error_reg, Q(6 downto 0) => Q(6 downto 0), + axi_str_txd_tlast => axi_str_txd_tlast, + axi_str_txd_tvalid => axi_str_txd_tvalid, bus2ip_rnw_i_reg_0 => bus2ip_rnw_i_reg, bus2ip_rnw_i_reg_1 => bus2ip_rnw_i_reg_0, cs_ce_clr => cs_ce_clr, @@ -8243,13 +9970,14 @@ I_SLAVE_ATTACHMENT: entity work.design_1_axi_fifo_mm_s_0_0_slave_attachment s_axi_bready => s_axi_bready, s_axi_bresp(0) => s_axi_bresp(0), s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(21 downto 0) => s_axi_rdata(21 downto 0), - \s_axi_rdata_i_reg[31]_0\(21 downto 0) => \s_axi_rdata_i_reg[31]\(21 downto 0), + s_axi_rdata(24 downto 0) => s_axi_rdata(24 downto 0), + \s_axi_rdata_i_reg[31]_0\(24 downto 0) => \s_axi_rdata_i_reg[31]\(24 downto 0), s_axi_rready => s_axi_rready, s_axi_rresp(0) => s_axi_rresp(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(12 downto 0) => s_axi_wdata(12 downto 0), - \s_axi_wdata[25]\ => \s_axi_wdata[25]\, + \s_axi_wdata[27]\ => \s_axi_wdata[27]\, + \s_axi_wdata[31]\(12 downto 0) => \s_axi_wdata[31]\(12 downto 0), s_axi_wvalid => s_axi_wvalid, sig_Bus2IP_CS => sig_Bus2IP_CS, sig_Bus2IP_Reset => sig_Bus2IP_Reset, @@ -8260,12 +9988,8 @@ I_SLAVE_ATTACHMENT: entity work.design_1_axi_fifo_mm_s_0_0_slave_attachment \sig_ip2bus_data_reg[7]\ => \sig_ip2bus_data_reg[7]\, \sig_ip2bus_data_reg[8]\ => \sig_ip2bus_data_reg[8]\, \sig_ip2bus_data_reg[9]\ => \sig_ip2bus_data_reg[9]\, - \sig_register_array_reg[0][6]\ => \sig_register_array_reg[0][6]\, sig_str_rst_reg => sig_str_rst_reg, - sig_tx_channel_reset_reg => sig_tx_channel_reset_reg, - sig_txd_sb_wr_en => sig_txd_sb_wr_en, - sig_txd_sb_wr_en_reg => sig_txd_sb_wr_en_reg, - sig_txd_sb_wr_en_reg_0 => sig_txd_sb_wr_en_reg_0 + sig_tx_channel_reset_reg => sig_tx_channel_reset_reg ); end STRUCTURE; library IEEE; @@ -8278,38 +10002,34 @@ entity design_1_axi_fifo_mm_s_0_0_axis_fg is axi_str_txd_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); axi_str_txd_tlast : out STD_LOGIC; prog_full_axis : out STD_LOGIC; - wr_data_count_axis : out STD_LOGIC_VECTOR ( 0 to 0 ); + wr_data_count_axis : out STD_LOGIC_VECTOR ( 10 downto 0 ); prog_empty_axis : out STD_LOGIC; s_aresetn : out STD_LOGIC; - \gen_wr_a.gen_word_narrow.mem_reg\ : out STD_LOGIC; sig_txd_wr_en : out STD_LOGIC; - \gwdc.wr_data_count_i_reg[9]\ : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \gwdc.wr_data_count_i_reg[12]\ : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gwdc.wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gwdc.wr_data_count_i_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gwdc.wr_data_count_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ : out STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ : out STD_LOGIC; IP2Bus_Error_reg : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \gen_wr_a.gen_word_narrow.mem_reg_0\ : in STD_LOGIC; + \gen_wr_a.gen_word_narrow.mem_reg_5\ : in STD_LOGIC; axi_str_txd_tready : in STD_LOGIC; start_wr : in STD_LOGIC; txd_wr_en : in STD_LOGIC; - \sig_register_array_reg[0][4]\ : in STD_LOGIC; - \sig_register_array_reg[0][4]_0\ : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 ); IP2Bus_Error_reg_0 : in STD_LOGIC; sig_txd_prog_full_d1 : in STD_LOGIC; sig_txd_prog_empty_d1 : in STD_LOGIC; - \gen_wr_a.gen_word_narrow.mem_reg_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_wr_a.gen_word_narrow.mem_reg_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn : in STD_LOGIC; IP2Bus_Error_reg_1 : in STD_LOGIC; Axi_Str_RxD_AReset : in STD_LOGIC; - mm2s_prmry_reset_out_n : in STD_LOGIC; - \sig_txd_wr_data_reg[0]\ : in STD_LOGIC; - \sig_txd_wr_data_reg[0]_0\ : in STD_LOGIC; - \sig_txd_wr_data_reg[0]_1\ : in STD_LOGIC + mm2s_prmry_reset_out_n : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_axi_fifo_mm_s_0_0_axis_fg : entity is "axis_fg"; @@ -8337,23 +10057,22 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axis_fg is signal COMP_FIFO_n_52 : STD_LOGIC; signal COMP_FIFO_n_53 : STD_LOGIC; signal COMP_FIFO_n_54 : STD_LOGIC; - signal \^axi_str_txd_tlast\ : STD_LOGIC; - signal \^axi_str_txd_tvalid\ : STD_LOGIC; - signal \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\ : STD_LOGIC; - signal \^gwdc.wr_data_count_i_reg[9]\ : STD_LOGIC; + signal \^gwdc.wr_data_count_i_reg[12]\ : STD_LOGIC; signal input_tstrb : STD_LOGIC_VECTOR ( 2 downto 1 ); signal input_tvalid : STD_LOGIC; signal \^prog_empty_axis\ : STD_LOGIC; signal \^prog_full_axis\ : STD_LOGIC; signal \^s_aresetn\ : STD_LOGIC; signal s_axis_tready_i : STD_LOGIC; - signal sig_txd_occupancy : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal \^wr_data_count_axis\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \sig_register_array[0][3]_i_4_n_0\ : STD_LOGIC; + signal \sig_register_array[0][3]_i_5_n_0\ : STD_LOGIC; + signal sig_txd_occupancy : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \^wr_data_count_axis\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_COMP_FIFO_almost_empty_axis_UNCONNECTED : STD_LOGIC; signal NLW_COMP_FIFO_almost_full_axis_UNCONNECTED : STD_LOGIC; signal NLW_COMP_FIFO_dbiterr_axis_UNCONNECTED : STD_LOGIC; signal NLW_COMP_FIFO_sbiterr_axis_UNCONNECTED : STD_LOGIC; - signal NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); attribute AXIS_DATA_WIDTH : integer; attribute AXIS_DATA_WIDTH of COMP_FIFO : label is 53; attribute AXIS_FINAL_DATA_WIDTH : integer; @@ -8377,11 +10096,11 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axis_fg is attribute EN_DATA_VALID_INT : string; attribute EN_DATA_VALID_INT of COMP_FIFO : label is "1'b1"; attribute FIFO_DEPTH : integer; - attribute FIFO_DEPTH of COMP_FIFO : label is 512; + attribute FIFO_DEPTH of COMP_FIFO : label is 4096; attribute FIFO_MEMORY_TYPE : string; attribute FIFO_MEMORY_TYPE of COMP_FIFO : label is "BRAM"; attribute LOG_DEPTH_AXIS : integer; - attribute LOG_DEPTH_AXIS of COMP_FIFO : label is 9; + attribute LOG_DEPTH_AXIS of COMP_FIFO : label is 12; attribute PACKET_FIFO : string; attribute PACKET_FIFO of COMP_FIFO : label is "true"; attribute PKT_SIZE_LT8 : string; @@ -8389,7 +10108,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axis_fg is attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of COMP_FIFO : label is 5; attribute PROG_FULL_THRESH : integer; - attribute PROG_FULL_THRESH of COMP_FIFO : label is 507; + attribute PROG_FULL_THRESH of COMP_FIFO : label is 4091; attribute P_COMMON_CLOCK : integer; attribute P_COMMON_CLOCK of COMP_FIFO : label is 1; attribute P_ECC_MODE : integer; @@ -8399,7 +10118,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axis_fg is attribute P_PKT_MODE : integer; attribute P_PKT_MODE of COMP_FIFO : label is 1; attribute RD_DATA_COUNT_WIDTH : integer; - attribute RD_DATA_COUNT_WIDTH of COMP_FIFO : label is 10; + attribute RD_DATA_COUNT_WIDTH of COMP_FIFO : label is 13; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of COMP_FIFO : label is 0; attribute SIM_ASSERT_CHK : integer; @@ -8431,28 +10150,18 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axis_fg is attribute USE_ADV_FEATURES_INT : integer; attribute USE_ADV_FEATURES_INT of COMP_FIFO : label is 826617925; attribute WR_DATA_COUNT_WIDTH : integer; - attribute WR_DATA_COUNT_WIDTH of COMP_FIFO : label is 10; + attribute WR_DATA_COUNT_WIDTH of COMP_FIFO : label is 13; attribute XPM_MODULE : string; attribute XPM_MODULE of COMP_FIFO : label is "TRUE"; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of IP2Bus_Error_i_1 : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[2]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[3]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[4]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[5]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[6]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[7]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[8]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \gfifo_gen.gmm2s.vacancy_i[9]_i_3\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of sig_txd_wr_en_i_1 : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of IP2Bus_Error_i_1 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of sig_txd_wr_en_i_1 : label is "soft_lutpair6"; begin - axi_str_txd_tlast <= \^axi_str_txd_tlast\; - axi_str_txd_tvalid <= \^axi_str_txd_tvalid\; - \gwdc.wr_data_count_i_reg[9]\ <= \^gwdc.wr_data_count_i_reg[9]\; + \gwdc.wr_data_count_i_reg[12]\ <= \^gwdc.wr_data_count_i_reg[12]\; prog_empty_axis <= \^prog_empty_axis\; prog_full_axis <= \^prog_full_axis\; s_aresetn <= \^s_aresetn\; - wr_data_count_axis(0) <= \^wr_data_count_axis\(0); + wr_data_count_axis(10 downto 0) <= \^wr_data_count_axis\(10 downto 0); COMP_FIFO: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis port map ( almost_empty_axis => NLW_COMP_FIFO_almost_empty_axis_UNCONNECTED, @@ -8474,7 +10183,7 @@ COMP_FIFO: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis m_axis_tkeep(2) => COMP_FIFO_n_39, m_axis_tkeep(1) => COMP_FIFO_n_40, m_axis_tkeep(0) => COMP_FIFO_n_41, - m_axis_tlast => \^axi_str_txd_tlast\, + m_axis_tlast => axi_str_txd_tlast, m_axis_tready => axi_str_txd_tready, m_axis_tstrb(3) => COMP_FIFO_n_34, m_axis_tstrb(2) => COMP_FIFO_n_35, @@ -8484,17 +10193,17 @@ COMP_FIFO: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis m_axis_tuser(2) => COMP_FIFO_n_52, m_axis_tuser(1) => COMP_FIFO_n_53, m_axis_tuser(0) => COMP_FIFO_n_54, - m_axis_tvalid => \^axi_str_txd_tvalid\, + m_axis_tvalid => axi_str_txd_tvalid, prog_empty_axis => \^prog_empty_axis\, prog_full_axis => \^prog_full_axis\, - rd_data_count_axis(9 downto 0) => NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED(9 downto 0), + rd_data_count_axis(12 downto 0) => NLW_COMP_FIFO_rd_data_count_axis_UNCONNECTED(12 downto 0), s_aclk => s_axi_aclk, s_aresetn => \^s_aresetn\, s_axis_tdata(31 downto 0) => Q(31 downto 0), s_axis_tdest(3 downto 0) => B"0000", s_axis_tid(3 downto 0) => B"0000", s_axis_tkeep(3 downto 0) => B"0000", - s_axis_tlast => \gen_wr_a.gen_word_narrow.mem_reg_0\, + s_axis_tlast => \gen_wr_a.gen_word_narrow.mem_reg_5\, s_axis_tready => s_axis_tready_i, s_axis_tstrb(3) => COMP_FIFO_i_2_n_0, s_axis_tstrb(2 downto 1) => input_tstrb(2 downto 1), @@ -8502,8 +10211,8 @@ COMP_FIFO: entity work.design_1_axi_fifo_mm_s_0_0_xpm_fifo_axis s_axis_tuser(3 downto 0) => B"0000", s_axis_tvalid => input_tvalid, sbiterr_axis => NLW_COMP_FIFO_sbiterr_axis_UNCONNECTED, - wr_data_count_axis(9 downto 2) => sig_txd_occupancy(9 downto 2), - wr_data_count_axis(1) => \^wr_data_count_axis\(0), + wr_data_count_axis(12) => sig_txd_occupancy(12), + wr_data_count_axis(11 downto 1) => \^wr_data_count_axis\(10 downto 0), wr_data_count_axis(0) => sig_txd_occupancy(0) ); COMP_FIFO_i_1: unisim.vcomponents.LUT3 @@ -8513,7 +10222,7 @@ COMP_FIFO_i_1: unisim.vcomponents.LUT3 port map ( I0 => start_wr, I1 => txd_wr_en, - I2 => \gen_wr_a.gen_word_narrow.mem_reg_0\, + I2 => \gen_wr_a.gen_word_narrow.mem_reg_5\, O => input_tvalid ); COMP_FIFO_i_2: unisim.vcomponents.LUT3 @@ -8521,9 +10230,9 @@ COMP_FIFO_i_2: unisim.vcomponents.LUT3 INIT => X"1F" ) port map ( - I0 => \gen_wr_a.gen_word_narrow.mem_reg_1\(0), - I1 => \gen_wr_a.gen_word_narrow.mem_reg_1\(1), - I2 => \gen_wr_a.gen_word_narrow.mem_reg_0\, + I0 => \gen_wr_a.gen_word_narrow.mem_reg_3\(0), + I1 => \gen_wr_a.gen_word_narrow.mem_reg_3\(1), + I2 => \gen_wr_a.gen_word_narrow.mem_reg_5\, O => COMP_FIFO_i_2_n_0 ); COMP_FIFO_i_3: unisim.vcomponents.LUT3 @@ -8531,9 +10240,9 @@ COMP_FIFO_i_3: unisim.vcomponents.LUT3 INIT => X"9F" ) port map ( - I0 => \gen_wr_a.gen_word_narrow.mem_reg_1\(0), - I1 => \gen_wr_a.gen_word_narrow.mem_reg_1\(1), - I2 => \gen_wr_a.gen_word_narrow.mem_reg_0\, + I0 => \gen_wr_a.gen_word_narrow.mem_reg_3\(0), + I1 => \gen_wr_a.gen_word_narrow.mem_reg_3\(1), + I2 => \gen_wr_a.gen_word_narrow.mem_reg_5\, O => input_tstrb(2) ); COMP_FIFO_i_4: unisim.vcomponents.LUT3 @@ -8541,118 +10250,126 @@ COMP_FIFO_i_4: unisim.vcomponents.LUT3 INIT => X"DF" ) port map ( - I0 => \gen_wr_a.gen_word_narrow.mem_reg_1\(0), - I1 => \gen_wr_a.gen_word_narrow.mem_reg_1\(1), - I2 => \gen_wr_a.gen_word_narrow.mem_reg_0\, + I0 => \gen_wr_a.gen_word_narrow.mem_reg_3\(0), + I1 => \gen_wr_a.gen_word_narrow.mem_reg_3\(1), + I2 => \gen_wr_a.gen_word_narrow.mem_reg_5\, O => input_tstrb(1) ); IP2Bus_Error_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"00AA03AA" + INIT => X"00AA30AA" ) port map ( I0 => p_1_in(0), I1 => IP2Bus_Error_reg_0, - I2 => \^gwdc.wr_data_count_i_reg[9]\, + I2 => \^gwdc.wr_data_count_i_reg[12]\, I3 => s_axi_aresetn, I4 => IP2Bus_Error_reg_1, O => IP2Bus_Error_reg ); -\gfifo_gen.gmm2s.vacancy_i[2]_i_1\: unisim.vcomponents.LUT2 +\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"9" + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(6), + O => \gwdc.wr_data_count_i_reg[7]\(3) + ); +\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(5), + O => \gwdc.wr_data_count_i_reg[7]\(2) + ); +\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(4), + O => \gwdc.wr_data_count_i_reg[7]\(1) + ); +\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(3), + O => \gwdc.wr_data_count_i_reg[7]\(0) + ); +\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(10), + O => DI(3) + ); +\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(9), + O => DI(2) + ); +\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(8), + O => DI(1) + ); +\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(7), + O => DI(0) + ); +\minusOp_carry__2_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sig_txd_occupancy(12), + O => S(0) + ); +minusOp_carry_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(2), + O => \gwdc.wr_data_count_i_reg[3]\(2) + ); +minusOp_carry_i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^wr_data_count_axis\(1), + O => \gwdc.wr_data_count_i_reg[3]\(1) + ); +minusOp_carry_i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" ) port map ( I0 => \^wr_data_count_axis\(0), - I1 => sig_txd_occupancy(2), - O => D(0) + O => \gwdc.wr_data_count_i_reg[3]\(0) ); -\gfifo_gen.gmm2s.vacancy_i[3]_i_1\: unisim.vcomponents.LUT3 +minusOp_carry_i_4: unisim.vcomponents.LUT1 generic map( - INIT => X"95" + INIT => X"1" ) port map ( - I0 => sig_txd_occupancy(3), - I1 => \^wr_data_count_axis\(0), - I2 => sig_txd_occupancy(2), - O => D(1) - ); -\gfifo_gen.gmm2s.vacancy_i[4]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9555" - ) - port map ( - I0 => sig_txd_occupancy(4), - I1 => sig_txd_occupancy(3), - I2 => sig_txd_occupancy(2), - I3 => \^wr_data_count_axis\(0), - O => D(2) - ); -\gfifo_gen.gmm2s.vacancy_i[5]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\, - I1 => sig_txd_occupancy(5), - O => D(3) - ); -\gfifo_gen.gmm2s.vacancy_i[6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"87" - ) - port map ( - I0 => sig_txd_occupancy(5), - I1 => \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\, - I2 => sig_txd_occupancy(6), - O => D(4) - ); -\gfifo_gen.gmm2s.vacancy_i[7]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"870F" - ) - port map ( - I0 => sig_txd_occupancy(5), - I1 => \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\, - I2 => sig_txd_occupancy(7), - I3 => sig_txd_occupancy(6), - O => D(5) - ); -\gfifo_gen.gmm2s.vacancy_i[8]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"870F0F0F" - ) - port map ( - I0 => sig_txd_occupancy(5), - I1 => \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\, - I2 => sig_txd_occupancy(8), - I3 => sig_txd_occupancy(6), - I4 => sig_txd_occupancy(7), - O => D(6) - ); -\gfifo_gen.gmm2s.vacancy_i[9]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"78F0F0F0F0F0F0F0" - ) - port map ( - I0 => sig_txd_occupancy(5), - I1 => \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\, - I2 => sig_txd_occupancy(9), - I3 => sig_txd_occupancy(8), - I4 => sig_txd_occupancy(7), - I5 => sig_txd_occupancy(6), - O => D(7) - ); -\gfifo_gen.gmm2s.vacancy_i[9]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"8000" - ) - port map ( - I0 => sig_txd_occupancy(4), - I1 => sig_txd_occupancy(3), - I2 => sig_txd_occupancy(2), - I3 => \^wr_data_count_axis\(0), - O => \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\ + I0 => sig_txd_occupancy(0), + O => \gwdc.wr_data_count_i_reg[0]\(0) ); mm2s_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT3 generic map( @@ -8675,28 +10392,38 @@ mm2s_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT3 ); \sig_register_array[0][3]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"1555555555555555" + INIT => X"ABAAAAAAAAAAAAAA" ) port map ( - I0 => sig_txd_occupancy(9), - I1 => sig_txd_occupancy(6), - I2 => sig_txd_occupancy(5), - I3 => sig_txd_occupancy(8), - I4 => sig_txd_occupancy(7), - I5 => \gfifo_gen.gmm2s.vacancy_i[9]_i_3_n_0\, - O => \^gwdc.wr_data_count_i_reg[9]\ + I0 => sig_txd_occupancy(12), + I1 => \sig_register_array[0][3]_i_4_n_0\, + I2 => \sig_register_array[0][3]_i_5_n_0\, + I3 => \^wr_data_count_axis\(8), + I4 => \^wr_data_count_axis\(7), + I5 => \^wr_data_count_axis\(3), + O => \^gwdc.wr_data_count_i_reg[12]\ ); -\sig_register_array[0][4]_i_3\: unisim.vcomponents.LUT5 +\sig_register_array[0][3]_i_4\: unisim.vcomponents.LUT4 generic map( - INIT => X"F8FFF8F8" + INIT => X"7FFF" ) port map ( - I0 => \^axi_str_txd_tvalid\, - I1 => \^axi_str_txd_tlast\, - I2 => \sig_register_array_reg[0][4]\, - I3 => \sig_register_array_reg[0][4]_0\, - I4 => s_axi_wdata(0), - O => \gen_wr_a.gen_word_narrow.mem_reg\ + I0 => \^wr_data_count_axis\(1), + I1 => \^wr_data_count_axis\(4), + I2 => \^wr_data_count_axis\(6), + I3 => \^wr_data_count_axis\(10), + O => \sig_register_array[0][3]_i_4_n_0\ + ); +\sig_register_array[0][3]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \^wr_data_count_axis\(0), + I1 => \^wr_data_count_axis\(2), + I2 => \^wr_data_count_axis\(5), + I3 => \^wr_data_count_axis\(9), + O => \sig_register_array[0][3]_i_5_n_0\ ); \sig_register_array[0][9]_i_2\: unisim.vcomponents.LUT2 generic map( @@ -8707,25 +10434,12 @@ mm2s_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT3 I1 => sig_txd_prog_full_d1, O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ ); -\sig_txd_wr_data[31]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"000000002222F222" - ) - port map ( - I0 => \^gwdc.wr_data_count_i_reg[9]\, - I1 => IP2Bus_Error_reg_0, - I2 => \sig_txd_wr_data_reg[0]\, - I3 => \sig_txd_wr_data_reg[0]_0\, - I4 => \sig_txd_wr_data_reg[0]_1\, - I5 => IP2Bus_Error_reg_1, - O => E(0) - ); sig_txd_wr_en_i_1: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => \^gwdc.wr_data_count_i_reg[9]\, + I0 => \^gwdc.wr_data_count_i_reg[12]\, I1 => IP2Bus_Error_reg_0, O => sig_txd_wr_en ); @@ -8742,22 +10456,17 @@ entity design_1_axi_fifo_mm_s_0_0_fifo is prog_full_axis : out STD_LOGIC; prog_empty_axis : out STD_LOGIC; s_aresetn : out STD_LOGIC; - \gen_wr_a.gen_word_narrow.mem_reg\ : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 8 downto 0 ); + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); sig_txd_wr_en : out STD_LOGIC; - \gwdc.wr_data_count_i_reg[9]\ : out STD_LOGIC; + \gwdc.wr_data_count_i_reg[12]\ : out STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ : out STD_LOGIC; \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ : out STD_LOGIC; IP2Bus_Error_reg : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aclk : in STD_LOGIC; - \gen_wr_a.gen_word_narrow.mem_reg_0\ : in STD_LOGIC; + \gen_wr_a.gen_word_narrow.mem_reg_5\ : in STD_LOGIC; axi_str_txd_tready : in STD_LOGIC; txd_wr_en : in STD_LOGIC; - \sig_register_array_reg[0][4]\ : in STD_LOGIC; - \sig_register_array_reg[0][4]_0\ : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_ip2bus_data_reg[22]\ : in STD_LOGIC; + \sig_ip2bus_data_reg[19]\ : in STD_LOGIC; IP2Bus_Error_reg_0 : in STD_LOGIC; sig_txd_prog_full_d1 : in STD_LOGIC; sig_txd_prog_empty_d1 : in STD_LOGIC; @@ -8766,57 +10475,98 @@ entity design_1_axi_fifo_mm_s_0_0_fifo is s_axi_aresetn : in STD_LOGIC; IP2Bus_Error_reg_1 : in STD_LOGIC; Axi_Str_RxD_AReset : in STD_LOGIC; - mm2s_prmry_reset_out_n : in STD_LOGIC; - \sig_txd_wr_data_reg[0]\ : in STD_LOGIC; - \sig_txd_wr_data_reg[0]_0\ : in STD_LOGIC; - \sig_txd_wr_data_reg[0]_1\ : in STD_LOGIC + mm2s_prmry_reset_out_n : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_axi_fifo_mm_s_0_0_fifo : entity is "fifo"; end design_1_axi_fifo_mm_s_0_0_fifo; architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_fifo is - signal data2 : STD_LOGIC_VECTOR ( 9 downto 1 ); - signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_42\ : STD_LOGIC; + signal data2 : STD_LOGIC_VECTOR ( 12 downto 1 ); + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_50\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_51\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_52\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_53\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_54\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_55\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_56\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_57\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_58\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_59\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_60\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_61\ : STD_LOGIC; + signal \gfifo_gen.COMP_AXIS_FG_FIFO_n_62\ : STD_LOGIC; signal \gfifo_gen.gmm2s.start_wr_i_1_n_0\ : STD_LOGIC; - signal minusOp : STD_LOGIC_VECTOR ( 9 downto 2 ); + signal minusOp : STD_LOGIC_VECTOR ( 12 downto 1 ); + signal \minusOp_carry__0_n_0\ : STD_LOGIC; + signal \minusOp_carry__0_n_1\ : STD_LOGIC; + signal \minusOp_carry__0_n_2\ : STD_LOGIC; + signal \minusOp_carry__0_n_3\ : STD_LOGIC; + signal \minusOp_carry__1_n_0\ : STD_LOGIC; + signal \minusOp_carry__1_n_1\ : STD_LOGIC; + signal \minusOp_carry__1_n_2\ : STD_LOGIC; + signal \minusOp_carry__1_n_3\ : STD_LOGIC; + signal minusOp_carry_n_0 : STD_LOGIC; + signal minusOp_carry_n_1 : STD_LOGIC; + signal minusOp_carry_n_2 : STD_LOGIC; + signal minusOp_carry_n_3 : STD_LOGIC; signal \^s_aresetn\ : STD_LOGIC; - signal sig_txd_occupancy : STD_LOGIC_VECTOR ( 1 to 1 ); + signal sig_txd_occupancy : STD_LOGIC_VECTOR ( 11 downto 1 ); signal sig_txd_reset0_out : STD_LOGIC; signal start_wr : STD_LOGIC; signal wr_data_int : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_minusOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_minusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of minusOp_carry : label is 35; + attribute ADDER_THRESHOLD of \minusOp_carry__0\ : label is 35; + attribute ADDER_THRESHOLD of \minusOp_carry__1\ : label is 35; + attribute ADDER_THRESHOLD of \minusOp_carry__2\ : label is 35; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \sig_ip2bus_data[23]_i_1\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[24]_i_1\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[25]_i_1\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[26]_i_1\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[27]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[28]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[29]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[30]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[19]_i_1\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[20]_i_1\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[21]_i_1\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[22]_i_1\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[23]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[24]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[25]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[26]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[27]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[28]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[29]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[30]_i_1\ : label is "soft_lutpair7"; begin s_aresetn <= \^s_aresetn\; \gfifo_gen.COMP_AXIS_FG_FIFO\: entity work.design_1_axi_fifo_mm_s_0_0_axis_fg port map ( Axi_Str_RxD_AReset => Axi_Str_RxD_AReset, - D(7) => minusOp(9), - D(6) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_42\, - D(5 downto 0) => minusOp(7 downto 2), - E(0) => E(0), + DI(3) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_51\, + DI(2) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_52\, + DI(1) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_53\, + DI(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_54\, IP2Bus_Error_reg => IP2Bus_Error_reg, IP2Bus_Error_reg_0 => IP2Bus_Error_reg_0, IP2Bus_Error_reg_1 => IP2Bus_Error_reg_1, Q(31 downto 0) => wr_data_int(31 downto 0), + S(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_50\, axi_str_txd_tdata(31 downto 0) => axi_str_txd_tdata(31 downto 0), axi_str_txd_tlast => axi_str_txd_tlast, axi_str_txd_tready => axi_str_txd_tready, axi_str_txd_tvalid => axi_str_txd_tvalid, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\, \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\, - \gen_wr_a.gen_word_narrow.mem_reg\ => \gen_wr_a.gen_word_narrow.mem_reg\, - \gen_wr_a.gen_word_narrow.mem_reg_0\ => \gen_wr_a.gen_word_narrow.mem_reg_0\, - \gen_wr_a.gen_word_narrow.mem_reg_1\(1 downto 0) => Q(1 downto 0), - \gwdc.wr_data_count_i_reg[9]\ => \gwdc.wr_data_count_i_reg[9]\, + \gen_wr_a.gen_word_narrow.mem_reg_3\(1 downto 0) => Q(1 downto 0), + \gen_wr_a.gen_word_narrow.mem_reg_5\ => \gen_wr_a.gen_word_narrow.mem_reg_5\, + \gwdc.wr_data_count_i_reg[0]\(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_62\, + \gwdc.wr_data_count_i_reg[12]\ => \gwdc.wr_data_count_i_reg[12]\, + \gwdc.wr_data_count_i_reg[3]\(2) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_59\, + \gwdc.wr_data_count_i_reg[3]\(1) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_60\, + \gwdc.wr_data_count_i_reg[3]\(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_61\, + \gwdc.wr_data_count_i_reg[7]\(3) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_55\, + \gwdc.wr_data_count_i_reg[7]\(2) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_56\, + \gwdc.wr_data_count_i_reg[7]\(1) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_57\, + \gwdc.wr_data_count_i_reg[7]\(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_58\, mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n, p_1_in(0) => p_1_in(0), prog_empty_axis => prog_empty_axis, @@ -8824,18 +10574,12 @@ begin s_aresetn => \^s_aresetn\, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, - s_axi_wdata(0) => s_axi_wdata(0), - \sig_register_array_reg[0][4]\ => \sig_register_array_reg[0][4]\, - \sig_register_array_reg[0][4]_0\ => \sig_register_array_reg[0][4]_0\, sig_txd_prog_empty_d1 => sig_txd_prog_empty_d1, sig_txd_prog_full_d1 => sig_txd_prog_full_d1, - \sig_txd_wr_data_reg[0]\ => \sig_txd_wr_data_reg[0]\, - \sig_txd_wr_data_reg[0]_0\ => \sig_txd_wr_data_reg[0]_0\, - \sig_txd_wr_data_reg[0]_1\ => \sig_txd_wr_data_reg[0]_1\, sig_txd_wr_en => sig_txd_wr_en, start_wr => start_wr, txd_wr_en => txd_wr_en, - wr_data_count_axis(0) => sig_txd_occupancy(1) + wr_data_count_axis(10 downto 0) => sig_txd_occupancy(11 downto 1) ); \gfifo_gen.gmm2s.start_wr_i_1\: unisim.vcomponents.LUT3 generic map( @@ -8843,7 +10587,7 @@ begin ) port map ( I0 => txd_wr_en, - I1 => \gen_wr_a.gen_word_narrow.mem_reg_0\, + I1 => \gen_wr_a.gen_word_narrow.mem_reg_5\, I2 => start_wr, O => \gfifo_gen.gmm2s.start_wr_i_1_n_0\ ); @@ -8858,7 +10602,7 @@ begin Q => start_wr, R => sig_txd_reset0_out ); -\gfifo_gen.gmm2s.vacancy_i[9]_i_1\: unisim.vcomponents.LUT1 +\gfifo_gen.gmm2s.vacancy_i[12]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) @@ -8866,6 +10610,39 @@ begin I0 => \^s_aresetn\, O => sig_txd_reset0_out ); +\gfifo_gen.gmm2s.vacancy_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => minusOp(10), + Q => data2(10), + R => sig_txd_reset0_out + ); +\gfifo_gen.gmm2s.vacancy_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => minusOp(11), + Q => data2(11), + R => sig_txd_reset0_out + ); +\gfifo_gen.gmm2s.vacancy_i_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => minusOp(12), + Q => data2(12), + R => sig_txd_reset0_out + ); \gfifo_gen.gmm2s.vacancy_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -8873,7 +10650,7 @@ begin port map ( C => s_axi_aclk, CE => '1', - D => sig_txd_occupancy(1), + D => minusOp(1), Q => data2(1), R => sig_txd_reset0_out ); @@ -8950,7 +10727,7 @@ begin port map ( C => s_axi_aclk, CE => '1', - D => \gfifo_gen.COMP_AXIS_FG_FIFO_n_42\, + D => minusOp(8), Q => data2(8), R => sig_txd_reset0_out ); @@ -9317,13 +11094,98 @@ begin Q => wr_data_int(9), R => sig_txd_reset0_out ); +minusOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => minusOp_carry_n_0, + CO(2) => minusOp_carry_n_1, + CO(1) => minusOp_carry_n_2, + CO(0) => minusOp_carry_n_3, + CYINIT => '0', + DI(3) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_59\, + DI(2) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_60\, + DI(1) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_61\, + DI(0) => '0', + O(3 downto 1) => minusOp(3 downto 1), + O(0) => NLW_minusOp_carry_O_UNCONNECTED(0), + S(3 downto 1) => sig_txd_occupancy(3 downto 1), + S(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_62\ + ); +\minusOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => minusOp_carry_n_0, + CO(3) => \minusOp_carry__0_n_0\, + CO(2) => \minusOp_carry__0_n_1\, + CO(1) => \minusOp_carry__0_n_2\, + CO(0) => \minusOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_55\, + DI(2) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_56\, + DI(1) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_57\, + DI(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_58\, + O(3 downto 0) => minusOp(7 downto 4), + S(3 downto 0) => sig_txd_occupancy(7 downto 4) + ); +\minusOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minusOp_carry__0_n_0\, + CO(3) => \minusOp_carry__1_n_0\, + CO(2) => \minusOp_carry__1_n_1\, + CO(1) => \minusOp_carry__1_n_2\, + CO(0) => \minusOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_51\, + DI(2) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_52\, + DI(1) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_53\, + DI(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_54\, + O(3 downto 0) => minusOp(11 downto 8), + S(3 downto 0) => sig_txd_occupancy(11 downto 8) + ); +\minusOp_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \minusOp_carry__1_n_0\, + CO(3 downto 0) => \NLW_minusOp_carry__2_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_minusOp_carry__2_O_UNCONNECTED\(3 downto 1), + O(0) => minusOp(12), + S(3 downto 1) => B"000", + S(0) => \gfifo_gen.COMP_AXIS_FG_FIFO_n_50\ + ); +\sig_ip2bus_data[19]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => data2(12), + I1 => \sig_ip2bus_data_reg[19]\, + O => D(11) + ); +\sig_ip2bus_data[20]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => data2(11), + I1 => \sig_ip2bus_data_reg[19]\, + O => D(10) + ); +\sig_ip2bus_data[21]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => data2(10), + I1 => \sig_ip2bus_data_reg[19]\, + O => D(9) + ); \sig_ip2bus_data[22]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => data2(9), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(8) ); \sig_ip2bus_data[23]_i_1\: unisim.vcomponents.LUT2 @@ -9332,7 +11194,7 @@ begin ) port map ( I0 => data2(8), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(7) ); \sig_ip2bus_data[24]_i_1\: unisim.vcomponents.LUT2 @@ -9341,7 +11203,7 @@ begin ) port map ( I0 => data2(7), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(6) ); \sig_ip2bus_data[25]_i_1\: unisim.vcomponents.LUT2 @@ -9350,7 +11212,7 @@ begin ) port map ( I0 => data2(6), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(5) ); \sig_ip2bus_data[26]_i_1\: unisim.vcomponents.LUT2 @@ -9359,7 +11221,7 @@ begin ) port map ( I0 => data2(5), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(4) ); \sig_ip2bus_data[27]_i_1\: unisim.vcomponents.LUT2 @@ -9368,7 +11230,7 @@ begin ) port map ( I0 => data2(4), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(3) ); \sig_ip2bus_data[28]_i_1\: unisim.vcomponents.LUT2 @@ -9377,7 +11239,7 @@ begin ) port map ( I0 => data2(3), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(2) ); \sig_ip2bus_data[29]_i_1\: unisim.vcomponents.LUT2 @@ -9386,7 +11248,7 @@ begin ) port map ( I0 => data2(2), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(1) ); \sig_ip2bus_data[30]_i_1\: unisim.vcomponents.LUT2 @@ -9395,7 +11257,7 @@ begin ) port map ( I0 => data2(1), - I1 => \sig_ip2bus_data_reg[22]\, + I1 => \sig_ip2bus_data_reg[19]\, O => D(0) ); end STRUCTURE; @@ -9415,43 +11277,39 @@ entity design_1_axi_fifo_mm_s_0_0_ipic2axi_s is p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 ); sig_tx_channel_reset_reg_0 : out STD_LOGIC; cs_ce_clr : out STD_LOGIC; - IPIC_STATE_reg_0 : out STD_LOGIC; IP2Bus_Error1_in : out STD_LOGIC; s2mm_prmry_reset_out_n : out STD_LOGIC; s_axi_wdata_7_sp_1 : out STD_LOGIC; - s_axi_wdata_0_sp_1 : out STD_LOGIC; interrupt : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 6 downto 0 ); - \sig_register_array_reg[0][4]_0\ : out STD_LOGIC; - \sig_register_array_reg[0][3]_0\ : out STD_LOGIC; - \sig_register_array_reg[0][6]_0\ : out STD_LOGIC; \sig_register_array_reg[0][10]_0\ : out STD_LOGIC; + \sig_register_array_reg[0][3]_0\ : out STD_LOGIC; \sig_register_array_reg[0][7]_0\ : out STD_LOGIC; - \sig_register_array_reg[0][9]_0\ : out STD_LOGIC; + \sig_register_array_reg[0][4]_0\ : out STD_LOGIC; \sig_register_array_reg[0][8]_0\ : out STD_LOGIC; - \sig_ip2bus_data_reg[0]_0\ : out STD_LOGIC_VECTOR ( 21 downto 0 ); + \sig_register_array_reg[0][6]_0\ : out STD_LOGIC; + \sig_register_array_reg[0][9]_0\ : out STD_LOGIC; + \sig_ip2bus_data_reg[0]_0\ : out STD_LOGIC_VECTOR ( 24 downto 0 ); s_axi_aclk : in STD_LOGIC; axi_str_txd_tready : in STD_LOGIC; - sig_txd_sb_wr_en : in STD_LOGIC; sig_str_rst_reg_1 : in STD_LOGIC; IP2Bus_WrAck_reg_1 : in STD_LOGIC; IP2Bus_RdAck_reg_1 : in STD_LOGIC; sig_Bus2IP_CS : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; + sig_txd_sb_wr_en_reg_0 : in STD_LOGIC; \sig_register_array_reg[0][3]_1\ : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \sig_txd_wr_data_reg[0]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \sig_ip2bus_data_reg[19]_0\ : in STD_LOGIC; \sig_ip2bus_data_reg[12]_0\ : in STD_LOGIC; - \sig_ip2bus_data_reg[22]_0\ : in STD_LOGIC; IP2Bus_Error_reg_0 : in STD_LOGIC; sig_tx_channel_reset_reg_1 : in STD_LOGIC; - \sig_txd_wr_data_reg[0]_1\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\ : in STD_LOGIC; \sig_register_array_reg[0][4]_1\ : in STD_LOGIC; + \sig_register_array_reg[0][4]_2\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : in STD_LOGIC; Bus_RNW_reg : in STD_LOGIC; - \sig_register_array_reg[0][6]_1\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \sig_register_array_reg[1][0]_0\ : in STD_LOGIC_VECTOR ( 12 downto 0 ) ); @@ -9549,12 +11407,10 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_ipic2axi_s is signal \eqOp_inferred__2/i__carry_n_1\ : STD_LOGIC; signal \eqOp_inferred__2/i__carry_n_2\ : STD_LOGIC; signal \eqOp_inferred__2/i__carry_n_3\ : STD_LOGIC; - signal \gtxd.COMP_TXD_FIFO_n_37\ : STD_LOGIC; - signal \gtxd.COMP_TXD_FIFO_n_48\ : STD_LOGIC; - signal \gtxd.COMP_TXD_FIFO_n_49\ : STD_LOGIC; signal \gtxd.COMP_TXD_FIFO_n_50\ : STD_LOGIC; signal \gtxd.COMP_TXD_FIFO_n_51\ : STD_LOGIC; signal \gtxd.COMP_TXD_FIFO_n_52\ : STD_LOGIC; + signal \gtxd.COMP_TXD_FIFO_n_53\ : STD_LOGIC; signal \gtxd.sig_txd_packet_size[0]_i_1_n_0\ : STD_LOGIC; signal \gtxd.sig_txd_packet_size[0]_i_3_n_0\ : STD_LOGIC; signal \gtxd.sig_txd_packet_size_reg\ : STD_LOGIC_VECTOR ( 30 downto 0 ); @@ -9644,7 +11500,6 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_ipic2axi_s is signal interrupt_INST_0_i_1_n_0 : STD_LOGIC; signal interrupt_INST_0_i_2_n_0 : STD_LOGIC; signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal s_axi_wdata_0_sn_1 : STD_LOGIC; signal s_axi_wdata_7_sn_1 : STD_LOGIC; signal \^sig_bus2ip_reset\ : STD_LOGIC; signal sig_ip2bus_data : STD_LOGIC_VECTOR ( 0 to 30 ); @@ -9652,6 +11507,7 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_ipic2axi_s is signal \sig_register_array[0][3]_i_1_n_0\ : STD_LOGIC; signal \sig_register_array[0][4]_i_1_n_0\ : STD_LOGIC; signal \sig_register_array[0][6]_i_1_n_0\ : STD_LOGIC; + signal \sig_register_array[0][6]_i_2_n_0\ : STD_LOGIC; signal \sig_register_array[0][7]_i_1_n_0\ : STD_LOGIC; signal \sig_register_array[0][8]_i_1_n_0\ : STD_LOGIC; signal \sig_register_array[0][9]_i_1_n_0\ : STD_LOGIC; @@ -9676,7 +11532,10 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_ipic2axi_s is signal sig_txd_prog_empty_d1 : STD_LOGIC; signal sig_txd_prog_full : STD_LOGIC; signal sig_txd_prog_full_d1 : STD_LOGIC; + signal sig_txd_sb_wr_en : STD_LOGIC; signal sig_txd_sb_wr_en_reg_n_0 : STD_LOGIC; + signal \sig_txd_wr_data[31]_i_1_n_0\ : STD_LOGIC; + signal \sig_txd_wr_data[31]_i_2_n_0\ : STD_LOGIC; signal sig_txd_wr_en : STD_LOGIC; signal txd_wr_data : STD_LOGIC_VECTOR ( 31 downto 2 ); signal txd_wr_data_0 : STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -9703,19 +11562,20 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_ipic2axi_s is attribute ADDER_THRESHOLD of \R_carry__5\ : label is 35; attribute ADDER_THRESHOLD of \R_carry__6\ : label is 35; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \sig_ip2bus_data[0]_i_1\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[11]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[12]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[1]_i_1\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[2]_i_1\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \sig_ip2bus_data[5]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[0]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[11]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[12]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[1]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[2]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \sig_ip2bus_data[5]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \sig_register_array[0][6]_i_2\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of sig_txd_sb_wr_en_i_1 : label is "soft_lutpair13"; begin IP2Bus_Error1_in <= \^ip2bus_error1_in\; IP2Bus_RdAck_reg_0 <= \^ip2bus_rdack_reg_0\; IP2Bus_WrAck_reg_0 <= \^ip2bus_wrack_reg_0\; Q(6 downto 0) <= \^q\(6 downto 0); p_1_in(0) <= \^p_1_in\(0); - s_axi_wdata_0_sp_1 <= s_axi_wdata_0_sn_1; s_axi_wdata_7_sp_1 <= s_axi_wdata_7_sn_1; sig_Bus2IP_Reset <= \^sig_bus2ip_reset\; \sig_register_array_reg[0][10]_0\ <= \^sig_register_array_reg[0][10]_0\; @@ -9734,7 +11594,7 @@ IP2Bus_Error_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \gtxd.COMP_TXD_FIFO_n_51\, + D => \gtxd.COMP_TXD_FIFO_n_53\, Q => \^p_1_in\(0), R => '0' ); @@ -10256,6 +12116,9 @@ R_carry_i_4: unisim.vcomponents.LUT1 \gtxd.COMP_TXD_FIFO\: entity work.design_1_axi_fifo_mm_s_0_0_fifo port map ( Axi_Str_RxD_AReset => Axi_Str_RxD_AReset, + D(11) => sig_ip2bus_data(19), + D(10) => sig_ip2bus_data(20), + D(9) => sig_ip2bus_data(21), D(8) => sig_ip2bus_data(22), D(7) => sig_ip2bus_data(23), D(6) => sig_ip2bus_data(24), @@ -10265,8 +12128,7 @@ R_carry_i_4: unisim.vcomponents.LUT1 D(2) => sig_ip2bus_data(28), D(1) => sig_ip2bus_data(29), D(0) => sig_ip2bus_data(30), - E(0) => \gtxd.COMP_TXD_FIFO_n_52\, - IP2Bus_Error_reg => \gtxd.COMP_TXD_FIFO_n_51\, + IP2Bus_Error_reg => \gtxd.COMP_TXD_FIFO_n_53\, IP2Bus_Error_reg_0 => IP2Bus_Error_reg_0, IP2Bus_Error_reg_1 => \^ip2bus_error1_in\, Q(31 downto 2) => txd_wr_data(31 downto 2), @@ -10275,11 +12137,10 @@ R_carry_i_4: unisim.vcomponents.LUT1 axi_str_txd_tlast => axi_str_txd_tlast, axi_str_txd_tready => axi_str_txd_tready, axi_str_txd_tvalid => axi_str_txd_tvalid, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ => \gtxd.COMP_TXD_FIFO_n_50\, - \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ => \gtxd.COMP_TXD_FIFO_n_49\, - \gen_wr_a.gen_word_narrow.mem_reg\ => \gtxd.COMP_TXD_FIFO_n_37\, - \gen_wr_a.gen_word_narrow.mem_reg_0\ => sig_txd_sb_wr_en_reg_n_0, - \gwdc.wr_data_count_i_reg[9]\ => \gtxd.COMP_TXD_FIFO_n_48\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\ => \gtxd.COMP_TXD_FIFO_n_52\, + \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\ => \gtxd.COMP_TXD_FIFO_n_51\, + \gen_wr_a.gen_word_narrow.mem_reg_5\ => sig_txd_sb_wr_en_reg_n_0, + \gwdc.wr_data_count_i_reg[12]\ => \gtxd.COMP_TXD_FIFO_n_50\, mm2s_prmry_reset_out_n => \^sig_tx_channel_reset_reg_0\, p_1_in(0) => \^p_1_in\(0), prog_empty_axis => sig_txd_prog_empty, @@ -10287,15 +12148,9 @@ R_carry_i_4: unisim.vcomponents.LUT1 s_aresetn => \^sig_str_rst_reg_0\, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, - s_axi_wdata(0) => s_axi_wdata(27), - \sig_ip2bus_data_reg[22]\ => \sig_ip2bus_data_reg[22]_0\, - \sig_register_array_reg[0][4]\ => sig_str_rst_reg_1, - \sig_register_array_reg[0][4]_0\ => \sig_register_array_reg[0][3]_1\, + \sig_ip2bus_data_reg[19]\ => \sig_ip2bus_data_reg[19]_0\, sig_txd_prog_empty_d1 => sig_txd_prog_empty_d1, sig_txd_prog_full_d1 => sig_txd_prog_full_d1, - \sig_txd_wr_data_reg[0]\ => \sig_txd_wr_data_reg[0]_1\, - \sig_txd_wr_data_reg[0]_0\ => s_axi_wdata_0_sn_1, - \sig_txd_wr_data_reg[0]_1\ => \sig_txd_wr_data_reg[0]_0\, sig_txd_wr_en => sig_txd_wr_en, txd_wr_en => txd_wr_en ); @@ -10712,12 +12567,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => \gtxd.sig_txd_packet_size_reg\(22), - I1 => s_axi_wdata(24), - I2 => s_axi_wdata(25), - I3 => \gtxd.sig_txd_packet_size_reg\(23), - I4 => s_axi_wdata(23), - I5 => \gtxd.sig_txd_packet_size_reg\(21), + I0 => \gtxd.sig_txd_packet_size_reg\(23), + I1 => s_axi_wdata(25), + I2 => s_axi_wdata(23), + I3 => \gtxd.sig_txd_packet_size_reg\(21), + I4 => s_axi_wdata(24), + I5 => \gtxd.sig_txd_packet_size_reg\(22), O => \i__carry__0_i_1_n_0\ ); \i__carry__0_i_1__0\: unisim.vcomponents.LUT6 @@ -10725,12 +12580,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => s_axi_wdata(23), - I1 => R(21), - I2 => s_axi_wdata(24), - I3 => R(22), - I4 => R(23), - I5 => s_axi_wdata(25), + I0 => s_axi_wdata(25), + I1 => R(23), + I2 => s_axi_wdata(23), + I3 => R(21), + I4 => R(22), + I5 => s_axi_wdata(24), O => \i__carry__0_i_1__0_n_0\ ); \i__carry__0_i_2\: unisim.vcomponents.LUT6 @@ -10738,12 +12593,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => \gtxd.sig_txd_packet_size_reg\(19), - I1 => s_axi_wdata(21), - I2 => s_axi_wdata(22), - I3 => \gtxd.sig_txd_packet_size_reg\(20), - I4 => s_axi_wdata(20), - I5 => \gtxd.sig_txd_packet_size_reg\(18), + I0 => \gtxd.sig_txd_packet_size_reg\(20), + I1 => s_axi_wdata(22), + I2 => s_axi_wdata(20), + I3 => \gtxd.sig_txd_packet_size_reg\(18), + I4 => s_axi_wdata(21), + I5 => \gtxd.sig_txd_packet_size_reg\(19), O => \i__carry__0_i_2_n_0\ ); \i__carry__0_i_2__0\: unisim.vcomponents.LUT6 @@ -10751,12 +12606,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => s_axi_wdata(20), - I1 => R(18), - I2 => s_axi_wdata(21), - I3 => R(19), - I4 => R(20), - I5 => s_axi_wdata(22), + I0 => s_axi_wdata(22), + I1 => R(20), + I2 => s_axi_wdata(20), + I3 => R(18), + I4 => R(19), + I5 => s_axi_wdata(21), O => \i__carry__0_i_2__0_n_0\ ); \i__carry__0_i_3\: unisim.vcomponents.LUT6 @@ -10777,12 +12632,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => R(16), - I1 => s_axi_wdata(18), - I2 => s_axi_wdata(19), - I3 => R(17), - I4 => s_axi_wdata(17), - I5 => R(15), + I0 => s_axi_wdata(18), + I1 => R(16), + I2 => s_axi_wdata(17), + I3 => R(15), + I4 => R(17), + I5 => s_axi_wdata(19), O => \i__carry__0_i_3__0_n_0\ ); \i__carry__0_i_4\: unisim.vcomponents.LUT6 @@ -10790,10 +12645,10 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => \gtxd.sig_txd_packet_size_reg\(14), - I1 => s_axi_wdata(16), - I2 => s_axi_wdata(15), - I3 => \gtxd.sig_txd_packet_size_reg\(13), + I0 => \gtxd.sig_txd_packet_size_reg\(13), + I1 => s_axi_wdata(15), + I2 => s_axi_wdata(16), + I3 => \gtxd.sig_txd_packet_size_reg\(14), I4 => s_axi_wdata(14), I5 => \gtxd.sig_txd_packet_size_reg\(12), O => \i__carry__0_i_4_n_0\ @@ -10803,12 +12658,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => s_axi_wdata(16), - I1 => R(14), - I2 => s_axi_wdata(14), - I3 => R(12), - I4 => R(13), - I5 => s_axi_wdata(15), + I0 => s_axi_wdata(14), + I1 => R(12), + I2 => s_axi_wdata(15), + I3 => R(13), + I4 => R(14), + I5 => s_axi_wdata(16), O => \i__carry__0_i_4__0_n_0\ ); \i__carry__1_i_1\: unisim.vcomponents.LUT1 @@ -10832,10 +12687,10 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => \gtxd.sig_txd_packet_size_reg\(29), - I1 => s_axi_wdata(31), - I2 => s_axi_wdata(30), - I3 => \gtxd.sig_txd_packet_size_reg\(28), + I0 => \gtxd.sig_txd_packet_size_reg\(28), + I1 => s_axi_wdata(30), + I2 => s_axi_wdata(31), + I3 => \gtxd.sig_txd_packet_size_reg\(29), I4 => s_axi_wdata(29), I5 => \gtxd.sig_txd_packet_size_reg\(27), O => \i__carry__1_i_2_n_0\ @@ -10845,12 +12700,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => s_axi_wdata(29), - I1 => R(27), - I2 => s_axi_wdata(31), - I3 => R(29), - I4 => R(28), - I5 => s_axi_wdata(30), + I0 => R(28), + I1 => s_axi_wdata(30), + I2 => s_axi_wdata(29), + I3 => R(27), + I4 => s_axi_wdata(31), + I5 => R(29), O => \i__carry__1_i_2__0_n_0\ ); \i__carry__1_i_3\: unisim.vcomponents.LUT6 @@ -10884,10 +12739,10 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => \gtxd.sig_txd_packet_size_reg\(10), - I1 => s_axi_wdata(12), - I2 => s_axi_wdata(13), - I3 => \gtxd.sig_txd_packet_size_reg\(11), + I0 => \gtxd.sig_txd_packet_size_reg\(11), + I1 => s_axi_wdata(13), + I2 => s_axi_wdata(12), + I3 => \gtxd.sig_txd_packet_size_reg\(10), I4 => s_axi_wdata(11), I5 => \gtxd.sig_txd_packet_size_reg\(9), O => \i__carry_i_1_n_0\ @@ -10897,12 +12752,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => R(10), - I1 => s_axi_wdata(12), - I2 => s_axi_wdata(13), - I3 => R(11), - I4 => s_axi_wdata(11), - I5 => R(9), + I0 => s_axi_wdata(13), + I1 => R(11), + I2 => s_axi_wdata(11), + I3 => R(9), + I4 => R(10), + I5 => s_axi_wdata(12), O => \i__carry_i_1__0_n_0\ ); \i__carry_i_2\: unisim.vcomponents.LUT6 @@ -10910,12 +12765,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => \gtxd.sig_txd_packet_size_reg\(8), - I1 => s_axi_wdata(10), + I0 => \gtxd.sig_txd_packet_size_reg\(7), + I1 => s_axi_wdata(9), I2 => s_axi_wdata(8), I3 => \gtxd.sig_txd_packet_size_reg\(6), - I4 => s_axi_wdata(9), - I5 => \gtxd.sig_txd_packet_size_reg\(7), + I4 => s_axi_wdata(10), + I5 => \gtxd.sig_txd_packet_size_reg\(8), O => \i__carry_i_2_n_0\ ); \i__carry_i_2__0\: unisim.vcomponents.LUT6 @@ -10923,12 +12778,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => R(8), - I1 => s_axi_wdata(10), + I0 => s_axi_wdata(9), + I1 => R(7), I2 => s_axi_wdata(8), I3 => R(6), - I4 => s_axi_wdata(9), - I5 => R(7), + I4 => R(8), + I5 => s_axi_wdata(10), O => \i__carry_i_2__0_n_0\ ); \i__carry_i_3\: unisim.vcomponents.LUT6 @@ -10936,10 +12791,10 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => \gtxd.sig_txd_packet_size_reg\(4), - I1 => s_axi_wdata(6), - I2 => s_axi_wdata(7), - I3 => \gtxd.sig_txd_packet_size_reg\(5), + I0 => \gtxd.sig_txd_packet_size_reg\(5), + I1 => s_axi_wdata(7), + I2 => s_axi_wdata(6), + I3 => \gtxd.sig_txd_packet_size_reg\(4), I4 => s_axi_wdata(5), I5 => \gtxd.sig_txd_packet_size_reg\(3), O => \i__carry_i_3_n_0\ @@ -10949,12 +12804,12 @@ R_carry_i_4: unisim.vcomponents.LUT1 INIT => X"9009000000009009" ) port map ( - I0 => s_axi_wdata(6), - I1 => R(4), + I0 => s_axi_wdata(7), + I1 => R(5), I2 => s_axi_wdata(5), I3 => R(3), - I4 => R(5), - I5 => s_axi_wdata(7), + I4 => R(4), + I5 => s_axi_wdata(6), O => \i__carry_i_3__0_n_0\ ); \i__carry_i_4\: unisim.vcomponents.LUT6 @@ -10990,8 +12845,8 @@ interrupt_INST_0: unisim.vcomponents.LUT6 port map ( I0 => interrupt_INST_0_i_1_n_0, I1 => interrupt_INST_0_i_2_n_0, - I2 => \^q\(5), - I3 => \^sig_register_array_reg[0][4]_0\, + I2 => \^q\(0), + I3 => \^sig_register_array_reg[0][10]_0\, I4 => \^q\(6), I5 => \^sig_register_array_reg[0][3]_0\, O => interrupt @@ -11001,12 +12856,12 @@ interrupt_INST_0_i_1: unisim.vcomponents.LUT6 INIT => X"FFFFF888F888F888" ) port map ( - I0 => \^q\(3), - I1 => \^sig_register_array_reg[0][7]_0\, - I2 => \^sig_register_array_reg[0][9]_0\, - I3 => \^q\(1), - I4 => \^sig_register_array_reg[0][8]_0\, - I5 => \^q\(2), + I0 => \^q\(2), + I1 => \^sig_register_array_reg[0][8]_0\, + I2 => \^sig_register_array_reg[0][6]_0\, + I3 => \^q\(4), + I4 => \^sig_register_array_reg[0][9]_0\, + I5 => \^q\(1), O => interrupt_INST_0_i_1_n_0 ); interrupt_INST_0_i_2: unisim.vcomponents.LUT4 @@ -11014,10 +12869,10 @@ interrupt_INST_0_i_2: unisim.vcomponents.LUT4 INIT => X"F888" ) port map ( - I0 => \^q\(4), - I1 => \^sig_register_array_reg[0][6]_0\, - I2 => \^q\(0), - I3 => \^sig_register_array_reg[0][10]_0\, + I0 => \^q\(3), + I1 => \^sig_register_array_reg[0][7]_0\, + I2 => \^q\(5), + I3 => \^sig_register_array_reg[0][4]_0\, O => interrupt_INST_0_i_2_n_0 ); s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 @@ -11090,7 +12945,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => sig_ip2bus_data(0), - Q => \sig_ip2bus_data_reg[0]_0\(21), + Q => \sig_ip2bus_data_reg[0]_0\(24), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[10]\: unisim.vcomponents.FDRE @@ -11101,7 +12956,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => D(0), - Q => \sig_ip2bus_data_reg[0]_0\(11), + Q => \sig_ip2bus_data_reg[0]_0\(14), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[11]\: unisim.vcomponents.FDRE @@ -11112,7 +12967,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => sig_ip2bus_data(11), - Q => \sig_ip2bus_data_reg[0]_0\(10), + Q => \sig_ip2bus_data_reg[0]_0\(13), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[12]\: unisim.vcomponents.FDRE @@ -11123,7 +12978,18 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => sig_ip2bus_data(12), - Q => \sig_ip2bus_data_reg[0]_0\(9), + Q => \sig_ip2bus_data_reg[0]_0\(12), + R => IP2Bus_WrAck_i_1_n_0 + ); +\sig_ip2bus_data_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => sig_ip2bus_data(19), + Q => \sig_ip2bus_data_reg[0]_0\(11), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[1]\: unisim.vcomponents.FDRE @@ -11134,7 +13000,29 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => sig_ip2bus_data(1), - Q => \sig_ip2bus_data_reg[0]_0\(20), + Q => \sig_ip2bus_data_reg[0]_0\(23), + R => IP2Bus_WrAck_i_1_n_0 + ); +\sig_ip2bus_data_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => sig_ip2bus_data(20), + Q => \sig_ip2bus_data_reg[0]_0\(10), + R => IP2Bus_WrAck_i_1_n_0 + ); +\sig_ip2bus_data_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => sig_ip2bus_data(21), + Q => \sig_ip2bus_data_reg[0]_0\(9), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[22]\: unisim.vcomponents.FDRE @@ -11233,7 +13121,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => sig_ip2bus_data(2), - Q => \sig_ip2bus_data_reg[0]_0\(19), + Q => \sig_ip2bus_data_reg[0]_0\(22), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[30]\: unisim.vcomponents.FDRE @@ -11255,7 +13143,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => D(6), - Q => \sig_ip2bus_data_reg[0]_0\(18), + Q => \sig_ip2bus_data_reg[0]_0\(21), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[4]\: unisim.vcomponents.FDRE @@ -11266,7 +13154,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => D(5), - Q => \sig_ip2bus_data_reg[0]_0\(17), + Q => \sig_ip2bus_data_reg[0]_0\(20), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[5]\: unisim.vcomponents.FDRE @@ -11277,7 +13165,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => sig_ip2bus_data(5), - Q => \sig_ip2bus_data_reg[0]_0\(16), + Q => \sig_ip2bus_data_reg[0]_0\(19), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[6]\: unisim.vcomponents.FDRE @@ -11288,7 +13176,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => D(4), - Q => \sig_ip2bus_data_reg[0]_0\(15), + Q => \sig_ip2bus_data_reg[0]_0\(18), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[7]\: unisim.vcomponents.FDRE @@ -11299,7 +13187,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => D(3), - Q => \sig_ip2bus_data_reg[0]_0\(14), + Q => \sig_ip2bus_data_reg[0]_0\(17), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[8]\: unisim.vcomponents.FDRE @@ -11310,7 +13198,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => D(2), - Q => \sig_ip2bus_data_reg[0]_0\(13), + Q => \sig_ip2bus_data_reg[0]_0\(16), R => IP2Bus_WrAck_i_1_n_0 ); \sig_ip2bus_data_reg[9]\: unisim.vcomponents.FDRE @@ -11321,43 +13209,35 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 C => s_axi_aclk, CE => '1', D => D(1), - Q => \sig_ip2bus_data_reg[0]_0\(12), + Q => \sig_ip2bus_data_reg[0]_0\(15), R => IP2Bus_WrAck_i_1_n_0 ); \sig_register_array[0][10]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0F004F470C004C44" + INIT => X"3705330337050000" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\, - I1 => \gtxd.COMP_TXD_FIFO_n_50\, - I2 => sig_str_rst_reg_1, + I1 => sig_str_rst_reg_1, + I2 => s_axi_wdata(21), I3 => \sig_register_array_reg[0][3]_1\, - I4 => s_axi_wdata(21), + I4 => \gtxd.COMP_TXD_FIFO_n_52\, I5 => \^sig_register_array_reg[0][10]_0\, O => \sig_register_array[0][10]_i_1_n_0\ ); -\sig_register_array[0][3]_i_1\: unisim.vcomponents.LUT5 +\sig_register_array[0][3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0D0D000D" + INIT => X"3705330337050000" ) port map ( - I0 => s_axi_wdata(28), - I1 => \sig_register_array_reg[0][3]_1\, - I2 => sig_str_rst_reg_1, - I3 => \gtxd.COMP_TXD_FIFO_n_48\, - I4 => \^sig_register_array_reg[0][3]_0\, + I0 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\, + I1 => sig_str_rst_reg_1, + I2 => s_axi_wdata(28), + I3 => \sig_register_array_reg[0][3]_1\, + I4 => \gtxd.COMP_TXD_FIFO_n_50\, + I5 => \^sig_register_array_reg[0][3]_0\, O => \sig_register_array[0][3]_i_1_n_0\ ); -\sig_register_array[0][3]_i_4\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => \^ip2bus_error1_in\, - I1 => \sig_txd_wr_data_reg[0]_0\, - O => IPIC_STATE_reg_0 - ); \sig_register_array[0][4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"02AAFFFF02AA0000" @@ -11367,24 +13247,37 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 I1 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\, I2 => s_axi_wdata(27), I3 => \sig_register_array_reg[0][4]_1\, - I4 => \gtxd.COMP_TXD_FIFO_n_37\, + I4 => \sig_register_array_reg[0][4]_2\, I5 => \^sig_register_array_reg[0][4]_0\, O => \sig_register_array[0][4]_i_1_n_0\ ); -\sig_register_array[0][6]_i_1\: unisim.vcomponents.LUT4 +\sig_register_array[0][6]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"2F20" + INIT => X"222F2220" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => Bus_RNW_reg, - I2 => \sig_register_array_reg[0][6]_1\, - I3 => \^sig_register_array_reg[0][6]_0\, + I2 => sig_str_rst_reg_1, + I3 => \sig_register_array[0][6]_i_2_n_0\, + I4 => \^sig_register_array_reg[0][6]_0\, O => \sig_register_array[0][6]_i_1_n_0\ ); +\sig_register_array[0][6]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10FF1010" + ) + port map ( + I0 => \^ip2bus_error1_in\, + I1 => \sig_txd_wr_data[31]_i_2_n_0\, + I2 => sig_txd_sb_wr_en_reg_0, + I3 => \sig_register_array_reg[0][3]_1\, + I4 => s_axi_wdata(25), + O => \sig_register_array[0][6]_i_2_n_0\ + ); \sig_register_array[0][7]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"F0FFD0DD" + INIT => X"FCFFDCDD" ) port map ( I0 => \^sig_str_rst_reg_0\, @@ -11409,14 +13302,14 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 ); \sig_register_array[0][9]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0F004F470C004C44" + INIT => X"3705330337050000" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\, - I1 => \gtxd.COMP_TXD_FIFO_n_49\, - I2 => sig_str_rst_reg_1, + I1 => sig_str_rst_reg_1, + I2 => s_axi_wdata(22), I3 => \sig_register_array_reg[0][3]_1\, - I4 => s_axi_wdata(22), + I4 => \gtxd.COMP_TXD_FIFO_n_51\, I5 => \^sig_register_array_reg[0][9]_0\, O => \sig_register_array[0][9]_i_1_n_0\ ); @@ -11582,7 +13475,7 @@ s2mm_prmry_reset_out_n_INST_0: unisim.vcomponents.LUT1 ); sig_str_rst_i_2: unisim.vcomponents.LUT5 generic map( - INIT => X"00000008" + INIT => X"FFFFFFF7" ) port map ( I0 => s_axi_wdata(7), @@ -11635,6 +13528,15 @@ sig_tx_channel_reset_reg: unisim.vcomponents.FDRE Q => \^sig_tx_channel_reset_reg_0\, R => \^sig_bus2ip_reset\ ); +sig_txd_sb_wr_en_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \sig_txd_wr_data[31]_i_2_n_0\, + I1 => sig_txd_sb_wr_en_reg_0, + O => sig_txd_sb_wr_en + ); sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -11646,7 +13548,19 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE Q => sig_txd_sb_wr_en_reg_n_0, R => IP2Bus_WrAck_i_1_n_0 ); -\sig_txd_wr_data[31]_i_3\: unisim.vcomponents.LUT4 +\sig_txd_wr_data[31]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000888F" + ) + port map ( + I0 => \sig_txd_wr_data[31]_i_2_n_0\, + I1 => sig_txd_sb_wr_en_reg_0, + I2 => \gtxd.COMP_TXD_FIFO_n_50\, + I3 => IP2Bus_Error_reg_0, + I4 => \^ip2bus_error1_in\, + O => \sig_txd_wr_data[31]_i_1_n_0\ + ); +\sig_txd_wr_data[31]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) @@ -11655,7 +13569,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE I1 => s_axi_wdata(0), I2 => s_axi_wdata(1), I3 => \eqOp_inferred__2/i__carry__1_n_1\, - O => s_axi_wdata_0_sn_1 + O => \sig_txd_wr_data[31]_i_2_n_0\ ); \sig_txd_wr_data_reg[0]\: unisim.vcomponents.FDRE generic map( @@ -11663,7 +13577,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(0), Q => txd_wr_data_0(0), R => \^sig_bus2ip_reset\ @@ -11674,7 +13588,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(10), Q => txd_wr_data(10), R => \^sig_bus2ip_reset\ @@ -11685,7 +13599,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(11), Q => txd_wr_data(11), R => \^sig_bus2ip_reset\ @@ -11696,7 +13610,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(12), Q => txd_wr_data(12), R => \^sig_bus2ip_reset\ @@ -11707,7 +13621,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(13), Q => txd_wr_data(13), R => \^sig_bus2ip_reset\ @@ -11718,7 +13632,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(14), Q => txd_wr_data(14), R => \^sig_bus2ip_reset\ @@ -11729,7 +13643,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(15), Q => txd_wr_data(15), R => \^sig_bus2ip_reset\ @@ -11740,7 +13654,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(16), Q => txd_wr_data(16), R => \^sig_bus2ip_reset\ @@ -11751,7 +13665,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(17), Q => txd_wr_data(17), R => \^sig_bus2ip_reset\ @@ -11762,7 +13676,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(18), Q => txd_wr_data(18), R => \^sig_bus2ip_reset\ @@ -11773,7 +13687,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(19), Q => txd_wr_data(19), R => \^sig_bus2ip_reset\ @@ -11784,7 +13698,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(1), Q => txd_wr_data_0(1), R => \^sig_bus2ip_reset\ @@ -11795,7 +13709,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(20), Q => txd_wr_data(20), R => \^sig_bus2ip_reset\ @@ -11806,7 +13720,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(21), Q => txd_wr_data(21), R => \^sig_bus2ip_reset\ @@ -11817,7 +13731,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(22), Q => txd_wr_data(22), R => \^sig_bus2ip_reset\ @@ -11828,7 +13742,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(23), Q => txd_wr_data(23), R => \^sig_bus2ip_reset\ @@ -11839,7 +13753,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(24), Q => txd_wr_data(24), R => \^sig_bus2ip_reset\ @@ -11850,7 +13764,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(25), Q => txd_wr_data(25), R => \^sig_bus2ip_reset\ @@ -11861,7 +13775,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(26), Q => txd_wr_data(26), R => \^sig_bus2ip_reset\ @@ -11872,7 +13786,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(27), Q => txd_wr_data(27), R => \^sig_bus2ip_reset\ @@ -11883,7 +13797,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(28), Q => txd_wr_data(28), R => \^sig_bus2ip_reset\ @@ -11894,7 +13808,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(29), Q => txd_wr_data(29), R => \^sig_bus2ip_reset\ @@ -11905,7 +13819,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(2), Q => txd_wr_data(2), R => \^sig_bus2ip_reset\ @@ -11916,7 +13830,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(30), Q => txd_wr_data(30), R => \^sig_bus2ip_reset\ @@ -11927,7 +13841,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(31), Q => txd_wr_data(31), R => \^sig_bus2ip_reset\ @@ -11938,7 +13852,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(3), Q => txd_wr_data(3), R => \^sig_bus2ip_reset\ @@ -11949,7 +13863,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(4), Q => txd_wr_data(4), R => \^sig_bus2ip_reset\ @@ -11960,7 +13874,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(5), Q => txd_wr_data(5), R => \^sig_bus2ip_reset\ @@ -11971,7 +13885,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(6), Q => txd_wr_data(6), R => \^sig_bus2ip_reset\ @@ -11982,7 +13896,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(7), Q => txd_wr_data(7), R => \^sig_bus2ip_reset\ @@ -11993,7 +13907,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(8), Q => txd_wr_data(8), R => \^sig_bus2ip_reset\ @@ -12004,7 +13918,7 @@ sig_txd_sb_wr_en_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => \gtxd.COMP_TXD_FIFO_n_52\, + CE => \sig_txd_wr_data[31]_i_1_n_0\, D => s_axi_wdata(9), Q => txd_wr_data(9), R => \^sig_bus2ip_reset\ @@ -12160,11 +14074,11 @@ entity design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s is attribute C_TX_CASCADE_HEIGHT : integer; attribute C_TX_CASCADE_HEIGHT of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s : entity is 0; attribute C_TX_FIFO_DEPTH : integer; - attribute C_TX_FIFO_DEPTH of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s : entity is 512; + attribute C_TX_FIFO_DEPTH of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s : entity is 4096; attribute C_TX_FIFO_PE_THRESHOLD : integer; attribute C_TX_FIFO_PE_THRESHOLD of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s : entity is 5; attribute C_TX_FIFO_PF_THRESHOLD : integer; - attribute C_TX_FIFO_PF_THRESHOLD of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s : entity is 507; + attribute C_TX_FIFO_PF_THRESHOLD of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s : entity is 4091; attribute C_USE_RX_CUT_THROUGH : integer; attribute C_USE_RX_CUT_THROUGH of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s : entity is 0; attribute C_USE_RX_DATA : integer; @@ -12183,9 +14097,9 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s is signal \\ : STD_LOGIC; signal \\ : STD_LOGIC; signal COMP_IPIC2AXI_S_n_39 : STD_LOGIC; - signal COMP_IPIC2AXI_S_n_41 : STD_LOGIC; - signal COMP_IPIC2AXI_S_n_44 : STD_LOGIC; + signal COMP_IPIC2AXI_S_n_43 : STD_LOGIC; signal COMP_IPIC2AXI_S_n_45 : STD_LOGIC; + signal COMP_IPIC2AXI_S_n_46 : STD_LOGIC; signal COMP_IPIC2AXI_S_n_47 : STD_LOGIC; signal COMP_IPIC2AXI_S_n_48 : STD_LOGIC; signal COMP_IPIC2AXI_S_n_49 : STD_LOGIC; @@ -12198,19 +14112,16 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s is signal COMP_IPIC2AXI_S_n_56 : STD_LOGIC; signal COMP_IPIC2AXI_S_n_57 : STD_LOGIC; signal COMP_IPIC2AXI_S_n_58 : STD_LOGIC; - signal COMP_IPIC2AXI_S_n_59 : STD_LOGIC; - signal COMP_IPIC2AXI_S_n_60 : STD_LOGIC; signal COMP_IPIF_n_10 : STD_LOGIC; signal COMP_IPIF_n_11 : STD_LOGIC; signal COMP_IPIF_n_12 : STD_LOGIC; signal COMP_IPIF_n_13 : STD_LOGIC; signal COMP_IPIF_n_14 : STD_LOGIC; - signal COMP_IPIF_n_16 : STD_LOGIC; + signal COMP_IPIF_n_15 : STD_LOGIC; + signal COMP_IPIF_n_23 : STD_LOGIC; signal COMP_IPIF_n_24 : STD_LOGIC; signal COMP_IPIF_n_25 : STD_LOGIC; - signal COMP_IPIF_n_26 : STD_LOGIC; - signal COMP_IPIF_n_27 : STD_LOGIC; - signal COMP_IPIF_n_41 : STD_LOGIC; + signal COMP_IPIF_n_39 : STD_LOGIC; signal COMP_IPIF_n_8 : STD_LOGIC; signal COMP_IPIF_n_9 : STD_LOGIC; signal IP2Bus_Error1_in : STD_LOGIC; @@ -12218,6 +14129,8 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s is signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr\ : STD_LOGIC; + signal \^axi_str_txd_tlast\ : STD_LOGIC; + signal \^axi_str_txd_tvalid\ : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 1 to 1 ); signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; @@ -12229,7 +14142,6 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0_axi_fifo_mm_s is signal sig_ip2bus_data : STD_LOGIC_VECTOR ( 0 to 30 ); signal sig_ip2bus_data_1 : STD_LOGIC_VECTOR ( 3 to 10 ); signal \sig_register_array[1]_0\ : STD_LOGIC_VECTOR ( 0 to 12 ); - signal sig_txd_sb_wr_en : STD_LOGIC; begin axi_str_rxd_tready <= \\; axi_str_txc_tdata(31) <= \\; @@ -12298,6 +14210,7 @@ begin axi_str_txd_tkeep(2) <= \\; axi_str_txd_tkeep(1) <= \\; axi_str_txd_tkeep(0) <= \\; + axi_str_txd_tlast <= \^axi_str_txd_tlast\; axi_str_txd_tstrb(3) <= \\; axi_str_txd_tstrb(2) <= \\; axi_str_txd_tstrb(1) <= \\; @@ -12306,6 +14219,7 @@ begin axi_str_txd_tuser(2) <= \\; axi_str_txd_tuser(1) <= \\; axi_str_txd_tuser(0) <= \\; + axi_str_txd_tvalid <= \^axi_str_txd_tvalid\; mm2s_cntrl_reset_out_n <= \\; s_axi4_arready <= \\; s_axi4_awready <= \\; @@ -12368,10 +14282,7 @@ begin s_axi_rdata(15) <= \\; s_axi_rdata(14) <= \\; s_axi_rdata(13) <= \\; - s_axi_rdata(12) <= \\; - s_axi_rdata(11) <= \\; - s_axi_rdata(10) <= \\; - s_axi_rdata(9 downto 1) <= \^s_axi_rdata\(9 downto 1); + s_axi_rdata(12 downto 1) <= \^s_axi_rdata\(12 downto 1); s_axi_rdata(0) <= \\; s_axi_rresp(1) <= \^s_axi_rresp\(1); s_axi_rresp(0) <= \\; @@ -12386,27 +14297,26 @@ COMP_IPIC2AXI_S: entity work.design_1_axi_fifo_mm_s_0_0_ipic2axi_s D(2) => sig_ip2bus_data_1(8), D(1) => sig_ip2bus_data_1(9), D(0) => sig_ip2bus_data_1(10), - E(0) => COMP_IPIF_n_41, + E(0) => COMP_IPIF_n_12, \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, IP2Bus_Error1_in => IP2Bus_Error1_in, - IP2Bus_Error_reg_0 => COMP_IPIF_n_26, + IP2Bus_Error_reg_0 => COMP_IPIF_n_24, IP2Bus_RdAck_reg_0 => \^s_axi_arready\, IP2Bus_RdAck_reg_1 => COMP_IPIF_n_13, IP2Bus_WrAck_reg_0 => \^s_axi_awready\, - IP2Bus_WrAck_reg_1 => COMP_IPIF_n_27, - IPIC_STATE_reg_0 => COMP_IPIC2AXI_S_n_41, - Q(6) => COMP_IPIC2AXI_S_n_47, - Q(5) => COMP_IPIC2AXI_S_n_48, - Q(4) => COMP_IPIC2AXI_S_n_49, - Q(3) => COMP_IPIC2AXI_S_n_50, - Q(2) => COMP_IPIC2AXI_S_n_51, - Q(1) => COMP_IPIC2AXI_S_n_52, - Q(0) => COMP_IPIC2AXI_S_n_53, + IP2Bus_WrAck_reg_1 => COMP_IPIF_n_39, + Q(6) => COMP_IPIC2AXI_S_n_45, + Q(5) => COMP_IPIC2AXI_S_n_46, + Q(4) => COMP_IPIC2AXI_S_n_47, + Q(3) => COMP_IPIC2AXI_S_n_48, + Q(2) => COMP_IPIC2AXI_S_n_49, + Q(1) => COMP_IPIC2AXI_S_n_50, + Q(0) => COMP_IPIC2AXI_S_n_51, axi_str_txd_tdata(31 downto 0) => axi_str_txd_tdata(31 downto 0), - axi_str_txd_tlast => axi_str_txd_tlast, + axi_str_txd_tlast => \^axi_str_txd_tlast\, axi_str_txd_tready => axi_str_txd_tready, - axi_str_txd_tvalid => axi_str_txd_tvalid, + axi_str_txd_tvalid => \^axi_str_txd_tvalid\, cs_ce_clr => \I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr\, interrupt => interrupt, p_1_in(0) => p_1_in(1), @@ -12414,23 +14324,25 @@ COMP_IPIC2AXI_S: entity work.design_1_axi_fifo_mm_s_0_0_ipic2axi_s s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), - s_axi_wdata_0_sp_1 => COMP_IPIC2AXI_S_n_45, - s_axi_wdata_7_sp_1 => COMP_IPIC2AXI_S_n_44, + s_axi_wdata_7_sp_1 => COMP_IPIC2AXI_S_n_43, sig_Bus2IP_CS => sig_Bus2IP_CS, sig_Bus2IP_Reset => sig_Bus2IP_Reset, - \sig_ip2bus_data_reg[0]_0\(21) => sig_ip2bus_data(0), - \sig_ip2bus_data_reg[0]_0\(20) => sig_ip2bus_data(1), - \sig_ip2bus_data_reg[0]_0\(19) => sig_ip2bus_data(2), - \sig_ip2bus_data_reg[0]_0\(18) => sig_ip2bus_data(3), - \sig_ip2bus_data_reg[0]_0\(17) => sig_ip2bus_data(4), - \sig_ip2bus_data_reg[0]_0\(16) => sig_ip2bus_data(5), - \sig_ip2bus_data_reg[0]_0\(15) => sig_ip2bus_data(6), - \sig_ip2bus_data_reg[0]_0\(14) => sig_ip2bus_data(7), - \sig_ip2bus_data_reg[0]_0\(13) => sig_ip2bus_data(8), - \sig_ip2bus_data_reg[0]_0\(12) => sig_ip2bus_data(9), - \sig_ip2bus_data_reg[0]_0\(11) => sig_ip2bus_data(10), - \sig_ip2bus_data_reg[0]_0\(10) => sig_ip2bus_data(11), - \sig_ip2bus_data_reg[0]_0\(9) => sig_ip2bus_data(12), + \sig_ip2bus_data_reg[0]_0\(24) => sig_ip2bus_data(0), + \sig_ip2bus_data_reg[0]_0\(23) => sig_ip2bus_data(1), + \sig_ip2bus_data_reg[0]_0\(22) => sig_ip2bus_data(2), + \sig_ip2bus_data_reg[0]_0\(21) => sig_ip2bus_data(3), + \sig_ip2bus_data_reg[0]_0\(20) => sig_ip2bus_data(4), + \sig_ip2bus_data_reg[0]_0\(19) => sig_ip2bus_data(5), + \sig_ip2bus_data_reg[0]_0\(18) => sig_ip2bus_data(6), + \sig_ip2bus_data_reg[0]_0\(17) => sig_ip2bus_data(7), + \sig_ip2bus_data_reg[0]_0\(16) => sig_ip2bus_data(8), + \sig_ip2bus_data_reg[0]_0\(15) => sig_ip2bus_data(9), + \sig_ip2bus_data_reg[0]_0\(14) => sig_ip2bus_data(10), + \sig_ip2bus_data_reg[0]_0\(13) => sig_ip2bus_data(11), + \sig_ip2bus_data_reg[0]_0\(12) => sig_ip2bus_data(12), + \sig_ip2bus_data_reg[0]_0\(11) => sig_ip2bus_data(19), + \sig_ip2bus_data_reg[0]_0\(10) => sig_ip2bus_data(20), + \sig_ip2bus_data_reg[0]_0\(9) => sig_ip2bus_data(21), \sig_ip2bus_data_reg[0]_0\(8) => sig_ip2bus_data(22), \sig_ip2bus_data_reg[0]_0\(7) => sig_ip2bus_data(23), \sig_ip2bus_data_reg[0]_0\(6) => sig_ip2bus_data(24), @@ -12440,18 +14352,18 @@ COMP_IPIC2AXI_S: entity work.design_1_axi_fifo_mm_s_0_0_ipic2axi_s \sig_ip2bus_data_reg[0]_0\(2) => sig_ip2bus_data(28), \sig_ip2bus_data_reg[0]_0\(1) => sig_ip2bus_data(29), \sig_ip2bus_data_reg[0]_0\(0) => sig_ip2bus_data(30), - \sig_ip2bus_data_reg[12]_0\ => COMP_IPIF_n_24, - \sig_ip2bus_data_reg[22]_0\ => COMP_IPIF_n_25, - \sig_register_array_reg[0][10]_0\ => COMP_IPIC2AXI_S_n_57, - \sig_register_array_reg[0][3]_0\ => COMP_IPIC2AXI_S_n_55, + \sig_ip2bus_data_reg[12]_0\ => COMP_IPIF_n_23, + \sig_ip2bus_data_reg[19]_0\ => COMP_IPIF_n_15, + \sig_register_array_reg[0][10]_0\ => COMP_IPIC2AXI_S_n_52, + \sig_register_array_reg[0][3]_0\ => COMP_IPIC2AXI_S_n_53, \sig_register_array_reg[0][3]_1\ => COMP_IPIF_n_10, - \sig_register_array_reg[0][4]_0\ => COMP_IPIC2AXI_S_n_54, - \sig_register_array_reg[0][4]_1\ => COMP_IPIF_n_12, - \sig_register_array_reg[0][6]_0\ => COMP_IPIC2AXI_S_n_56, - \sig_register_array_reg[0][6]_1\ => COMP_IPIF_n_8, - \sig_register_array_reg[0][7]_0\ => COMP_IPIC2AXI_S_n_58, - \sig_register_array_reg[0][8]_0\ => COMP_IPIC2AXI_S_n_60, - \sig_register_array_reg[0][9]_0\ => COMP_IPIC2AXI_S_n_59, + \sig_register_array_reg[0][4]_0\ => COMP_IPIC2AXI_S_n_55, + \sig_register_array_reg[0][4]_1\ => COMP_IPIF_n_11, + \sig_register_array_reg[0][4]_2\ => COMP_IPIF_n_8, + \sig_register_array_reg[0][6]_0\ => COMP_IPIC2AXI_S_n_57, + \sig_register_array_reg[0][7]_0\ => COMP_IPIC2AXI_S_n_54, + \sig_register_array_reg[0][8]_0\ => COMP_IPIC2AXI_S_n_56, + \sig_register_array_reg[0][9]_0\ => COMP_IPIC2AXI_S_n_58, \sig_register_array_reg[1][0]_0\(12) => \sig_register_array[1]_0\(0), \sig_register_array_reg[1][0]_0\(11) => \sig_register_array[1]_0\(1), \sig_register_array_reg[1][0]_0\(10) => \sig_register_array[1]_0\(2), @@ -12469,26 +14381,11 @@ COMP_IPIC2AXI_S: entity work.design_1_axi_fifo_mm_s_0_0_ipic2axi_s sig_str_rst_reg_1 => COMP_IPIF_n_9, sig_tx_channel_reset_reg_0 => COMP_IPIC2AXI_S_n_39, sig_tx_channel_reset_reg_1 => COMP_IPIF_n_14, - sig_txd_sb_wr_en => sig_txd_sb_wr_en, - \sig_txd_wr_data_reg[0]_0\ => COMP_IPIF_n_16, - \sig_txd_wr_data_reg[0]_1\ => COMP_IPIF_n_11 + sig_txd_sb_wr_en_reg_0 => COMP_IPIF_n_25 ); COMP_IPIF: entity work.design_1_axi_fifo_mm_s_0_0_axi_lite_ipif port map ( Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, - Bus_RNW_reg_reg(12) => \sig_register_array[1]_0\(0), - Bus_RNW_reg_reg(11) => \sig_register_array[1]_0\(1), - Bus_RNW_reg_reg(10) => \sig_register_array[1]_0\(2), - Bus_RNW_reg_reg(9) => \sig_register_array[1]_0\(3), - Bus_RNW_reg_reg(8) => \sig_register_array[1]_0\(4), - Bus_RNW_reg_reg(7) => \sig_register_array[1]_0\(5), - Bus_RNW_reg_reg(6) => \sig_register_array[1]_0\(6), - Bus_RNW_reg_reg(5) => \sig_register_array[1]_0\(7), - Bus_RNW_reg_reg(4) => \sig_register_array[1]_0\(8), - Bus_RNW_reg_reg(3) => \sig_register_array[1]_0\(9), - Bus_RNW_reg_reg(2) => \sig_register_array[1]_0\(10), - Bus_RNW_reg_reg(1) => \sig_register_array[1]_0\(11), - Bus_RNW_reg_reg(0) => \sig_register_array[1]_0\(12), D(6) => sig_ip2bus_data_1(3), D(5) => sig_ip2bus_data_1(4), D(4) => sig_ip2bus_data_1(6), @@ -12496,29 +14393,31 @@ COMP_IPIF: entity work.design_1_axi_fifo_mm_s_0_0_axi_lite_ipif D(2) => sig_ip2bus_data_1(8), D(1) => sig_ip2bus_data_1(9), D(0) => sig_ip2bus_data_1(10), - E(0) => COMP_IPIF_n_41, + E(0) => COMP_IPIF_n_12, \FSM_onehot_state_reg[2]\ => \^s_axi_awready\, \FSM_onehot_state_reg[3]\ => \^s_axi_arready\, \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg\, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => COMP_IPIF_n_9, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_0\ => COMP_IPIF_n_10, - \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]_1\ => COMP_IPIF_n_12, - \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => COMP_IPIF_n_16, - \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => COMP_IPIF_n_24, + \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => COMP_IPIF_n_10, + \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => COMP_IPIF_n_15, + \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => COMP_IPIF_n_23, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => COMP_IPIF_n_14, - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ => COMP_IPIF_n_25, - \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ => COMP_IPIF_n_26, + \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ => COMP_IPIF_n_25, + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => COMP_IPIF_n_9, + \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => COMP_IPIF_n_11, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, IP2Bus_Error1_in => IP2Bus_Error1_in, - Q(6) => COMP_IPIC2AXI_S_n_47, - Q(5) => COMP_IPIC2AXI_S_n_48, - Q(4) => COMP_IPIC2AXI_S_n_49, - Q(3) => COMP_IPIC2AXI_S_n_50, - Q(2) => COMP_IPIC2AXI_S_n_51, - Q(1) => COMP_IPIC2AXI_S_n_52, - Q(0) => COMP_IPIC2AXI_S_n_53, + IP2Bus_Error_reg => COMP_IPIC2AXI_S_n_39, + Q(6) => COMP_IPIC2AXI_S_n_45, + Q(5) => COMP_IPIC2AXI_S_n_46, + Q(4) => COMP_IPIC2AXI_S_n_47, + Q(3) => COMP_IPIC2AXI_S_n_48, + Q(2) => COMP_IPIC2AXI_S_n_49, + Q(1) => COMP_IPIC2AXI_S_n_50, + Q(0) => COMP_IPIC2AXI_S_n_51, + axi_str_txd_tlast => \^axi_str_txd_tlast\, + axi_str_txd_tvalid => \^axi_str_txd_tvalid\, bus2ip_rnw_i_reg => COMP_IPIF_n_13, - bus2ip_rnw_i_reg_0 => COMP_IPIF_n_27, + bus2ip_rnw_i_reg_0 => COMP_IPIF_n_39, cs_ce_clr => \I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr\, p_1_in(0) => p_1_in(1), s_axi_aclk => s_axi_aclk, @@ -12529,21 +14428,24 @@ COMP_IPIF: entity work.design_1_axi_fifo_mm_s_0_0_axi_lite_ipif s_axi_bready => s_axi_bready, s_axi_bresp(0) => \^s_axi_bresp\(1), s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(21 downto 9) => \^s_axi_rdata\(31 downto 19), - s_axi_rdata(8 downto 0) => \^s_axi_rdata\(9 downto 1), - \s_axi_rdata_i_reg[31]\(21) => sig_ip2bus_data(0), - \s_axi_rdata_i_reg[31]\(20) => sig_ip2bus_data(1), - \s_axi_rdata_i_reg[31]\(19) => sig_ip2bus_data(2), - \s_axi_rdata_i_reg[31]\(18) => sig_ip2bus_data(3), - \s_axi_rdata_i_reg[31]\(17) => sig_ip2bus_data(4), - \s_axi_rdata_i_reg[31]\(16) => sig_ip2bus_data(5), - \s_axi_rdata_i_reg[31]\(15) => sig_ip2bus_data(6), - \s_axi_rdata_i_reg[31]\(14) => sig_ip2bus_data(7), - \s_axi_rdata_i_reg[31]\(13) => sig_ip2bus_data(8), - \s_axi_rdata_i_reg[31]\(12) => sig_ip2bus_data(9), - \s_axi_rdata_i_reg[31]\(11) => sig_ip2bus_data(10), - \s_axi_rdata_i_reg[31]\(10) => sig_ip2bus_data(11), - \s_axi_rdata_i_reg[31]\(9) => sig_ip2bus_data(12), + s_axi_rdata(24 downto 12) => \^s_axi_rdata\(31 downto 19), + s_axi_rdata(11 downto 0) => \^s_axi_rdata\(12 downto 1), + \s_axi_rdata_i_reg[31]\(24) => sig_ip2bus_data(0), + \s_axi_rdata_i_reg[31]\(23) => sig_ip2bus_data(1), + \s_axi_rdata_i_reg[31]\(22) => sig_ip2bus_data(2), + \s_axi_rdata_i_reg[31]\(21) => sig_ip2bus_data(3), + \s_axi_rdata_i_reg[31]\(20) => sig_ip2bus_data(4), + \s_axi_rdata_i_reg[31]\(19) => sig_ip2bus_data(5), + \s_axi_rdata_i_reg[31]\(18) => sig_ip2bus_data(6), + \s_axi_rdata_i_reg[31]\(17) => sig_ip2bus_data(7), + \s_axi_rdata_i_reg[31]\(16) => sig_ip2bus_data(8), + \s_axi_rdata_i_reg[31]\(15) => sig_ip2bus_data(9), + \s_axi_rdata_i_reg[31]\(14) => sig_ip2bus_data(10), + \s_axi_rdata_i_reg[31]\(13) => sig_ip2bus_data(11), + \s_axi_rdata_i_reg[31]\(12) => sig_ip2bus_data(12), + \s_axi_rdata_i_reg[31]\(11) => sig_ip2bus_data(19), + \s_axi_rdata_i_reg[31]\(10) => sig_ip2bus_data(20), + \s_axi_rdata_i_reg[31]\(9) => sig_ip2bus_data(21), \s_axi_rdata_i_reg[31]\(8) => sig_ip2bus_data(22), \s_axi_rdata_i_reg[31]\(7) => sig_ip2bus_data(23), \s_axi_rdata_i_reg[31]\(6) => sig_ip2bus_data(24), @@ -12557,23 +14459,32 @@ COMP_IPIF: entity work.design_1_axi_fifo_mm_s_0_0_axi_lite_ipif s_axi_rresp(0) => \^s_axi_rresp\(1), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(12 downto 0) => s_axi_wdata(31 downto 19), - \s_axi_wdata[25]\ => COMP_IPIF_n_8, + \s_axi_wdata[27]\ => COMP_IPIF_n_8, + \s_axi_wdata[31]\(12) => \sig_register_array[1]_0\(0), + \s_axi_wdata[31]\(11) => \sig_register_array[1]_0\(1), + \s_axi_wdata[31]\(10) => \sig_register_array[1]_0\(2), + \s_axi_wdata[31]\(9) => \sig_register_array[1]_0\(3), + \s_axi_wdata[31]\(8) => \sig_register_array[1]_0\(4), + \s_axi_wdata[31]\(7) => \sig_register_array[1]_0\(5), + \s_axi_wdata[31]\(6) => \sig_register_array[1]_0\(6), + \s_axi_wdata[31]\(5) => \sig_register_array[1]_0\(7), + \s_axi_wdata[31]\(4) => \sig_register_array[1]_0\(8), + \s_axi_wdata[31]\(3) => \sig_register_array[1]_0\(9), + \s_axi_wdata[31]\(2) => \sig_register_array[1]_0\(10), + \s_axi_wdata[31]\(1) => \sig_register_array[1]_0\(11), + \s_axi_wdata[31]\(0) => \sig_register_array[1]_0\(12), s_axi_wvalid => s_axi_wvalid, sig_Bus2IP_CS => sig_Bus2IP_CS, sig_Bus2IP_Reset => sig_Bus2IP_Reset, - \sig_ip2bus_data_reg[10]\ => COMP_IPIC2AXI_S_n_57, - \sig_ip2bus_data_reg[3]\ => COMP_IPIC2AXI_S_n_55, - \sig_ip2bus_data_reg[4]\ => COMP_IPIC2AXI_S_n_54, - \sig_ip2bus_data_reg[6]\ => COMP_IPIC2AXI_S_n_56, - \sig_ip2bus_data_reg[7]\ => COMP_IPIC2AXI_S_n_58, - \sig_ip2bus_data_reg[8]\ => COMP_IPIC2AXI_S_n_60, - \sig_ip2bus_data_reg[9]\ => COMP_IPIC2AXI_S_n_59, - \sig_register_array_reg[0][6]\ => COMP_IPIC2AXI_S_n_41, - sig_str_rst_reg => COMP_IPIC2AXI_S_n_44, - sig_tx_channel_reset_reg => COMP_IPIF_n_11, - sig_txd_sb_wr_en => sig_txd_sb_wr_en, - sig_txd_sb_wr_en_reg => COMP_IPIC2AXI_S_n_45, - sig_txd_sb_wr_en_reg_0 => COMP_IPIC2AXI_S_n_39 + \sig_ip2bus_data_reg[10]\ => COMP_IPIC2AXI_S_n_52, + \sig_ip2bus_data_reg[3]\ => COMP_IPIC2AXI_S_n_53, + \sig_ip2bus_data_reg[4]\ => COMP_IPIC2AXI_S_n_55, + \sig_ip2bus_data_reg[6]\ => COMP_IPIC2AXI_S_n_57, + \sig_ip2bus_data_reg[7]\ => COMP_IPIC2AXI_S_n_54, + \sig_ip2bus_data_reg[8]\ => COMP_IPIC2AXI_S_n_56, + \sig_ip2bus_data_reg[9]\ => COMP_IPIC2AXI_S_n_58, + sig_str_rst_reg => COMP_IPIC2AXI_S_n_43, + sig_tx_channel_reset_reg => COMP_IPIF_n_24 ); GND: unisim.vcomponents.GND port map ( @@ -12701,11 +14612,11 @@ architecture STRUCTURE of design_1_axi_fifo_mm_s_0_0 is attribute C_TX_CASCADE_HEIGHT : integer; attribute C_TX_CASCADE_HEIGHT of U0 : label is 0; attribute C_TX_FIFO_DEPTH : integer; - attribute C_TX_FIFO_DEPTH of U0 : label is 512; + attribute C_TX_FIFO_DEPTH of U0 : label is 4096; attribute C_TX_FIFO_PE_THRESHOLD : integer; attribute C_TX_FIFO_PE_THRESHOLD of U0 : label is 5; attribute C_TX_FIFO_PF_THRESHOLD : integer; - attribute C_TX_FIFO_PF_THRESHOLD of U0 : label is 507; + attribute C_TX_FIFO_PF_THRESHOLD of U0 : label is 4091; attribute C_USE_RX_CUT_THROUGH : integer; attribute C_USE_RX_CUT_THROUGH of U0 : label is 0; attribute C_USE_RX_DATA : integer; diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v index fd196f6..b211920 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 -// Date : Thu Jan 20 22:00:03 2022 +// Date : Wed May 11 18:46:03 2022 // Host : DESKTOP-J72MK93 running 64-bit major release (build 9200) // Command : write_verilog -force -mode synth_stub -// c:/Users/Aleksa/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v +// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_Rev2/dso_top_Rev2.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v // Design : design_1_axi_fifo_mm_s_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcsg325-2 diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl index 7c0dcc8..618d3d2 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 --- Date : Thu Jan 20 22:00:03 2022 +-- Date : Wed May 11 18:46:03 2022 -- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub --- c:/Users/Aleksa/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl +-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_Rev2/dso_top_Rev2.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl -- Design : design_1_axi_fifo_mm_s_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7a35tcsg325-2 diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd index 13628cf..b27c480 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd @@ -253,11 +253,11 @@ BEGIN C_S_AXI_ADDR_WIDTH => 32, C_S_AXI_DATA_WIDTH => 32, C_S_AXI4_DATA_WIDTH => 32, - C_TX_FIFO_DEPTH => 512, + C_TX_FIFO_DEPTH => 4096, C_RX_FIFO_DEPTH => 512, C_TX_CASCADE_HEIGHT => 0, C_RX_CASCADE_HEIGHT => 0, - C_TX_FIFO_PF_THRESHOLD => 507, + C_TX_FIFO_PF_THRESHOLD => 4091, C_TX_FIFO_PE_THRESHOLD => 5, C_RX_FIFO_PF_THRESHOLD => 507, C_RX_FIFO_PE_THRESHOLD => 5, diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/synth/design_1_axi_fifo_mm_s_0_0.vhd b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/synth/design_1_axi_fifo_mm_s_0_0.vhd index 686781b..d67dd82 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/synth/design_1_axi_fifo_mm_s_0_0.vhd +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/synth/design_1_axi_fifo_mm_s_0_0.vhd @@ -216,8 +216,8 @@ ARCHITECTURE design_1_axi_fifo_mm_s_0_0_arch OF design_1_axi_fifo_mm_s_0_0 IS ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_fifo_mm_s_0_0_arch : ARCHITECTURE IS "design_1_axi_fifo_mm_s_0_0,axi_fifo_mm_s,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; - ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_fifo_mm_s_0_0_arch: ARCHITECTURE IS "design_1_axi_fifo_mm_s_0_0,axi_fifo_mm_s,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_fifo_mm_s,x_ipVersion=4.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ID_WIDTH=4,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_DATA_WIDTH=32,C_TX_FIFO_DEPTH=512,C_RX_FIFO_DEPTH=512,C_TX_CASCADE_HEIGHT=0,C_RX_CASCADE_HEIGHT=0,C_TX_FIFO_PF_THRESHOLD=507,C_TX_FIFO_PE_THRESHOLD=5,C_RX_FIFO_PF_THRESHOLD=507,C_RX_FIFO_PE_THRESHOLD=5,C_US" & -"E_TX_CUT_THROUGH=0,C_DATA_INTERFACE_TYPE=0,C_BASEADDR=0x40020000,C_HIGHADDR=0x4002FFFF,C_AXI4_BASEADDR=0x80001000,C_AXI4_HIGHADDR=0x80002FFF,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TID_WIDTH=4,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_USE_RX_CUT_THROUGH=0,C_USE_TX_DATA=1,C_USE_TX_CTRL=0,C_USE_RX_DATA=0}"; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_fifo_mm_s_0_0_arch: ARCHITECTURE IS "design_1_axi_fifo_mm_s_0_0,axi_fifo_mm_s,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_fifo_mm_s,x_ipVersion=4.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ID_WIDTH=4,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_DATA_WIDTH=32,C_TX_FIFO_DEPTH=4096,C_RX_FIFO_DEPTH=512,C_TX_CASCADE_HEIGHT=0,C_RX_CASCADE_HEIGHT=0,C_TX_FIFO_PF_THRESHOLD=4091,C_TX_FIFO_PE_THRESHOLD=5,C_RX_FIFO_PF_THRESHOLD=507,C_RX_FIFO_PE_THRESHOLD=5,C_" & +"USE_TX_CUT_THROUGH=0,C_DATA_INTERFACE_TYPE=0,C_BASEADDR=0x40020000,C_HIGHADDR=0x4002FFFF,C_AXI4_BASEADDR=0x80001000,C_AXI4_HIGHADDR=0x80002FFF,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TID_WIDTH=4,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_USE_RX_CUT_THROUGH=0,C_USE_TX_DATA=1,C_USE_TX_CTRL=0,C_USE_RX_DATA=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TDATA"; @@ -260,11 +260,11 @@ BEGIN C_S_AXI_ADDR_WIDTH => 32, C_S_AXI_DATA_WIDTH => 32, C_S_AXI4_DATA_WIDTH => 32, - C_TX_FIFO_DEPTH => 512, + C_TX_FIFO_DEPTH => 4096, C_RX_FIFO_DEPTH => 512, C_TX_CASCADE_HEIGHT => 0, C_RX_CASCADE_HEIGHT => 0, - C_TX_FIFO_PF_THRESHOLD => 507, + C_TX_FIFO_PF_THRESHOLD => 4091, C_TX_FIFO_PE_THRESHOLD => 5, C_RX_FIFO_PF_THRESHOLD => 507, C_RX_FIFO_PE_THRESHOLD => 5, diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/sim/design_1.v b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/sim/design_1.v index 7780bf2..bab2d24 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/sim/design_1.v +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/sim/design_1.v @@ -1,7 +1,7 @@ //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 -//Date : Sun Feb 13 11:02:18 2022 +//Date : Wed May 11 18:45:19 2022 //Host : DESKTOP-J72MK93 running 64-bit major release (build 9200) //Command : generate_target design_1.bd //Design : design_1 diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.hwdef b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.hwdef index ad82132..255e23f 100644 Binary files a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.hwdef and b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.hwdef differ diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.v b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.v index 7780bf2..bab2d24 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.v +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.v @@ -1,7 +1,7 @@ //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 -//Date : Sun Feb 13 11:02:18 2022 +//Date : Wed May 11 18:45:19 2022 //Host : DESKTOP-J72MK93 running 64-bit major release (build 9200) //Command : generate_target design_1.bd //Design : design_1 diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui index b5df135..0c07c19 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui @@ -1,81 +1,72 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.507657", - "Default View_TopLeft":"37,-985", - "ExpandedHierarchyInLayout":"", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"105,144", + "ExpandedHierarchyInLayout":"/AXI_LITE_IO", "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS # -string -flagsOSRD preplace port pcie -pg 1 -lvl 0 -x 0 -y 670 -defaultsOSRD -preplace port pcie_mgt -pg 1 -lvl 3 -x 1640 -y 680 -defaultsOSRD +preplace port pcie_mgt -pg 1 -lvl 3 -x 1420 -y 680 -defaultsOSRD preplace port S_AXIS_S2MM_CMD -pg 1 -lvl 0 -x 0 -y 430 -defaultsOSRD -preplace port AXI_STR_TXD_0 -pg 1 -lvl 3 -x 1640 -y 590 -defaultsOSRD +preplace port AXI_STR_TXD_0 -pg 1 -lvl 3 -x 1420 -y 590 -defaultsOSRD preplace port S_AXIS_S2MM -pg 1 -lvl 0 -x 0 -y 450 -defaultsOSRD -preplace port DDR3 -pg 1 -lvl 3 -x 1640 -y 260 -defaultsOSRD -preplace port M00_AXI_0 -pg 1 -lvl 3 -x 1640 -y 280 -defaultsOSRD +preplace port DDR3 -pg 1 -lvl 3 -x 1420 -y 260 -defaultsOSRD +preplace port M00_AXI_0 -pg 1 -lvl 3 -x 1420 -y 280 -defaultsOSRD preplace port S_AXI_0 -pg 1 -lvl 0 -x 0 -y 270 -defaultsOSRD preplace port pcie_perstn -pg 1 -lvl 0 -x 0 -y 690 -defaultsOSRD -preplace port s2mm_err -pg 1 -lvl 3 -x 1640 -y 470 -defaultsOSRD -preplace port s2mm_wr_xfer_cmplt -pg 1 -lvl 3 -x 1640 -y 490 -defaultsOSRD -preplace port axi_aresetn -pg 1 -lvl 3 -x 1640 -y 510 -defaultsOSRD +preplace port s2mm_err -pg 1 -lvl 3 -x 1420 -y 470 -defaultsOSRD +preplace port s2mm_wr_xfer_cmplt -pg 1 -lvl 3 -x 1420 -y 490 -defaultsOSRD +preplace port axi_aresetn -pg 1 -lvl 3 -x 1420 -y 510 -defaultsOSRD preplace port S01_ARESETN -pg 1 -lvl 0 -x 0 -y 490 -defaultsOSRD preplace port s2mm_halt -pg 1 -lvl 0 -x 0 -y 510 -defaultsOSRD -preplace port axi_aclk -pg 1 -lvl 3 -x 1640 -y 450 -defaultsOSRD -preplace port ui_clk_0 -pg 1 -lvl 3 -x 1640 -y 300 -defaultsOSRD -preplace port ui_clk_sync_rst_0 -pg 1 -lvl 3 -x 1640 -y 320 -defaultsOSRD +preplace port axi_aclk -pg 1 -lvl 3 -x 1420 -y 450 -defaultsOSRD +preplace port ui_clk_0 -pg 1 -lvl 3 -x 1420 -y 300 -defaultsOSRD +preplace port ui_clk_sync_rst_0 -pg 1 -lvl 3 -x 1420 -y 320 -defaultsOSRD preplace portBus gpio2_io_i -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD -preplace portBus gpio_io_o_0 -pg 1 -lvl 3 -x 1640 -y 610 -defaultsOSRD -preplace portBus init_calib_complete_0 -pg 1 -lvl 3 -x 1640 -y 380 -defaultsOSRD +preplace portBus gpio_io_o_0 -pg 1 -lvl 3 -x 1420 -y 610 -defaultsOSRD +preplace portBus init_calib_complete_0 -pg 1 -lvl 3 -x 1420 -y 380 -defaultsOSRD preplace inst Memory -pg 1 -lvl 2 -x 650 -y 100 -defaultsOSRD preplace inst Datamover -pg 1 -lvl 1 -x 190 -y 470 -defaultsOSRD -preplace inst AXI_LITE_IO -pg 1 -lvl 2 -x 650 -y 600 -defaultsOSRD +preplace inst AXI_LITE_IO -pg 1 -lvl 2 -x 650 -y 604 -defaultsOSRD preplace inst PCIe -pg 1 -lvl 1 -x 190 -y 680 -defaultsOSRD -preplace inst Memory|axi_crossbar_0 -pg 1 -lvl 4 -x 1320 -y 120 -defaultsOSRD -preplace inst Memory|clk_wiz_0 -pg 1 -lvl 2 -x 820 -y 200 -defaultsOSRD -preplace inst Memory|xlconstant_0 -pg 1 -lvl 1 -x 640 -y 190 -defaultsOSRD -preplace inst Memory|xlconstant_1 -pg 1 -lvl 2 -x 820 -y 330 -defaultsOSRD -preplace inst Memory|mig_7series_0 -pg 1 -lvl 3 -x 1050 -y 300 -defaultsOSRD -preplace inst Memory|util_ds_buf_0 -pg 1 -lvl 4 -x 1320 -y 380 -defaultsOSRD +preplace inst AXI_LITE_IO|axi_crossbar_0 -pg 1 -lvl 1 -x 710 -y 624 -defaultsOSRD +preplace inst AXI_LITE_IO|axi_fifo_mm_s_0 -pg 1 -lvl 2 -x 1030 -y 824 -defaultsOSRD +preplace inst AXI_LITE_IO|axi_gpio_0 -pg 1 -lvl 2 -x 1030 -y 654 -defaultsOSRD preplace netloc sys_rst_n_0_1 1 0 1 NJ 690 -preplace netloc xdma_0_axi_aclk 1 0 3 20 560 380 460 1620J +preplace netloc xdma_0_axi_aclk 1 0 3 20 560 380 450 NJ preplace netloc Datamover_s2mm_err_0 1 1 2 NJ 470 NJ preplace netloc Datamover_s2mm_wr_xfer_cmplt_0 1 1 2 NJ 490 NJ preplace netloc gpio2_io_i_0_1 1 0 2 NJ 580 370J -preplace netloc PCIe_axi_aresetn 1 1 2 400 510 NJ +preplace netloc PCIe_axi_aresetn 1 1 2 390 502 1390J preplace netloc S01_ARESETN_0_1 1 0 1 NJ 490 preplace netloc s2mm_halt_0_1 1 0 1 NJ 510 -preplace netloc AXI_LITE_IO_gpio_io_o_0 1 2 1 NJ 610 -preplace netloc Memory_ui_clk_0 1 2 1 NJ 300 -preplace netloc Memory_ui_clk_sync_rst_0 1 2 1 NJ 320 -preplace netloc Memory_init_calib_complete_0 1 2 1 NJ 380 -preplace netloc S_AXI_0_1 1 0 2 NJ 270 NJ -preplace netloc Memory_DDR3_0 1 2 1 NJ 260 -preplace netloc PCIe_M_AXI_LITE 1 1 1 390 570n -preplace netloc xdma_0_M_AXI 1 1 1 360 90n -preplace netloc Datamover_M_AXI_S2MM 1 1 1 370 110n -preplace netloc S_AXIS_S2MM_CMD_0_1 1 0 1 NJ 430 -preplace netloc Memory_M00_AXI_0 1 2 1 NJ 280 +preplace netloc AXI_LITE_IO_gpio_io_o_0 1 2 1 1400J 610n +preplace netloc Memory_ui_clk_0 1 2 1 1380J 100n +preplace netloc Memory_ui_clk_sync_rst_0 1 2 1 1370J 120n +preplace netloc Memory_init_calib_complete_0 1 2 1 1360J 140n preplace netloc CLK_IN_D_0_1 1 0 1 NJ 670 -preplace netloc xdma_0_pcie_mgt 1 1 2 NJ 680 NJ +preplace netloc Memory_M00_AXI_0 1 2 1 1390J 80n +preplace netloc xdma_0_pcie_mgt 1 1 2 400J 512 1370J +preplace netloc xdma_0_M_AXI 1 1 1 360 60n preplace netloc S_AXIS_S2MM_0_1 1 0 1 NJ 450 -preplace netloc AXI_LITE_IO_AXI_STR_TXD_0 1 2 1 NJ 590 -preplace netloc Memory|xlconstant_0_dout 1 1 1 NJ 190 -preplace netloc Memory|S00_ARESETN_1 1 0 4 550J 100 NJ 100 NJ 100 1180 -preplace netloc Memory|xdma_0_axi_aclk 1 0 4 560J 130 720 130 NJ 130 N -preplace netloc Memory|clk_wiz_0_clk_out1 1 2 1 910 190n -preplace netloc Memory|xlconstant_1_dout 1 2 1 920 290n -preplace netloc Memory|mig_7series_0_ui_clk 1 3 2 NJ 300 NJ -preplace netloc Memory|mig_7series_0_ui_clk_sync_rst 1 3 2 NJ 280 1460J -preplace netloc Memory|mig_7series_0_init_calib_complete 1 3 1 1180 340n -preplace netloc Memory|util_ds_buf_0_BUFG_O 1 4 1 NJ 380 -preplace netloc Memory|Conn3 1 0 3 NJ 270 NJ 270 NJ -preplace netloc Memory|S00_AXI_1 1 0 4 NJ 90 NJ 90 NJ 90 N -preplace netloc Memory|S01_AXI_1 1 0 4 NJ 110 NJ 110 NJ 110 N -preplace netloc Memory|Conn2 1 4 1 1470 120n -preplace netloc Memory|Conn1 1 3 2 NJ 260 NJ -levelinfo -pg 1 0 190 650 1640 -levelinfo -hier Memory * 640 820 1050 1320 * -pagesize -pg 1 -db -bbox -sgen -190 0 1860 770 -pagesize -hier Memory -db -bbox -sgen 520 30 1500 440 +preplace netloc S_AXIS_S2MM_CMD_0_1 1 0 1 NJ 430 +preplace netloc AXI_LITE_IO_AXI_STR_TXD_0 1 2 1 1390J 590n +preplace netloc PCIe_M_AXI_LITE 1 1 1 410 604n +preplace netloc Datamover_M_AXI_S2MM 1 1 1 370 80n +preplace netloc Memory_DDR3_0 1 2 1 1400J 60n +preplace netloc S_AXI_0_1 1 0 2 20J 100 NJ +preplace netloc AXI_LITE_IO|gpio2_io_i_1 1 0 3 NJ 744 NJ 744 1190 +preplace netloc AXI_LITE_IO|axi_aclk_1 1 0 2 560 754 860 +preplace netloc AXI_LITE_IO|axi_resetn_1 1 0 2 570 764 870 +preplace netloc AXI_LITE_IO|axi_gpio_0_gpio_io_o 1 2 1 1200 644n +preplace netloc AXI_LITE_IO|axi_crossbar_0_M00_AXI 1 1 1 850 614n +preplace netloc AXI_LITE_IO|axi_crossbar_0_M01_AXI 1 1 1 N 634 +preplace netloc AXI_LITE_IO|Conn1 1 2 1 N 804 +preplace netloc AXI_LITE_IO|S00_AXI_1 1 0 1 N 604 +levelinfo -pg 1 0 190 650 1420 +levelinfo -hier AXI_LITE_IO * 710 1030 * +pagesize -pg 1 -db -bbox -sgen -190 0 1640 940 +pagesize -hier AXI_LITE_IO -db -bbox -sgen 530 544 1230 904 " } { diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_77ae6ffa.ui b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_77ae6ffa.ui index 22ed281..6f00c3f 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_77ae6ffa.ui +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_77ae6ffa.ui @@ -7,7 +7,7 @@ "Color Coded_TopLeft":"-540,-2", "Default View_Layers":"/AXI_LITE_IO/axi_aclk_1:true|/AXI_LITE_IO/axi_resetn_1:true|", "Default View_ScaleFactor":"1.0", - "Default View_TopLeft":"-586,-82", + "Default View_TopLeft":"-432,-352", "Display-PortTypeClock":"true", "Display-PortTypeOthers":"true", "Display-PortTypeReset":"true", @@ -30,19 +30,19 @@ preplace port axi_aclk -pg 1 -lvl 0 -x 0 -y 210 -defaultsOSRD preplace port axi_resetn -pg 1 -lvl 0 -x 0 -y 230 -defaultsOSRD preplace portBus gpio2_io_i -pg 1 -lvl 0 -x 0 -y 320 -defaultsOSRD preplace portBus gpio_io_o_0 -pg 1 -lvl 3 -x 680 -y 220 -defaultsOSRD -preplace inst axi_gpio_0 -pg 1 -lvl 2 -x 500 -y 230 -defaultsOSRD -preplace inst axi_fifo_mm_s_0 -pg 1 -lvl 2 -x 500 -y 80 -defaultsOSRD preplace inst axi_crossbar_0 -pg 1 -lvl 1 -x 170 -y 210 -defaultsOSRD +preplace inst axi_fifo_mm_s_0 -pg 1 -lvl 2 -x 500 -y 80 -defaultsOSRD +preplace inst axi_gpio_0 -pg 1 -lvl 2 -x 500 -y 230 -defaultsOSRD preplace netloc gpio2_io_i_1 1 0 3 NJ 320 NJ 320 660 -preplace netloc axi_aclk_1 1 0 2 30 130 320 -preplace netloc axi_resetn_1 1 0 2 20 120 330 +preplace netloc axi_aclk_1 1 0 2 30 130 310 +preplace netloc axi_resetn_1 1 0 2 20 120 320 preplace netloc axi_gpio_0_gpio_io_o 1 2 1 NJ 220 +preplace netloc axi_crossbar_0_M00_AXI 1 1 1 300 60n +preplace netloc axi_crossbar_0_M01_AXI 1 1 1 330 210n preplace netloc Conn1 1 2 1 NJ 60 -preplace netloc axi_crossbar_0_M01_AXI 1 1 1 340 210n preplace netloc S00_AXI_1 1 0 1 NJ 190 -preplace netloc axi_crossbar_0_M00_AXI 1 1 1 310 60n levelinfo -pg 1 0 170 500 680 -pagesize -pg 1 -db -bbox -sgen -150 0 850 520 +pagesize -pg 1 -db -bbox -sgen -170 0 860 520 " } 0 diff --git a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.xpr b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.xpr index 838fa9f..661c985 100644 --- a/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.xpr +++ b/Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.xpr @@ -3,10 +3,10 @@ - + -