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Increased Serial FIFO Depth for PLL config #233

Merged
AleksaBjelogrlic merged 1 commits from FW/Aleksa/dso_top_fpga_module_Rev2_unsigned into master 2022-05-11 23:17:21 +00:00
Conversation 0 Commits 1 Files Changed 21 +9628 -6182
21 changed files with 9628 additions and 6182 deletions
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183
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bd
View File

@ -1643,24 +1643,6 @@
}
},
"interface_nets": {
"Conn2": {
"interface_ports": [
"M00_AXI_0",
"axi_crossbar_0/M00_AXI"
]
},
"S00_AXI_1": {
"interface_ports": [
"S00_AXI",
"axi_crossbar_0/S00_AXI"
]
},
"S01_AXI_1": {
"interface_ports": [
"S01_AXI",
"axi_crossbar_0/S01_AXI"
]
},
"Conn3": {
"interface_ports": [
"S_AXI_0",
@ -1672,6 +1654,24 @@
"DDR3",
"mig_7series_0/DDR3"
]
},
"S01_AXI_1": {
"interface_ports": [
"S01_AXI",
"axi_crossbar_0/S01_AXI"
]
},
"Conn2": {
"interface_ports": [
"M00_AXI_0",
"axi_crossbar_0/M00_AXI"
]
},
"S00_AXI_1": {
"interface_ports": [
"S00_AXI",
"axi_crossbar_0/S00_AXI"
]
}
},
"nets": {
@ -1819,10 +1819,10 @@
}
},
"interface_nets": {
"S_AXIS_S2MM_1": {
"Conn2": {
"interface_ports": [
"S_AXIS_S2MM",
"axi_datamover_0/S_AXIS_S2MM"
"S_AXIS_S2MM_CMD",
"axi_datamover_0/S_AXIS_S2MM_CMD"
]
},
"Conn3": {
@ -1831,10 +1831,10 @@
"axi_datamover_0/M_AXI_S2MM"
]
},
"Conn2": {
"S_AXIS_S2MM_1": {
"interface_ports": [
"S_AXIS_S2MM_CMD",
"axi_datamover_0/S_AXIS_S2MM_CMD"
"S_AXIS_S2MM",
"axi_datamover_0/S_AXIS_S2MM"
]
}
},
@ -2928,6 +2928,15 @@
"vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2",
"xci_name": "design_1_axi_fifo_mm_s_0_0",
"parameters": {
"C_TX_FIFO_DEPTH": {
"value": "4096"
},
"C_TX_FIFO_PE_THRESHOLD": {
"value": "5"
},
"C_TX_FIFO_PF_THRESHOLD": {
"value": "4091"
},
"C_USE_RX_DATA": {
"value": "0"
},
@ -2956,6 +2965,18 @@
}
},
"interface_nets": {
"S00_AXI_1": {
"interface_ports": [
"S00_AXI",
"axi_crossbar_0/S00_AXI"
]
},
"Conn1": {
"interface_ports": [
"AXI_STR_TXD_0",
"axi_fifo_mm_s_0/AXI_STR_TXD"
]
},
"axi_crossbar_0_M00_AXI": {
"interface_ports": [
"axi_crossbar_0/M00_AXI",
@ -2967,18 +2988,6 @@
"axi_crossbar_0/M01_AXI",
"axi_gpio_0/S_AXI"
]
},
"Conn1": {
"interface_ports": [
"AXI_STR_TXD_0",
"axi_fifo_mm_s_0/AXI_STR_TXD"
]
},
"S00_AXI_1": {
"interface_ports": [
"S00_AXI",
"axi_crossbar_0/S00_AXI"
]
}
},
"nets": {
@ -3202,30 +3211,30 @@
}
},
"interface_nets": {
"PCIe_M_AXI_LITE": {
"interface_ports": [
"M_AXI_LITE",
"xdma_0/M_AXI_LITE"
]
},
"xdma_0_M_AXI1": {
"interface_ports": [
"xdma_0/M_AXI",
"axi_dwidth_converter_0/S_AXI"
]
},
"xdma_0_pcie_mgt": {
"interface_ports": [
"pcie_mgt",
"xdma_0/pcie_mgt"
]
},
"CLK_IN_D_0_1": {
"interface_ports": [
"pcie",
"util_ds_buf_0/CLK_IN_D"
]
},
"PCIe_M_AXI_LITE": {
"interface_ports": [
"M_AXI_LITE",
"xdma_0/M_AXI_LITE"
]
},
"xdma_0_pcie_mgt": {
"interface_ports": [
"pcie_mgt",
"xdma_0/pcie_mgt"
]
},
"xdma_0_M_AXI": {
"interface_ports": [
"M_AXI",
@ -3264,40 +3273,10 @@
}
},
"interface_nets": {
"xdma_0_pcie_mgt": {
"S_AXI_0_1": {
"interface_ports": [
"pcie_mgt",
"PCIe/pcie_mgt"
]
},
"AXI_LITE_IO_AXI_STR_TXD_0": {
"interface_ports": [
"AXI_STR_TXD_0",
"AXI_LITE_IO/AXI_STR_TXD_0"
]
},
"S_AXIS_S2MM_0_1": {
"interface_ports": [
"S_AXIS_S2MM",
"Datamover/S_AXIS_S2MM"
]
},
"CLK_IN_D_0_1": {
"interface_ports": [
"pcie",
"PCIe/pcie"
]
},
"xdma_0_M_AXI": {
"interface_ports": [
"PCIe/M_AXI",
"Memory/S00_AXI"
]
},
"S_AXIS_S2MM_CMD_0_1": {
"interface_ports": [
"S_AXIS_S2MM_CMD",
"Datamover/S_AXIS_S2MM_CMD"
"S_AXI_0",
"Memory/S_AXI_0"
]
},
"Memory_M00_AXI_0": {
@ -3306,10 +3285,40 @@
"Memory/M00_AXI_0"
]
},
"Datamover_M_AXI_S2MM": {
"xdma_0_M_AXI": {
"interface_ports": [
"Datamover/M_AXI_S2MM",
"Memory/S01_AXI"
"PCIe/M_AXI",
"Memory/S00_AXI"
]
},
"xdma_0_pcie_mgt": {
"interface_ports": [
"pcie_mgt",
"PCIe/pcie_mgt"
]
},
"S_AXIS_S2MM_0_1": {
"interface_ports": [
"S_AXIS_S2MM",
"Datamover/S_AXIS_S2MM"
]
},
"S_AXIS_S2MM_CMD_0_1": {
"interface_ports": [
"S_AXIS_S2MM_CMD",
"Datamover/S_AXIS_S2MM_CMD"
]
},
"AXI_LITE_IO_AXI_STR_TXD_0": {
"interface_ports": [
"AXI_STR_TXD_0",
"AXI_LITE_IO/AXI_STR_TXD_0"
]
},
"CLK_IN_D_0_1": {
"interface_ports": [
"pcie",
"PCIe/pcie"
]
},
"PCIe_M_AXI_LITE": {
@ -3318,10 +3327,10 @@
"AXI_LITE_IO/S00_AXI"
]
},
"S_AXI_0_1": {
"Datamover_M_AXI_S2MM": {
"interface_ports": [
"S_AXI_0",
"Memory/S_AXI_0"
"Datamover/M_AXI_S2MM",
"Memory/S01_AXI"
]
},
"Memory_DDR3_0": {

26
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/design_1.bxml
View File

@ -2,14 +2,14 @@
<Root MajorVersion="0" MinorVersion="39">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1644768161"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1644768161"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1644768161"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1644768161"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1652309120"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1652309120"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1652309120"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1652309120"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip\design_1_xdma_0_0\design_1_xdma_0_0.xci" Type="IP">
<Instance HierarchyPath="PCIe/xdma_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642726721" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1644731037" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -25,7 +25,7 @@
</File>
<File Name="ip\design_1_clk_wiz_0_0\design_1_clk_wiz_0_0.xci" Type="IP">
<Instance HierarchyPath="Memory/clk_wiz_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642728078" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642730712" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -49,7 +49,7 @@
</File>
<File Name="ip\design_1_axi_datamover_0_0\design_1_axi_datamover_0_0.xci" Type="IP">
<Instance HierarchyPath="Datamover/axi_datamover_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642728078" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642730713" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -73,7 +73,7 @@
</File>
<File Name="ip\design_1_axi_fifo_mm_s_0_0\design_1_axi_fifo_mm_s_0_0.xci" Type="IP">
<Instance HierarchyPath="AXI_LITE_IO/axi_fifo_mm_s_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642728078" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642730713" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -81,7 +81,7 @@
</File>
<File Name="ip\design_1_axi_dwidth_converter_0_0\design_1_axi_dwidth_converter_0_0.xci" Type="IP">
<Instance HierarchyPath="PCIe/axi_dwidth_converter_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642728078" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642730713" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -89,7 +89,7 @@
</File>
<File Name="ip\design_1_axi_crossbar_0_0\design_1_axi_crossbar_0_0.xci" Type="IP">
<Instance HierarchyPath="AXI_LITE_IO/axi_crossbar_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642728078" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642730713" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -97,7 +97,7 @@
</File>
<File Name="ip\design_1_axi_crossbar_0_1\design_1_axi_crossbar_0_1.xci" Type="IP">
<Instance HierarchyPath="Memory/axi_crossbar_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1642728078" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1644735993" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -105,7 +105,7 @@
</File>
<File Name="ip\design_1_mig_7series_0_1\design_1_mig_7series_0_1.xci" Type="IP">
<Instance HierarchyPath="Memory/mig_7series_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1644768125" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
@ -124,7 +124,7 @@
</File>
<File Name="ip\design_1_util_ds_buf_0_1\design_1_util_ds_buf_0_1.xci" Type="IP">
<Instance HierarchyPath="Memory/util_ds_buf_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="1644735827" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>

2
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
View File

@ -1,7 +1,7 @@
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date : Sun Feb 13 11:02:18 2022
//Date : Wed May 11 18:45:19 2022
//Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper

564
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Feb 13 11:02:41 2022" VIVADOVERSION="2020.1">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed May 11 18:45:20 2022" VIVADOVERSION="2020.1">
<SYSTEMINFO ARCH="artix7" DEVICE="7a35t" NAME="design_1" PACKAGE="csg325" SPEEDGRADE="-2"/>
@ -65,279 +65,14 @@
<CONNECTION INSTANCE="Memory_util_ds_buf_0" PORT="BUFG_O"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="0" NAME="S_AXI_0_awid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awid">
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_p" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_P">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awid"/>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_P"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="27" NAME="S_AXI_0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awaddr">
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_n" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_N">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="S_AXI_0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="S_AXI_0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_awlock" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awqos">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_awvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_awready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="255" NAME="S_AXI_0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S_AXI_0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_wlast" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_wvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_wready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_bready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="S_AXI_0_bid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S_AXI_0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_bvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="0" NAME="S_AXI_0_arid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="27" NAME="S_AXI_0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="S_AXI_0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="S_AXI_0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_arlock" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_arvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_arready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_rready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="S_AXI_0_rid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="255" NAME="S_AXI_0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S_AXI_0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_rlast" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_rvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="31" NAME="DDR3_dq" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dq">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dq"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR3_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dqs_p">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dqs_p"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR3_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dqs_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dqs_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="12" NAME="DDR3_addr" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_addr">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_addr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="DDR3_ba" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_ba">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ba"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_ras_n" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_ras_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ras_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_cas_n" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_cas_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_cas_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_we_n" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_we_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_we_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="Memory_mig_7series_0_ddr3_reset_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_reset_n"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="O" LEFT="0" NAME="DDR3_ck_p" RIGHT="0" SIGIS="clk" SIGNAME="Memory_mig_7series_0_ddr3_ck_p">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ck_p"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="O" LEFT="0" NAME="DDR3_ck_n" RIGHT="0" SIGIS="clk" SIGNAME="Memory_mig_7series_0_ddr3_ck_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ck_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="DDR3_cke" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_cke">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_cke"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="DDR3_cs_n" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_cs_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_cs_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="DDR3_dm" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dm">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="DDR3_odt" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_odt">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_odt"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="71" NAME="S_AXIS_S2MM_CMD_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_S2MM_CMD_tready" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_S2MM_CMD_tvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tvalid"/>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_N"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_0_awid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_axi_crossbar_0_m_axi_awid">
@ -540,16 +275,6 @@
<CONNECTION INSTANCE="Memory_axi_crossbar_0" PORT="m_axi_rready"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_p" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_P">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_P"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_n" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_N">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_N"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="pcie_mgt_rxn" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_rxn">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_rxn"/>
@ -595,6 +320,21 @@
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="71" NAME="S_AXIS_S2MM_CMD_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_S2MM_CMD_tready" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_S2MM_CMD_tvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="AXI_STR_TXD_0_tdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tdata"/>
@ -615,6 +355,266 @@
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="31" NAME="DDR3_dq" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dq">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dq"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR3_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dqs_p">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dqs_p"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR3_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dqs_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dqs_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="12" NAME="DDR3_addr" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_addr">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_addr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="DDR3_ba" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_ba">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ba"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_ras_n" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_ras_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ras_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_cas_n" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_cas_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_cas_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_we_n" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_we_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_we_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="DDR3_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="Memory_mig_7series_0_ddr3_reset_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_reset_n"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="O" LEFT="0" NAME="DDR3_ck_p" RIGHT="0" SIGIS="clk" SIGNAME="Memory_mig_7series_0_ddr3_ck_p">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ck_p"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="O" LEFT="0" NAME="DDR3_ck_n" RIGHT="0" SIGIS="clk" SIGNAME="Memory_mig_7series_0_ddr3_ck_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_ck_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="DDR3_cke" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_cke">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_cke"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="DDR3_cs_n" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_cs_n">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_cs_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="DDR3_dm" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dm">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_dm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="DDR3_odt" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_odt">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_odt"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="0" NAME="S_AXI_0_awid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="27" NAME="S_AXI_0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="S_AXI_0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="S_AXI_0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_awlock" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awqos">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_awvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_awready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="255" NAME="S_AXI_0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S_AXI_0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_wlast" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_wvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_wready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_bready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="S_AXI_0_bid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S_AXI_0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_bvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="0" NAME="S_AXI_0_arid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="27" NAME="S_AXI_0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="S_AXI_0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="S_AXI_0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_arlock" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S_AXI_0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_arvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_arready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_0_rready" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="S_AXI_0_rid" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="255" NAME="S_AXI_0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S_AXI_0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_rlast" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_0_rvalid" SIGIS="undef" SIGNAME="Memory_mig_7series_0_s_axi_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_rvalid"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
@ -2542,11 +2542,11 @@
<PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_S_AXI4_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_TX_FIFO_DEPTH" VALUE="512"/>
<PARAMETER NAME="C_TX_FIFO_DEPTH" VALUE="4096"/>
<PARAMETER NAME="C_RX_FIFO_DEPTH" VALUE="512"/>
<PARAMETER NAME="C_TX_CASCADE_HEIGHT" VALUE="0"/>
<PARAMETER NAME="C_RX_CASCADE_HEIGHT" VALUE="0"/>
<PARAMETER NAME="C_TX_FIFO_PF_THRESHOLD" VALUE="507"/>
<PARAMETER NAME="C_TX_FIFO_PF_THRESHOLD" VALUE="4091"/>
<PARAMETER NAME="C_TX_FIFO_PE_THRESHOLD" VALUE="5"/>
<PARAMETER NAME="C_RX_FIFO_PF_THRESHOLD" VALUE="507"/>
<PARAMETER NAME="C_RX_FIFO_PE_THRESHOLD" VALUE="5"/>

3
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
View File

@ -1308,6 +1308,9 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
# Create instance: axi_fifo_mm_s_0, and set properties
set axi_fifo_mm_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_fifo_mm_s:4.2 axi_fifo_mm_s_0 ]
set_property -dict [ list \
CONFIG.C_TX_FIFO_DEPTH {4096} \
CONFIG.C_TX_FIFO_PE_THRESHOLD {5} \
CONFIG.C_TX_FIFO_PF_THRESHOLD {4091} \
CONFIG.C_USE_RX_DATA {0} \
CONFIG.C_USE_TX_CTRL {0} \
] $axi_fifo_mm_s_0

BIN
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.dcp
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Binary file not shown.

11
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci
View File

@ -145,9 +145,9 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_CASCADE_HEIGHT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_DEPTH">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_DEPTH">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_PE_THRESHOLD">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">507</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">4091</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RX_CUT_THROUGH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RX_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TX_CTRL">0</spirit:configurableElementValue>
@ -183,9 +183,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_CASCADE_HEIGHT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_DEPTH">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_DEPTH">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_PE_THRESHOLD">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">507</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">4091</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_RX_CUT_THROUGH">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_RX_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TX_CTRL">0</spirit:configurableElementValue>
@ -269,6 +269,9 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HAS_AXIS_TID" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_DEPTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_PE_THRESHOLD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_RX_DATA" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_TX_CTRL" xilinx:valueSource="user"/>
</xilinx:configElementInfos>

33
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xml
View File

@ -2729,7 +2729,7 @@ If the number of packets received is one, then this register returns the value o
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:0b3eebe4</spirit:value>
<spirit:value>9:98214153</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -2743,11 +2743,11 @@ If the number of packets received is one, then this register returns the value o
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 21 02:05:28 UTC 2022</spirit:value>
<spirit:value>Wed May 11 22:45:19 UTC 2022</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:0b3eebe4</spirit:value>
<spirit:value>9:98214153</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -2763,11 +2763,11 @@ If the number of packets received is one, then this register returns the value o
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 21 02:05:28 UTC 2022</spirit:value>
<spirit:value>Wed May 11 22:45:19 UTC 2022</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:0b3eebe4</spirit:value>
<spirit:value>9:98214153</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -2798,7 +2798,7 @@ If the number of packets received is one, then this register returns the value o
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ec828180</spirit:value>
<spirit:value>9:a28c6e28</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -2814,11 +2814,11 @@ If the number of packets received is one, then this register returns the value o
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 21 02:05:28 UTC 2022</spirit:value>
<spirit:value>Wed May 11 22:45:19 UTC 2022</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ec828180</spirit:value>
<spirit:value>9:a28c6e28</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -2832,11 +2832,11 @@ If the number of packets received is one, then this register returns the value o
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 21 03:00:03 UTC 2022</spirit:value>
<spirit:value>Wed May 11 22:46:03 UTC 2022</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:0b3eebe4</spirit:value>
<spirit:value>9:98214153</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -4989,7 +4989,7 @@ If the number of packets received is one, then this register returns the value o
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_TX_FIFO_DEPTH</spirit:name>
<spirit:displayName>Tx Fifo Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_FIFO_DEPTH">512</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_FIFO_DEPTH">4096</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_RX_FIFO_DEPTH</spirit:name>
@ -5009,7 +5009,7 @@ If the number of packets received is one, then this register returns the value o
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_TX_FIFO_PF_THRESHOLD</spirit:name>
<spirit:displayName>Tx PF Threshold</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_FIFO_PF_THRESHOLD" spirit:minimum="10" spirit:maximum="131067" spirit:rangeType="long">507</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_FIFO_PF_THRESHOLD" spirit:minimum="10" spirit:maximum="131067" spirit:rangeType="long">4091</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_TX_FIFO_PE_THRESHOLD</spirit:name>
@ -5439,12 +5439,12 @@ If the number of packets received is one, then this register returns the value o
<spirit:parameter>
<spirit:name>C_TX_FIFO_PE_THRESHOLD</spirit:name>
<spirit:displayName>Transmit Fifo Programable Empty Threshold</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TX_FIFO_PE_THRESHOLD" spirit:order="1600" spirit:minimum="2" spirit:maximum="502" spirit:rangeType="long">5</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TX_FIFO_PE_THRESHOLD" spirit:order="1600" spirit:minimum="2" spirit:maximum="4086" spirit:rangeType="long">5</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_TX_FIFO_PF_THRESHOLD</spirit:name>
<spirit:displayName>Transmit Fifo Programable Full Threshold</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD" spirit:order="1500" spirit:minimum="10" spirit:maximum="507" spirit:rangeType="long">507</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD" spirit:order="1500" spirit:minimum="10" spirit:maximum="4091" spirit:rangeType="long">4091</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_RX_FIFO_DEPTH</spirit:name>
@ -5454,7 +5454,7 @@ If the number of packets received is one, then this register returns the value o
<spirit:parameter>
<spirit:name>C_TX_FIFO_DEPTH</spirit:name>
<spirit:displayName>Transmit Fifo Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TX_FIFO_DEPTH" spirit:choiceRef="choice_list_cb97c1b0" spirit:order="1300">512</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TX_FIFO_DEPTH" spirit:choiceRef="choice_list_cb97c1b0" spirit:order="1300">4096</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_HIGHADDR</spirit:name>
@ -5643,6 +5643,9 @@ If the number of packets received is one, then this register returns the value o
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HAS_AXIS_TID" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="propagated"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_DEPTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_PE_THRESHOLD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_RX_DATA" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_TX_CTRL" xilinx:valueSource="user"/>
</xilinx:configElementInfos>

6844
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v
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File diff suppressed because it is too large Load Diff

7913
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.vhdl
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File diff suppressed because it is too large Load Diff

4
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v
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@ -1,10 +1,10 @@
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Thu Jan 20 22:00:03 2022
// Date : Wed May 11 18:46:03 2022
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Aleksa/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_Rev2/dso_top_Rev2.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.v
// Design : design_1_axi_fifo_mm_s_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg325-2

4
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl
View File

@ -1,10 +1,10 @@
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Thu Jan 20 22:00:03 2022
-- Date : Wed May 11 18:46:03 2022
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/Aleksa/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_Rev2/dso_top_Rev2.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_stub.vhdl
-- Design : design_1_axi_fifo_mm_s_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg325-2

4
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd
View File

@ -253,11 +253,11 @@ BEGIN
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_DATA_WIDTH => 32,
C_TX_FIFO_DEPTH => 512,
C_TX_FIFO_DEPTH => 4096,
C_RX_FIFO_DEPTH => 512,
C_TX_CASCADE_HEIGHT => 0,
C_RX_CASCADE_HEIGHT => 0,
C_TX_FIFO_PF_THRESHOLD => 507,
C_TX_FIFO_PF_THRESHOLD => 4091,
C_TX_FIFO_PE_THRESHOLD => 5,
C_RX_FIFO_PF_THRESHOLD => 507,
C_RX_FIFO_PE_THRESHOLD => 5,

8
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/synth/design_1_axi_fifo_mm_s_0_0.vhd
View File

@ -216,8 +216,8 @@ ARCHITECTURE design_1_axi_fifo_mm_s_0_0_arch OF design_1_axi_fifo_mm_s_0_0 IS
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_fifo_mm_s_0_0_arch : ARCHITECTURE IS "design_1_axi_fifo_mm_s_0_0,axi_fifo_mm_s,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_fifo_mm_s_0_0_arch: ARCHITECTURE IS "design_1_axi_fifo_mm_s_0_0,axi_fifo_mm_s,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_fifo_mm_s,x_ipVersion=4.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ID_WIDTH=4,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_DATA_WIDTH=32,C_TX_FIFO_DEPTH=512,C_RX_FIFO_DEPTH=512,C_TX_CASCADE_HEIGHT=0,C_RX_CASCADE_HEIGHT=0,C_TX_FIFO_PF_THRESHOLD=507,C_TX_FIFO_PE_THRESHOLD=5,C_RX_FIFO_PF_THRESHOLD=507,C_RX_FIFO_PE_THRESHOLD=5,C_US" &
"E_TX_CUT_THROUGH=0,C_DATA_INTERFACE_TYPE=0,C_BASEADDR=0x40020000,C_HIGHADDR=0x4002FFFF,C_AXI4_BASEADDR=0x80001000,C_AXI4_HIGHADDR=0x80002FFF,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TID_WIDTH=4,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_USE_RX_CUT_THROUGH=0,C_USE_TX_DATA=1,C_USE_TX_CTRL=0,C_USE_RX_DATA=0}";
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_fifo_mm_s_0_0_arch: ARCHITECTURE IS "design_1_axi_fifo_mm_s_0_0,axi_fifo_mm_s,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_fifo_mm_s,x_ipVersion=4.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ID_WIDTH=4,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_DATA_WIDTH=32,C_TX_FIFO_DEPTH=4096,C_RX_FIFO_DEPTH=512,C_TX_CASCADE_HEIGHT=0,C_RX_CASCADE_HEIGHT=0,C_TX_FIFO_PF_THRESHOLD=4091,C_TX_FIFO_PE_THRESHOLD=5,C_RX_FIFO_PF_THRESHOLD=507,C_RX_FIFO_PE_THRESHOLD=5,C_" &
"USE_TX_CUT_THROUGH=0,C_DATA_INTERFACE_TYPE=0,C_BASEADDR=0x40020000,C_HIGHADDR=0x4002FFFF,C_AXI4_BASEADDR=0x80001000,C_AXI4_HIGHADDR=0x80002FFF,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TID_WIDTH=4,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_USE_RX_CUT_THROUGH=0,C_USE_TX_DATA=1,C_USE_TX_CTRL=0,C_USE_RX_DATA=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TDATA";
@ -260,11 +260,11 @@ BEGIN
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_DATA_WIDTH => 32,
C_TX_FIFO_DEPTH => 512,
C_TX_FIFO_DEPTH => 4096,
C_RX_FIFO_DEPTH => 512,
C_TX_CASCADE_HEIGHT => 0,
C_RX_CASCADE_HEIGHT => 0,
C_TX_FIFO_PF_THRESHOLD => 507,
C_TX_FIFO_PF_THRESHOLD => 4091,
C_TX_FIFO_PE_THRESHOLD => 5,
C_RX_FIFO_PF_THRESHOLD => 507,
C_RX_FIFO_PE_THRESHOLD => 5,

2
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/sim/design_1.v
View File

@ -1,7 +1,7 @@
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date : Sun Feb 13 11:02:18 2022
//Date : Wed May 11 18:45:19 2022
//Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd
//Design : design_1

BIN
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.hwdef
View File

Binary file not shown.

2
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/synth/design_1.v
View File

@ -1,7 +1,7 @@
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date : Sun Feb 13 11:02:18 2022
//Date : Wed May 11 18:45:19 2022
//Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd
//Design : design_1

101
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
View File

@ -1,81 +1,72 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.507657",
"Default View_TopLeft":"37,-985",
"ExpandedHierarchyInLayout":"",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"105,144",
"ExpandedHierarchyInLayout":"/AXI_LITE_IO",
"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS
# -string -flagsOSRD
preplace port pcie -pg 1 -lvl 0 -x 0 -y 670 -defaultsOSRD
preplace port pcie_mgt -pg 1 -lvl 3 -x 1640 -y 680 -defaultsOSRD
preplace port pcie_mgt -pg 1 -lvl 3 -x 1420 -y 680 -defaultsOSRD
preplace port S_AXIS_S2MM_CMD -pg 1 -lvl 0 -x 0 -y 430 -defaultsOSRD
preplace port AXI_STR_TXD_0 -pg 1 -lvl 3 -x 1640 -y 590 -defaultsOSRD
preplace port AXI_STR_TXD_0 -pg 1 -lvl 3 -x 1420 -y 590 -defaultsOSRD
preplace port S_AXIS_S2MM -pg 1 -lvl 0 -x 0 -y 450 -defaultsOSRD
preplace port DDR3 -pg 1 -lvl 3 -x 1640 -y 260 -defaultsOSRD
preplace port M00_AXI_0 -pg 1 -lvl 3 -x 1640 -y 280 -defaultsOSRD
preplace port DDR3 -pg 1 -lvl 3 -x 1420 -y 260 -defaultsOSRD
preplace port M00_AXI_0 -pg 1 -lvl 3 -x 1420 -y 280 -defaultsOSRD
preplace port S_AXI_0 -pg 1 -lvl 0 -x 0 -y 270 -defaultsOSRD
preplace port pcie_perstn -pg 1 -lvl 0 -x 0 -y 690 -defaultsOSRD
preplace port s2mm_err -pg 1 -lvl 3 -x 1640 -y 470 -defaultsOSRD
preplace port s2mm_wr_xfer_cmplt -pg 1 -lvl 3 -x 1640 -y 490 -defaultsOSRD
preplace port axi_aresetn -pg 1 -lvl 3 -x 1640 -y 510 -defaultsOSRD
preplace port s2mm_err -pg 1 -lvl 3 -x 1420 -y 470 -defaultsOSRD
preplace port s2mm_wr_xfer_cmplt -pg 1 -lvl 3 -x 1420 -y 490 -defaultsOSRD
preplace port axi_aresetn -pg 1 -lvl 3 -x 1420 -y 510 -defaultsOSRD
preplace port S01_ARESETN -pg 1 -lvl 0 -x 0 -y 490 -defaultsOSRD
preplace port s2mm_halt -pg 1 -lvl 0 -x 0 -y 510 -defaultsOSRD
preplace port axi_aclk -pg 1 -lvl 3 -x 1640 -y 450 -defaultsOSRD
preplace port ui_clk_0 -pg 1 -lvl 3 -x 1640 -y 300 -defaultsOSRD
preplace port ui_clk_sync_rst_0 -pg 1 -lvl 3 -x 1640 -y 320 -defaultsOSRD
preplace port axi_aclk -pg 1 -lvl 3 -x 1420 -y 450 -defaultsOSRD
preplace port ui_clk_0 -pg 1 -lvl 3 -x 1420 -y 300 -defaultsOSRD
preplace port ui_clk_sync_rst_0 -pg 1 -lvl 3 -x 1420 -y 320 -defaultsOSRD
preplace portBus gpio2_io_i -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD
preplace portBus gpio_io_o_0 -pg 1 -lvl 3 -x 1640 -y 610 -defaultsOSRD
preplace portBus init_calib_complete_0 -pg 1 -lvl 3 -x 1640 -y 380 -defaultsOSRD
preplace portBus gpio_io_o_0 -pg 1 -lvl 3 -x 1420 -y 610 -defaultsOSRD
preplace portBus init_calib_complete_0 -pg 1 -lvl 3 -x 1420 -y 380 -defaultsOSRD
preplace inst Memory -pg 1 -lvl 2 -x 650 -y 100 -defaultsOSRD
preplace inst Datamover -pg 1 -lvl 1 -x 190 -y 470 -defaultsOSRD
preplace inst AXI_LITE_IO -pg 1 -lvl 2 -x 650 -y 600 -defaultsOSRD
preplace inst AXI_LITE_IO -pg 1 -lvl 2 -x 650 -y 604 -defaultsOSRD
preplace inst PCIe -pg 1 -lvl 1 -x 190 -y 680 -defaultsOSRD
preplace inst Memory|axi_crossbar_0 -pg 1 -lvl 4 -x 1320 -y 120 -defaultsOSRD
preplace inst Memory|clk_wiz_0 -pg 1 -lvl 2 -x 820 -y 200 -defaultsOSRD
preplace inst Memory|xlconstant_0 -pg 1 -lvl 1 -x 640 -y 190 -defaultsOSRD
preplace inst Memory|xlconstant_1 -pg 1 -lvl 2 -x 820 -y 330 -defaultsOSRD
preplace inst Memory|mig_7series_0 -pg 1 -lvl 3 -x 1050 -y 300 -defaultsOSRD
preplace inst Memory|util_ds_buf_0 -pg 1 -lvl 4 -x 1320 -y 380 -defaultsOSRD
preplace inst AXI_LITE_IO|axi_crossbar_0 -pg 1 -lvl 1 -x 710 -y 624 -defaultsOSRD
preplace inst AXI_LITE_IO|axi_fifo_mm_s_0 -pg 1 -lvl 2 -x 1030 -y 824 -defaultsOSRD
preplace inst AXI_LITE_IO|axi_gpio_0 -pg 1 -lvl 2 -x 1030 -y 654 -defaultsOSRD
preplace netloc sys_rst_n_0_1 1 0 1 NJ 690
preplace netloc xdma_0_axi_aclk 1 0 3 20 560 380 460 1620J
preplace netloc xdma_0_axi_aclk 1 0 3 20 560 380 450 NJ
preplace netloc Datamover_s2mm_err_0 1 1 2 NJ 470 NJ
preplace netloc Datamover_s2mm_wr_xfer_cmplt_0 1 1 2 NJ 490 NJ
preplace netloc gpio2_io_i_0_1 1 0 2 NJ 580 370J
preplace netloc PCIe_axi_aresetn 1 1 2 400 510 NJ
preplace netloc PCIe_axi_aresetn 1 1 2 390 502 1390J
preplace netloc S01_ARESETN_0_1 1 0 1 NJ 490
preplace netloc s2mm_halt_0_1 1 0 1 NJ 510
preplace netloc AXI_LITE_IO_gpio_io_o_0 1 2 1 NJ 610
preplace netloc Memory_ui_clk_0 1 2 1 NJ 300
preplace netloc Memory_ui_clk_sync_rst_0 1 2 1 NJ 320
preplace netloc Memory_init_calib_complete_0 1 2 1 NJ 380
preplace netloc S_AXI_0_1 1 0 2 NJ 270 NJ
preplace netloc Memory_DDR3_0 1 2 1 NJ 260
preplace netloc PCIe_M_AXI_LITE 1 1 1 390 570n
preplace netloc xdma_0_M_AXI 1 1 1 360 90n
preplace netloc Datamover_M_AXI_S2MM 1 1 1 370 110n
preplace netloc S_AXIS_S2MM_CMD_0_1 1 0 1 NJ 430
preplace netloc Memory_M00_AXI_0 1 2 1 NJ 280
preplace netloc AXI_LITE_IO_gpio_io_o_0 1 2 1 1400J 610n
preplace netloc Memory_ui_clk_0 1 2 1 1380J 100n
preplace netloc Memory_ui_clk_sync_rst_0 1 2 1 1370J 120n
preplace netloc Memory_init_calib_complete_0 1 2 1 1360J 140n
preplace netloc CLK_IN_D_0_1 1 0 1 NJ 670
preplace netloc xdma_0_pcie_mgt 1 1 2 NJ 680 NJ
preplace netloc Memory_M00_AXI_0 1 2 1 1390J 80n
preplace netloc xdma_0_pcie_mgt 1 1 2 400J 512 1370J
preplace netloc xdma_0_M_AXI 1 1 1 360 60n
preplace netloc S_AXIS_S2MM_0_1 1 0 1 NJ 450
preplace netloc AXI_LITE_IO_AXI_STR_TXD_0 1 2 1 NJ 590
preplace netloc Memory|xlconstant_0_dout 1 1 1 NJ 190
preplace netloc Memory|S00_ARESETN_1 1 0 4 550J 100 NJ 100 NJ 100 1180
preplace netloc Memory|xdma_0_axi_aclk 1 0 4 560J 130 720 130 NJ 130 N
preplace netloc Memory|clk_wiz_0_clk_out1 1 2 1 910 190n
preplace netloc Memory|xlconstant_1_dout 1 2 1 920 290n
preplace netloc Memory|mig_7series_0_ui_clk 1 3 2 NJ 300 NJ
preplace netloc Memory|mig_7series_0_ui_clk_sync_rst 1 3 2 NJ 280 1460J
preplace netloc Memory|mig_7series_0_init_calib_complete 1 3 1 1180 340n
preplace netloc Memory|util_ds_buf_0_BUFG_O 1 4 1 NJ 380
preplace netloc Memory|Conn3 1 0 3 NJ 270 NJ 270 NJ
preplace netloc Memory|S00_AXI_1 1 0 4 NJ 90 NJ 90 NJ 90 N
preplace netloc Memory|S01_AXI_1 1 0 4 NJ 110 NJ 110 NJ 110 N
preplace netloc Memory|Conn2 1 4 1 1470 120n
preplace netloc Memory|Conn1 1 3 2 NJ 260 NJ
levelinfo -pg 1 0 190 650 1640
levelinfo -hier Memory * 640 820 1050 1320 *
pagesize -pg 1 -db -bbox -sgen -190 0 1860 770
pagesize -hier Memory -db -bbox -sgen 520 30 1500 440
preplace netloc S_AXIS_S2MM_CMD_0_1 1 0 1 NJ 430
preplace netloc AXI_LITE_IO_AXI_STR_TXD_0 1 2 1 1390J 590n
preplace netloc PCIe_M_AXI_LITE 1 1 1 410 604n
preplace netloc Datamover_M_AXI_S2MM 1 1 1 370 80n
preplace netloc Memory_DDR3_0 1 2 1 1400J 60n
preplace netloc S_AXI_0_1 1 0 2 20J 100 NJ
preplace netloc AXI_LITE_IO|gpio2_io_i_1 1 0 3 NJ 744 NJ 744 1190
preplace netloc AXI_LITE_IO|axi_aclk_1 1 0 2 560 754 860
preplace netloc AXI_LITE_IO|axi_resetn_1 1 0 2 570 764 870
preplace netloc AXI_LITE_IO|axi_gpio_0_gpio_io_o 1 2 1 1200 644n
preplace netloc AXI_LITE_IO|axi_crossbar_0_M00_AXI 1 1 1 850 614n
preplace netloc AXI_LITE_IO|axi_crossbar_0_M01_AXI 1 1 1 N 634
preplace netloc AXI_LITE_IO|Conn1 1 2 1 N 804
preplace netloc AXI_LITE_IO|S00_AXI_1 1 0 1 N 604
levelinfo -pg 1 0 190 650 1420
levelinfo -hier AXI_LITE_IO * 710 1030 *
pagesize -pg 1 -db -bbox -sgen -190 0 1640 940
pagesize -hier AXI_LITE_IO -db -bbox -sgen 530 544 1230 904
"
}
{

16
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.srcs/sources_1/bd/design_1/ui/bd_77ae6ffa.ui
View File

@ -7,7 +7,7 @@
"Color Coded_TopLeft":"-540,-2",
"Default View_Layers":"/AXI_LITE_IO/axi_aclk_1:true|/AXI_LITE_IO/axi_resetn_1:true|",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-586,-82",
"Default View_TopLeft":"-432,-352",
"Display-PortTypeClock":"true",
"Display-PortTypeOthers":"true",
"Display-PortTypeReset":"true",
@ -30,19 +30,19 @@ preplace port axi_aclk -pg 1 -lvl 0 -x 0 -y 210 -defaultsOSRD
preplace port axi_resetn -pg 1 -lvl 0 -x 0 -y 230 -defaultsOSRD
preplace portBus gpio2_io_i -pg 1 -lvl 0 -x 0 -y 320 -defaultsOSRD
preplace portBus gpio_io_o_0 -pg 1 -lvl 3 -x 680 -y 220 -defaultsOSRD
preplace inst axi_gpio_0 -pg 1 -lvl 2 -x 500 -y 230 -defaultsOSRD
preplace inst axi_fifo_mm_s_0 -pg 1 -lvl 2 -x 500 -y 80 -defaultsOSRD
preplace inst axi_crossbar_0 -pg 1 -lvl 1 -x 170 -y 210 -defaultsOSRD
preplace inst axi_fifo_mm_s_0 -pg 1 -lvl 2 -x 500 -y 80 -defaultsOSRD
preplace inst axi_gpio_0 -pg 1 -lvl 2 -x 500 -y 230 -defaultsOSRD
preplace netloc gpio2_io_i_1 1 0 3 NJ 320 NJ 320 660
preplace netloc axi_aclk_1 1 0 2 30 130 320
preplace netloc axi_resetn_1 1 0 2 20 120 330
preplace netloc axi_aclk_1 1 0 2 30 130 310
preplace netloc axi_resetn_1 1 0 2 20 120 320
preplace netloc axi_gpio_0_gpio_io_o 1 2 1 NJ 220
preplace netloc axi_crossbar_0_M00_AXI 1 1 1 300 60n
preplace netloc axi_crossbar_0_M01_AXI 1 1 1 330 210n
preplace netloc Conn1 1 2 1 NJ 60
preplace netloc axi_crossbar_0_M01_AXI 1 1 1 340 210n
preplace netloc S00_AXI_1 1 0 1 NJ 190
preplace netloc axi_crossbar_0_M00_AXI 1 1 1 310 60n
levelinfo -pg 1 0 170 500 680
pagesize -pg 1 -db -bbox -sgen -150 0 850 520
pagesize -pg 1 -db -bbox -sgen -170 0 860 520
"
}
0

90
Firmware/Artix7_PCIe/dso_top_fpga_module_rev2_unsigned/dso_top.xpr
View File

@ -3,10 +3,10 @@
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="49" Path="C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top/dso_top.xpr">
<Project Version="7" Minor="49" Path="C:/Users/Aleksa/Documents/EEVengers/Firmware/Artix7_PCIe/dso_top/dso_top.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="6a2f1ab8195f4ae09b52cc5330fbfd9c"/>
<Option Name="Id" Val="7f4d46e2a432428bb28f287cc44be7dc"/>
<Option Name="Part" Val="xc7a35tcsg325-2"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@ -66,49 +66,49 @@
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/bd/design_1/design_1.bd"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/bd/design_1/design_1.bd"/>
<Attr Name="ImportTime" Val="1615001535"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
<Proxy FileSetName="design_1_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_1/design_1_util_ds_buf_0_1.xci">
<Proxy FileSetName="design_1_util_ds_buf_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci">
<Proxy FileSetName="design_1_mig_7series_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
<Proxy FileSetName="design_1_util_ds_buf_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci">
<Proxy FileSetName="design_1_axi_fifo_mm_s_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
<Proxy FileSetName="design_1_xdma_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_datamover_0_0/design_1_axi_datamover_0_0.xci">
<Proxy FileSetName="design_1_axi_datamover_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci">
<Proxy FileSetName="design_1_axi_gpio_0_1"/>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
<Proxy FileSetName="design_1_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
<Proxy FileSetName="design_1_xdma_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_1/design_1_util_ds_buf_0_1.xci">
<Proxy FileSetName="design_1_util_ds_buf_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
<Proxy FileSetName="design_1_util_ds_buf_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dwidth_converter_0_0/design_1_axi_dwidth_converter_0_0.xci">
<Proxy FileSetName="design_1_axi_dwidth_converter_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci">
<Proxy FileSetName="design_1_axi_gpio_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci">
<Proxy FileSetName="design_1_mig_7series_0_1"/>
</CompFileExtendedInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../EEVengers/Firmware/Spartan6_USB/dso_top/I2C_Transmit.v"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../Spartan6_USB/dso_top/I2C_Transmit.v"/>
<Attr Name="ImportTime" Val="1613141433"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -117,7 +117,7 @@
</File>
<File Path="$PSRCDIR/sources_1/imports/dso_top/SPI_Transmit.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../EEVengers/Firmware/Spartan6_USB/dso_top/SPI_Transmit.v"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../Spartan6_USB/dso_top/SPI_Transmit.v"/>
<Attr Name="ImportTime" Val="1613141433"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@ -126,7 +126,7 @@
</File>
<File Path="$PSRCDIR/sources_1/new/adc_to_datamover.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/new/adc_to_datamover.v"/>
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@ -135,7 +135,7 @@
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@ -144,7 +144,7 @@
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top_axixclk/dso_top_axixclk.srcs/sources_1/new/axixclk.v"/>
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@ -153,7 +153,7 @@
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/new/serdes.v"/>
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@ -162,7 +162,7 @@
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/new/serial_controller.v"/>
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@ -171,7 +171,7 @@
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@ -180,7 +180,7 @@
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/dso_top/dso_top.srcs/sources_1/new/dso_top.v"/>
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@ -189,7 +189,7 @@
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@ -197,7 +197,7 @@
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<Attr Name="ImportPath" Val="$PPRDIR/../dso_top_CSG325/dso_top_CSG325.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/mig_b.prj"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/Artix7_PCIe/dso_top_CSG325/dso_top_CSG325.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/mig_b.prj"/>
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@ -213,7 +213,7 @@
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/Blink/Blink.srcs/constrs_1/new/module_bitgen.xdc"/>
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@ -221,7 +221,7 @@
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<Attr Name="UsedIn" Val="synthesis"/>
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@ -229,7 +229,7 @@
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@ -259,9 +259,9 @@
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@ -323,7 +323,7 @@
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@ -332,7 +332,7 @@
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@ -347,7 +347,7 @@
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