Hw/aleksa/fpga module rev2 #240

Merged
AleksaBjelogrlic merged 10 commits from HW/Aleksa/FPGA_Module_Rev2 into master 2022-11-01 02:51:38 +00:00
33 changed files with 72223 additions and 68765 deletions
Showing only changes of commit 061e037e7c - Show all commits

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@ -33,7 +33,7 @@ FSMCodingStyle=eFMSDropDownList_OneProcess
FSMEncodingStyle=eFMSDropDownList_OneHot
IsProjectConflictPreventionWarningsEnabled=0
IsVirtualBomDocumentRemoved=0
OutputPath=Project Outputs for FPGA_Module
OutputPath=
LogFolderPath=
ManagedProjectGUID=FBDD5B7D-1FB1-4C39-A525-0E81901E11EE
VaultGUID=b03a642c-f334-40b3-b929-2941954f9f28
@ -273,7 +273,111 @@ ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=DWMBPBHF
DocumentUniqueId=NWUHWUCY
[GeneratedDocument1]
DocumentPath=Project Outputs for FPGA_Module\BOM\Bill of Materials-FPGA_Module_Panel.xlsx
DItemRevisionGUID=
[GeneratedDocument2]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.DRR
DItemRevisionGUID=
[GeneratedDocument3]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.EXTREP
DItemRevisionGUID=
[GeneratedDocument4]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G1
DItemRevisionGUID=
[GeneratedDocument5]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G2
DItemRevisionGUID=
[GeneratedDocument6]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G3
DItemRevisionGUID=
[GeneratedDocument7]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G4
DItemRevisionGUID=
[GeneratedDocument8]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GBL
DItemRevisionGUID=
[GeneratedDocument9]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GTL
DItemRevisionGUID=
[GeneratedDocument10]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.LDP
DItemRevisionGUID=
[GeneratedDocument11]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.RUL
DItemRevisionGUID=
[GeneratedDocument12]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.TXT
DItemRevisionGUID=
[GeneratedDocument13]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Board_Outline.gbr
DItemRevisionGUID=
[GeneratedDocument14]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Board Outline.gbr
DItemRevisionGUID=
[GeneratedDocument15]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Drawing.gbr
DItemRevisionGUID=
[GeneratedDocument16]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Drawing_1.gbr
DItemRevisionGUID=
[GeneratedDocument17]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Guide_1.gbr
DItemRevisionGUID=
[GeneratedDocument18]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drillguide.gbr
DItemRevisionGUID=
[GeneratedDocument19]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Fab_Notes.gbr
DItemRevisionGUID=
[GeneratedDocument20]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Bot.gbr
DItemRevisionGUID=
[GeneratedDocument21]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Top.gbr
DItemRevisionGUID=
[GeneratedDocument22]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Bot.gbr
DItemRevisionGUID=
[GeneratedDocument23]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Top.gbr
DItemRevisionGUID=
[GeneratedDocument24]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Bot.gbr
DItemRevisionGUID=
[GeneratedDocument25]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Top.gbr
DItemRevisionGUID=
[GeneratedDocument26]
DocumentPath=Project Outputs for FPGA_Module\Pick Place\Pick Place for FPGA_Module_Panel.txt
DItemRevisionGUID=
[Configuration1]
Name=Sources
@ -346,7 +450,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
SaveSettingsToOutJob=0
[Generic_EDE]
OutputDir=Project Outputs for FPGA_Module
OutputDir=
[OutputGroup1]
Name=Netlist Outputs

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@ -17,11 +17,11 @@ RevisionNamingSchemeGUID=
[OutputGroup1]
Name=Job1.OutJob
Description=
TargetOutputMedium=PDF
TargetOutputMedium=Folder Structure
VariantName=[No Variations]
VariantScope=1
CurrentConfigurationName=
TargetPrinter=Virtual Printer
TargetPrinter=Microsoft Print to PDF
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
OutputMedium1=Print Job
OutputMedium1_Type=Printer
@ -38,20 +38,20 @@ OutputName1=Gerber Files
OutputCategory1=Fabrication
OutputDocumentPath1=FPGA_Module_Panel.PcbDoc
OutputVariantName1=
OutputEnabled1=0
OutputEnabled1=1
OutputEnabled1_OutputMedium1=0
OutputEnabled1_OutputMedium2=0
OutputEnabled1_OutputMedium3=1
OutputEnabled1_OutputMedium4=0
OutputDefault1=0
Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|BoardID=NWUHWUCY|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=KeepLeadingAndTrailingZeroes|MaxApertureSize=2500000|MergePadAndRegion=False|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16777220~1,16777218~1,16777219~1,16777221~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908295~1|PlotBoardProfile=False|PlotBoardProfileFileName=FPGA_Module_Panel_Profile.gbr|PlotDrillDrawingLayerPair0_Backdrill=False|PlotDrillDrawingLayerPair0_Checked=True|PlotDrillDrawingLayerPair0_DrillType=Regular|PlotDrillDrawingLayerPair0_FileName=FPGA_Module_Panel_Drill_Drawing_1.gbr|PlotDrillDrawingLayerPair0_HighLayer=Bottom Layer|PlotDrillDrawingLayerPair0_LowLayer=Top Layer|PlotDrillGuideLayerPair0_Backdrill=False|PlotDrillGuideLayerPair0_Checked=True|PlotDrillGuideLayerPair0_DrillType=Regular|PlotDrillGuideLayerPair0_FileName=FPGA_Module_Panel_Drill_Guide_1.gbr|PlotDrillGuideLayerPair0_HighLayer=Bottom Layer|PlotDrillGuideLayerPair0_LowLayer=Top Layer|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|UserLayerName.Caption0=FPGA_Module_Panel_Paste_Bot.gbr|UserLayerName.Caption1=FPGA_Module_Panel_Paste_Top.gbr|UserLayerName.Caption10=FPGA_Module_Panel_Fab_Notes.gbr|UserLayerName.Caption11=FPGA_Module_Panel_Copper_Signal_3.gbr|UserLayerName.Caption12=FPGA_Module_Panel_Copper_Signal_Bot.gbr|UserLayerName.Caption13=FPGA_Module_Panel_Bottom_3D_Body.gbr|UserLayerName.Caption14=FPGA_Module_Panel_Copper_Signal_Top.gbr|UserLayerName.Caption15=FPGA_Module_Panel_Legend_Bot.gbr|UserLayerName.Caption16=FPGA_Module_Panel_Pads_Top.gbr|UserLayerName.Caption17=FPGA_Module_Panel_Top_3D_Body.gbr|UserLayerName.Caption18=FPGA_Module_Panel_Top_Assembly.gbr|UserLayerName.Caption19=FPGA_Module_Panel_Top_Component_Center.gbr|UserLayerName.Caption2=FPGA_Module_Panel_Legend_Top.gbr|UserLayerName.Caption20=FPGA_Module_Panel_Copper_Signal_1.gbr|UserLayerName.Caption21=FPGA_Module_Panel_Board_Outline.gbr|UserLayerName.Caption22=FPGA_Module_Panel_Copper_Signal_4.gbr|UserLayerName.Caption23=FPGA_Module_Panel_Bottom_Courtyard.gbr|UserLayerName.Caption24=FPGA_Module_Panel_Keep-out.gbr|UserLayerName.Caption3=FPGA_Module_Panel_Soldermask_Top.gbr|UserLayerName.Caption4=FPGA_Module_Panel_Bottom_Component_Center.gbr|UserLayerName.Caption5=FPGA_Module_Panel_Top_Courtyard.gbr|UserLayerName.Caption6=FPGA_Module_Panel_Pads_Bot.gbr|UserLayerName.Caption7=FPGA_Module_Panel_Copper_Signal_2.gbr|UserLayerName.Caption8=FPGA_Module_Panel_Bottom_Assembly.gbr|UserLayerName.Caption9=FPGA_Module_Panel_Soldermask_Bot.gbr|UserLayerName.Count=25|UserLayerName.Layer0=16973833|UserLayerName.Layer1=16973832|UserLayerName.Layer10=16908295|UserLayerName.Layer11=16777219|UserLayerName.Layer12=16842751|UserLayerName.Layer13=16908302|UserLayerName.Layer14=16777217|UserLayerName.Layer15=16973831|UserLayerName.Layer16=16973848|UserLayerName.Layer17=16908301|UserLayerName.Layer18=16908297|UserLayerName.Layer19=16908299|UserLayerName.Layer2=16973830|UserLayerName.Layer20=16777220|UserLayerName.Layer21=16908289|UserLayerName.Layer22=16777221|UserLayerName.Layer23=16908291|UserLayerName.Layer24=16973837|UserLayerName.Layer3=16973834|UserLayerName.Layer4=16908300|UserLayerName.Layer5=16908290|UserLayerName.Layer6=16973849|UserLayerName.Layer7=16777218|UserLayerName.Layer8=16908298|UserLayerName.Layer9=16973835|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
Configuration1_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|BoardID=NWUHWUCY|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=KeepLeadingAndTrailingZeroes|MaxApertureSize=2500000|MergePadAndRegion=False|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16777220~1,16777218~1,16777219~1,16777221~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908295~1|PlotBoardProfile=False|PlotBoardProfileFileName=FPGA_Module_Panel_Profile.gbr|PlotDrillDrawingLayerPair0_Backdrill=False|PlotDrillDrawingLayerPair0_Checked=True|PlotDrillDrawingLayerPair0_DrillType=Regular|PlotDrillDrawingLayerPair0_FileName=FPGA_Module_Panel_Drill_Drawing.gbr|PlotDrillDrawingLayerPair0_HighLayer=Bottom Layer|PlotDrillDrawingLayerPair0_LowLayer=Top Layer|PlotDrillGuideLayerPair0_Backdrill=False|PlotDrillGuideLayerPair0_Checked=True|PlotDrillGuideLayerPair0_DrillType=Regular|PlotDrillGuideLayerPair0_FileName=FPGA_Module_Panel_Drillguide.gbr|PlotDrillGuideLayerPair0_HighLayer=Bottom Layer|PlotDrillGuideLayerPair0_LowLayer=Top Layer|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|UserLayerName.Caption0=FPGA_Module_Panel_Paste_Bot.gbr|UserLayerName.Caption1=FPGA_Module_Panel_Paste_Top.gbr|UserLayerName.Caption10=FPGA_Module_Panel_Fab_Notes.gbr|UserLayerName.Caption11=FPGA_Module_Panel_Copper_Signal_3.gbr|UserLayerName.Caption12=FPGA_Module_Panel_Copper_Signal_Bot.gbr|UserLayerName.Caption13=FPGA_Module_Panel_Bottom_3D_Body.gbr|UserLayerName.Caption14=FPGA_Module_Panel_Copper_Signal_Top.gbr|UserLayerName.Caption15=FPGA_Module_Panel_Legend_Bot.gbr|UserLayerName.Caption16=FPGA_Module_Panel_Pads_Top.gbr|UserLayerName.Caption17=FPGA_Module_Panel_Top_3D_Body.gbr|UserLayerName.Caption18=FPGA_Module_Panel_Top_Assembly.gbr|UserLayerName.Caption19=FPGA_Module_Panel_Top_Component_Center.gbr|UserLayerName.Caption2=FPGA_Module_Panel_Legend_Top.gbr|UserLayerName.Caption20=FPGA_Module_Panel_Copper_Signal_1.gbr|UserLayerName.Caption21=FPGA_Module_Panel_Board Outline.gbr|UserLayerName.Caption22=FPGA_Module_Panel_Copper_Signal_4.gbr|UserLayerName.Caption23=FPGA_Module_Panel_Bottom_Courtyard.gbr|UserLayerName.Caption24=FPGA_Module_Panel_Keep-out.gbr|UserLayerName.Caption3=FPGA_Module_Panel_Soldermask_Top.gbr|UserLayerName.Caption4=FPGA_Module_Panel_Bottom_Component_Center.gbr|UserLayerName.Caption5=FPGA_Module_Panel_Top_Courtyard.gbr|UserLayerName.Caption6=FPGA_Module_Panel_Pads_Bot.gbr|UserLayerName.Caption7=FPGA_Module_Panel_Copper_Signal_2.gbr|UserLayerName.Caption8=FPGA_Module_Panel_Bottom_Assembly.gbr|UserLayerName.Caption9=FPGA_Module_Panel_Soldermask_Bot.gbr|UserLayerName.Count=25|UserLayerName.Layer0=16973833|UserLayerName.Layer1=16973832|UserLayerName.Layer10=16908295|UserLayerName.Layer11=16777219|UserLayerName.Layer12=16842751|UserLayerName.Layer13=16908302|UserLayerName.Layer14=16777217|UserLayerName.Layer15=16973831|UserLayerName.Layer16=16973848|UserLayerName.Layer17=16908301|UserLayerName.Layer18=16908297|UserLayerName.Layer19=16908299|UserLayerName.Layer2=16973830|UserLayerName.Layer20=16777220|UserLayerName.Layer21=16908289|UserLayerName.Layer22=16777221|UserLayerName.Layer23=16908291|UserLayerName.Layer24=16973837|UserLayerName.Layer3=16973834|UserLayerName.Layer4=16908300|UserLayerName.Layer5=16908290|UserLayerName.Layer6=16973849|UserLayerName.Layer7=16777218|UserLayerName.Layer8=16908298|UserLayerName.Layer9=16973835|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
OutputType2=NC Drill
OutputName2=NC Drill Files
OutputCategory2=Fabrication
OutputDocumentPath2=FPGA_Module_Panel.PcbDoc
OutputVariantName2=
OutputEnabled2=0
OutputEnabled2=1
OutputEnabled2_OutputMedium1=0
OutputEnabled2_OutputMedium2=0
OutputEnabled2_OutputMedium3=2
@ -62,9 +62,9 @@ Configuration2_Item1=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|Ge
OutputType3=Assembly
OutputName3=Assembly Drawings
OutputCategory3=Assembly
OutputDocumentPath3=FPGA_Module_Panel.PcbDoc
OutputDocumentPath3=FPGA_Module.PcbDoc
OutputVariantName3=
OutputEnabled3=1
OutputEnabled3=0
OutputEnabled3_OutputMedium1=0
OutputEnabled3_OutputMedium2=1
OutputEnabled3_OutputMedium3=0
@ -89,9 +89,9 @@ PcbPrintPreferences3=SubsititueFont_Default=True|SubsititueFont_Serif=True|Subsi
OutputType4=Pick Place
OutputName4=Generates pick and place files
OutputCategory4=Assembly
OutputDocumentPath4=FPGA_Module_Panel.PcbDoc
OutputDocumentPath4=FPGA_Module.PcbDoc
OutputVariantName4=
OutputEnabled4=0
OutputEnabled4=1
OutputEnabled4_OutputMedium1=0
OutputEnabled4_OutputMedium2=0
OutputEnabled4_OutputMedium3=3
@ -102,9 +102,9 @@ Configuration4_Item1=Record=PickPlaceView|Units=Imperial|GenerateCSVFormat=False
OutputType5=BOM_PartType
OutputName5=Bill of Materials
OutputCategory5=Report
OutputDocumentPath5=FPGA_Module_Panel.PcbDoc
OutputDocumentPath5=FPGA_Module.PcbDoc
OutputVariantName5=
OutputEnabled5=0
OutputEnabled5=1
OutputEnabled5_OutputMedium1=0
OutputEnabled5_OutputMedium2=0
OutputEnabled5_OutputMedium3=4

Note: AllSpice cannot diff pdf files. Rendering head (latest) version below.

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@ -0,0 +1,99 @@
Protel Design System Design Rule Check
PCB File : C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc
Date : 2022-10-23
Time : 9:52:01 PM
Processing Rule : Clearance Constraint (Gap=0.127mm) (InNet('PG_1V0')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (All),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (InComponent('U7')),(InComponent('U7'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (isVia),(IsPad or IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (isVia),(isPad and (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')or HasFootprint('GEN_R_0402')or HasFootprint('GEN_C_0402')or HasFootprint('MX_WSON8')))
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.127mm) (Max=0.213mm) (Preferred=0.127mm) ((InNetClass('DDR3 ADDR')) OR (InNetClass('DQ0')) OR (InNetClass('DQ1')) OR (InNetClass('DQ2')) OR (InNetClass('DQ3')))
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=0.254mm) (Preferred=0.127mm) (InNet('PG_1V0'))
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=3.2mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.098mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS1') or InNetClass('DQ1'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS0') or InNetClass('DQ0'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('DDR3_CLK') or InDifferentialPairClass('DQS0') or InDifferentialPairClass('DQS1') or InDifferentialPairClass('DQS2') or InDifferentialPairClass('DQS3'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS2') or InNetClass('DQ2'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps Target=DDR3_CLK_P_PP1) (InxSignalClass('xSignals_U1_U4,U5'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS3') or InNetClass('DQ3'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=1ps) (InDifferentialPairClass('PCIe'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('ADC LVDS'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('ADC LVDS'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (Disabled)(InNetClass('DDR3 ADDR'))
Rule Violations :0
Processing Rule : Vias Under SMD Constraint (Allowed=Not Allowed) ((HasFootprint('GEN_C_0201') OR HasFootprint('GEN_R_0201') OR HasFootprint('GEN_C_0402') OR HasFootprint('GEN_R_0402')))
Rule Violations :0
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (All),(All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:02

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@ -0,0 +1,392 @@
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</head>
<body onload=""><img ALT="Altium" src="
file://C:\Users\Public\Documents\Altium\AD21\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">2022-10-23</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">9:52:01 PM</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:02</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc" class="file"><acronym title="C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc">C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc</acronym></a></td>
</tr>
</table>
</td>
<td class="column2">
<table class="DRC_summary_header">
<tr>
<td class="DRC_summary_header_col1">Warnings:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
</table>
</td>
</table><a name="IDOX2JXHXMVCHGIV2ABXBN5DDILJ4AILYXUI2NHCEQ30N42GOM0HRI"><h2>Summary</h2></a><table>
<tr>
<th class="column1">Warnings</th>
<th class="column2">Count</th>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
</table><br><table>
<tr>
<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID04Q3XOHHUKUFDRP3CZPEABQRSLN3UWSPU0TVAPEPTWA0WBYZIQHG">Clearance Constraint (Gap=0.127mm) (InNet('PG_1V0')),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAJDV2DV0U34VJ1P0VIBI0BQ5JKH2HI4WLL3HEMBMW1VZL3IZD4MO">Clearance Constraint (Gap=0.1mm) (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID0L3RF4T2EJXPC3BJPQVQIXJ5NH0ZNF2VRMF4CPE3HKD4EFPW1G0K">Clearance Constraint (Gap=0.127mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDELOGURWARZ02LHCHWTEPFQOIHHPO3VZHNZTVWGHLNJNXMGCKEMHD">Clearance Constraint (Gap=0.127mm) (InComponent('U7')),(InComponent('U7'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDRTNS2ZU4JCNQHU1MAPCB00WBSF2OJU5QNJPQMWHNZGPXDWZQWQYH">Clearance Constraint (Gap=0.127mm) (isVia),(IsPad or IsVia)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#ID3XZ0INEIAHLSJIO5GAMJZOHFOBHV55VCQEUDZNHYNTE0QBCFUVPN">Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3')),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDMOD1STYOPPBTFXGSTMODK2HRFGWN0JS250AH22I2Q1BAR5ETGV3L">Clearance Constraint (Gap=0.1mm) (isVia),(isPad and (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')or HasFootprint('GEN_R_0402')or HasFootprint('GEN_C_0402')or HasFootprint('MX_WSON8')))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDPHOBJY12XZKKFRY5P0NUYBAFIFWFUHQHXDTAQ4PHDP5RUZEEKT1">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDIXJXWZANLA53H1GRE1AW2VKUNBLWIF53ELZQSUHHIG33FJFJIQIM">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDABTC2GOF3EVEB0KUQ33D3YG24O4O14NC2K2KIRJVI4S12NUVQ5RJ">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDGE0LLLDPN5ZTMFKTFY4NB4SLUF4ZQ3TCKBCZMLOWNJVDUNI4ENG">Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDXTPC0D1JSIPXCKAOG3IZ542SAFELZNMD3Z3JYDKUR31QNDXEGTFN">Width Constraint (Min=0.127mm) (Max=0.213mm) (Preferred=0.127mm) ((InNetClass('DDR3 ADDR')) OR (InNetClass('DQ0')) OR (InNetClass('DQ1')) OR (InNetClass('DQ2')) OR (InNetClass('DQ3')))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDJN3BHLPKCCUGHHL30VBD1WNAFFIRRNCFASRO5HJ4ZZWLXEPVCM1K">Width Constraint (Min=0.1mm) (Max=0.254mm) (Preferred=0.127mm) (InNet('PG_1V0'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#ID5CJTEN13WT1BH1QK3SYWNIY24EGOIDWOERE0GCKAPUQSNE20J3XO">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID25O12RM433EM2NOG2H2ODVBYPHUAIA0JNCJTMDXVPLJJ5SLVAM">Hole Size Constraint (Min=0.025mm) (Max=3.2mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDRNMBNWJA4MUBK4GAVPISXFVHNCYJXVPB01KA44DDKVGNSIA3ZNAI">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDZZPFTX0TXEZEMDJSKECALIISQJGZQKP0QJO5ZDJ42IZK2FQMQYAC">Minimum Solder Mask Sliver (Gap=0.098mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDQDQJ1MFODH1JIAHMIEJXDGH54LFDZDJ2IZYCV1FSPY4GN2WDROSO">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS1') or InNetClass('DQ1'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDQERMAAEMEVWWPDSIR3UY0KIVYCG3LO2AV2SGLPJRMJK5O3IGE4X">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS0') or InNetClass('DQ0'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDLQJKLXHMCBLABUHMTSBKF0TRLGFRGMPD5CBCBQJPWEIBXB2HFQNI">Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('DDR3_CLK') or InDifferentialPairClass('DQS0') or InDifferentialPairClass('DQS1') or InDifferentialPairClass('DQS2') or InDifferentialPairClass('DQS3'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID0ITJGCCBL00VJOEIWDG0F45P2IAAVAAGOZYE1SDVIOI2G1MKQQKP">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS2') or InNetClass('DQ2'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDM0P4X0ZPALDICWPNFHYGC5X2DLFRBCTSSTF41RPKU4QRRSDG4QPK">Matched Lengths(Delay Tolerance=5ps Target=DDR3_CLK_P_PP1) (InxSignalClass('xSignals_U1_U4,U5'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDJGR5V0AIQSASPCFSD0VZ5OGIKOLY4NOAJ1EWZ3DXWLDKMXP5QOCM">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS3') or InNetClass('DQ3'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDMOX2BTR4VR3MIV5AIP3BU3LALG5WF1BCPFXE5RKRZZ3YH4XW5BPN">Matched Lengths(Delay Tolerance=1ps) (InDifferentialPairClass('PCIe'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDWWPHNRPD4W3FCZYZY41VDS3RVDKFSBOKET1PQMETYXG5LHBC4PRB">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('ADC LVDS'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#ID22LNWT4ROXNVPWRUHI5BWYVNIDZWBWIJT3KQYFK0G1DVTK5NO42J">Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('ADC LVDS'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDN55V0FWJTX3LBE3CNTRV3DBYXGS0DTHIYJCSIPKJWLXAPJ1P3H3B">Matched Lengths(Delay Tolerance=5ps) (Disabled)(InNetClass('DDR3 ADDR'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#ID1DHYC5EDLOZEIORPGLM1FMJL0PTVX4KL5Z0RQSDC4XIYTOACFMJB">Vias Under SMD Constraint (Allowed=Not Allowed) ((HasFootprint('GEN_C_0201') OR HasFootprint('GEN_R_0201') OR HasFootprint('GEN_C_0402') OR HasFootprint('GEN_R_0402')))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDE51WKMH5W2EXJPBSTNOZXRG1UI3OS2X0QUO5RXPKNHGJFWG20B0">Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (All),(All) </a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDARIDIBDDH010BCMOGGXBGBFJPLZ4EMB1DFDFQHL0WGU3QKZ12JTO">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
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View File

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------------------------------------------------------------------------------------------
Gerber File Extension Report For: FPGA_Module_Panel.GBR 2022-10-19 10:28:49 PM
Gerber File Extension Report For: FPGA_Module_Panel.GBR 2022-10-23 9:52:28 PM
------------------------------------------------------------------------------------------

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X031245Y012000D01*
X031197Y012020D01*
X031145D01*
X031098Y012000D01*
@ -1271,13 +1262,12 @@ X031061Y011816D01*
X031098Y011780D01*
X031145Y011760D01*
X031197D01*
X031214Y011767D01*
X031248Y011779D01*
X031289Y011767D01*
X031245Y011780D01*
X031249Y011784D01*
X031299Y011763D01*
Y011709D01*
X031257Y011682D01*
X031214Y011698D01*
Y011701D01*
X031249Y011681D01*
X031245Y011685D01*
X031197Y011705D01*
X031145D01*
X031098Y011685D01*
@ -1288,13 +1278,12 @@ X031061Y011501D01*
X031098Y011465D01*
X031145Y011445D01*
X031197D01*
X031214Y011452D01*
X031248Y011464D01*
X031289Y011452D01*
X031245Y011465D01*
X031249Y011469D01*
X031299Y011448D01*
Y011374D01*
X031257Y011348D01*
X031214Y011363D01*
Y011367D01*
X031249Y011346D01*
X031245Y011350D01*
X031197Y011370D01*
X031145D01*
X031098Y011350D01*
@ -1313,14 +1302,12 @@ X031071Y010871D01*
X031107Y010835D01*
X031155Y010815D01*
X031207D01*
X031255Y010835D01*
X031296Y010809D01*
X031298Y010808D01*
X031299Y010803D01*
Y010421D01*
X031298Y010416D01*
X031294Y010413D01*
X031255Y010389D01*
X031249Y010832D01*
X031275Y010823D01*
X031299Y010808D01*
Y010415D01*
X031275Y010401D01*
X031249Y010391D01*
X031207Y010409D01*
X031155D01*
X031107Y010389D01*
@ -1335,15 +1322,9 @@ X030785Y010389D01*
X030766Y010341D01*
Y010289D01*
X030785Y010241D01*
X030788Y010239D01*
X030793Y010228D01*
X030783Y010187D01*
X030800Y010227D01*
X030779Y010177D01*
X030503D01*
X030497Y010180D01*
X030493D01*
X030489Y010182D01*
X030483Y010184D01*
X030492D01*
X030346Y010284D01*
X030356Y010309D01*
Y010361D01*
@ -1677,18 +1658,14 @@ X027021Y019908D01*
X027043Y019941D01*
X027051Y019980D01*
Y020817D01*
X031288D01*
X031299Y020812D01*
X031299D01*
Y019833D01*
D02*
G37*
G36*
X014764D02*
Y019833D01*
Y019618D01*
X014763Y019617D01*
X014762Y019612D01*
X014758Y019608D01*
X014752Y019593D01*
Y019611D01*
X014714Y019578D01*
X014711Y019579D01*
X014659D01*
X014611Y019559D01*
@ -1705,15 +1682,12 @@ Y019187D01*
X014575Y019139D01*
X014611Y019102D01*
X014659Y019083D01*
X014706D01*
X014716Y019079D01*
X014758Y019053D01*
X014762Y019049D01*
X014763Y019044D01*
X014764Y019043D01*
Y017987D01*
X014722Y017960D01*
X014678Y017974D01*
X014711D01*
X014714Y019084D01*
X014764Y019050D01*
Y017979D01*
X014714Y017959D01*
X014713Y017959D01*
X014669Y017977D01*
X014622D01*
X014578Y017959D01*
@ -1724,10 +1698,10 @@ X014544Y017790D01*
X014578Y017757D01*
X014622Y017739D01*
X014669D01*
X014678Y017742D01*
X014717Y017754D01*
X014746Y017738D01*
X014747Y017685D01*
X014713Y017757D01*
X014714Y017757D01*
X014761Y017738D01*
Y017690D01*
X014736Y017680D01*
X014702Y017646D01*
X014684Y017602D01*
@ -1735,9 +1709,8 @@ Y017555D01*
X014702Y017511D01*
X014736Y017478D01*
X014764Y017466D01*
Y013634D01*
X014735Y013593D01*
X014702Y013592D01*
Y013612D01*
X014734Y013592D01*
X014683D01*
X014635Y013572D01*
X014598Y013536D01*
@ -1746,7 +1719,9 @@ Y013436D01*
X014598Y013388D01*
X014635Y013352D01*
X014683Y013332D01*
X014689Y013302D01*
X014697D01*
X014739Y013290D01*
X014696Y013265D01*
X014672Y013275D01*
X014621D01*
X014573Y013255D01*
@ -1757,13 +1732,12 @@ X014536Y013071D01*
X014573Y013034D01*
X014621Y013015D01*
X014672D01*
X014681Y013018D01*
X014716Y013030D01*
X014747Y013016D01*
X014749Y013000D01*
X014744Y012963D01*
X014708Y012943D01*
X014679Y012954D01*
X014714Y013032D01*
X014741Y013021D01*
X014764Y013007D01*
Y012957D01*
X014714Y012936D01*
X014708Y012942D01*
X014660Y012962D01*
X014608D01*
X014560Y012942D01*
@ -1774,13 +1748,12 @@ X014524Y012759D01*
X014560Y012722D01*
X014608Y012702D01*
X014660D01*
X014679Y012710D01*
X014711Y012722D01*
X014754Y012712D01*
X014708Y012722D01*
X014714Y012728D01*
X014764Y012707D01*
Y012339D01*
X014722Y012312D01*
X014678Y012328D01*
Y012331D01*
X014714Y012311D01*
X014709Y012315D01*
X014662Y012335D01*
X014610D01*
X014562Y012315D01*
@ -1791,13 +1764,12 @@ X014526Y012131D01*
X014562Y012095D01*
X014610Y012075D01*
X014662D01*
X014678Y012082D01*
X014712Y012094D01*
X014754Y012082D01*
X014709Y012095D01*
X014714Y012099D01*
X014764Y012078D01*
Y012024D01*
X014722Y011997D01*
X014678Y012013D01*
Y012016D01*
X014714Y011996D01*
X014709Y012000D01*
X014662Y012020D01*
X014610D01*
X014562Y012000D01*
@ -1808,13 +1780,12 @@ X014526Y011816D01*
X014562Y011780D01*
X014610Y011760D01*
X014662D01*
X014678Y011767D01*
X014712Y011779D01*
X014754Y011767D01*
X014709Y011780D01*
X014714Y011784D01*
X014764Y011763D01*
Y011709D01*
X014722Y011682D01*
X014678Y011698D01*
Y011701D01*
X014714Y011681D01*
X014709Y011685D01*
X014662Y011705D01*
X014610D01*
X014562Y011685D01*
@ -1825,13 +1796,12 @@ X014526Y011501D01*
X014562Y011465D01*
X014610Y011445D01*
X014662D01*
X014678Y011452D01*
X014712Y011464D01*
X014754Y011452D01*
X014709Y011465D01*
X014714Y011469D01*
X014764Y011448D01*
Y011374D01*
X014722Y011348D01*
X014678Y011363D01*
Y011367D01*
X014714Y011346D01*
X014709Y011350D01*
X014662Y011370D01*
X014610D01*
X014562Y011350D01*
@ -1850,14 +1820,12 @@ X014535Y010871D01*
X014572Y010835D01*
X014620Y010815D01*
X014672D01*
X014719Y010835D01*
X014761Y010809D01*
X014763Y010808D01*
X014764Y010803D01*
Y010421D01*
X014763Y010416D01*
X014759Y010413D01*
X014719Y010389D01*
X014714Y010832D01*
X014739Y010823D01*
X014764Y010808D01*
Y010415D01*
X014739Y010401D01*
X014714Y010391D01*
X014672Y010409D01*
X014620D01*
X014572Y010389D01*
@ -1872,15 +1840,9 @@ X014250Y010389D01*
X014230Y010341D01*
Y010289D01*
X014250Y010241D01*
X014252Y010239D01*
X014258Y010228D01*
X014248Y010187D01*
X014264Y010227D01*
X014243Y010177D01*
X013967D01*
X013962Y010180D01*
X013957D01*
X013954Y010182D01*
X013948Y010184D01*
X013811Y010284D01*
X013821Y010309D01*
Y010361D01*
@ -2214,8 +2176,8 @@ X010485Y019908D01*
X010508Y019941D01*
X010515Y019980D01*
Y020817D01*
X014753D01*
X014764Y020812D01*
X014764D01*
Y019833D01*
D02*
G37*
G36*
@ -10126,8 +10088,7 @@ X028131Y017739D01*
X028094Y017775D01*
X028046Y017795D01*
X027995D01*
X027947Y017775D01*
X027941Y017776D01*
X027989Y017793D01*
X027931Y017802D01*
X027894Y017839D01*
X027846Y017859D01*
@ -12677,8 +12638,7 @@ X011595Y017739D01*
X011559Y017775D01*
X011511Y017795D01*
X011459D01*
X011411Y017775D01*
X011406Y017776D01*
X011453Y017793D01*
X011395Y017802D01*
X011359Y017839D01*
X011311Y017859D01*
@ -15278,27 +15238,7 @@ X032319Y005404D01*
D02*
G37*
G36*
X033097Y004461D02*
X033045D01*
X032997Y004441D01*
X032961Y004404D01*
X032941Y004357D01*
Y004305D01*
X032961Y004257D01*
X032997Y004220D01*
X033045Y004201D01*
X033097D01*
X033145Y004220D01*
X033181Y004257D01*
X033201Y004305D01*
Y004357D01*
X033181Y004404D01*
X033145Y004441D01*
X033097Y004461D01*
D02*
G37*
G36*
X032309D02*
X032309Y004461D02*
X032258D01*
X032210Y004441D01*
X032173Y004404D01*
@ -16772,27 +16712,7 @@ X015784Y005404D01*
D02*
G37*
G36*
X016561Y004461D02*
X016510D01*
X016462Y004441D01*
X016425Y004404D01*
X016405Y004357D01*
Y004305D01*
X016425Y004257D01*
X016462Y004220D01*
X016510Y004201D01*
X016561D01*
X016609Y004220D01*
X016646Y004257D01*
X016665Y004305D01*
Y004357D01*
X016646Y004404D01*
X016609Y004441D01*
X016561Y004461D01*
D02*
G37*
G36*
X015774D02*
X015774Y004461D02*
X015722D01*
X015674Y004441D01*
X015638Y004404D01*

View File

@ -7,7 +7,7 @@ G04 Layer_Color=16737945*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,CBA5B0EC-3C9A-411B-936C-A00E84A017FD*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
@ -16628,9 +16628,7 @@ X019291Y012599D02*
D03*
X019291Y011811D02*
D03*
X016535Y004331D02*
D03*
X015748D02*
X015748Y004331D02*
D03*
X014961D02*
D03*
@ -17044,9 +17042,7 @@ X035827Y012599D02*
D03*
X035827Y011811D02*
D03*
X033071Y004331D02*
D03*
X032283D02*
X032283Y004331D02*
D03*
X031496D02*
D03*

View File

@ -7,7 +7,7 @@ G04 Layer_Color=16711680*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,CBA5B0EC-3C9A-411B-936C-A00E84A017FD*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
@ -446,9 +446,8 @@ X030080Y006581D01*
X030049Y006587D01*
X029990D01*
X029959Y006581D01*
X029958Y006580D01*
X029921Y006567D01*
X029884Y006580D01*
X029933Y006563D01*
X029910D01*
X029883Y006581D01*
X029852Y006587D01*
X029793D01*
@ -585,9 +584,8 @@ X013545Y006581D01*
X013514Y006587D01*
X013455D01*
X013424Y006581D01*
X013423Y006580D01*
X013386Y006567D01*
X013349Y006580D01*
X013397Y006563D01*
X013374D01*
X013348Y006581D01*
X013317Y006587D01*
X013258D01*
@ -826,7 +824,7 @@ X030355Y007027D01*
X030414Y007067D01*
X030453Y007125D01*
X030467Y007195D01*
Y007400D01*
Y007401D01*
X030517Y007416D01*
X030531Y007395D01*
X030568Y007370D01*
@ -890,7 +888,7 @@ X013819Y007027D01*
X013878Y007067D01*
X013918Y007125D01*
X013931Y007195D01*
Y007400D01*
Y007401D01*
X013981Y007416D01*
X013995Y007395D01*
X014033Y007370D01*
@ -933,13 +931,15 @@ D02*
G37*
%LPD*%
D10*
X037402Y003150D02*
X037795Y005906D02*
D03*
X001969Y025591D02*
X001969Y022835D02*
D03*
X001969Y001969D02*
D03*
X038189Y025591D02*
X031102Y025197D02*
D03*
X018898Y006693D02*
D03*
X008110Y011663D02*
D03*
@ -949,6 +949,8 @@ X014567Y015354D02*
D03*
X008661Y020079D02*
D03*
X035433Y006693D02*
D03*
X024646Y011663D02*
D03*
X023228Y005906D02*
@ -11361,9 +11363,7 @@ X019291Y012599D02*
D03*
X019291Y011811D02*
D03*
X016535Y004331D02*
D03*
X015748D02*
X015748Y004331D02*
D03*
X014961D02*
D03*
@ -12639,9 +12639,7 @@ X035827Y012599D02*
D03*
X035827Y011811D02*
D03*
X033071Y004331D02*
D03*
X032283D02*
X032283Y004331D02*
D03*
X031496D02*
D03*

View File

@ -7,7 +7,7 @@ G04 Layer_Color=255*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,CBA5B0EC-3C9A-411B-936C-A00E84A017FD*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
@ -1662,7 +1662,9 @@ G36*
X034921Y007500D02*
X034620Y007199D01*
X034517Y007302D01*
X034517Y007302D01*
X034478Y007318D01*
X034472Y007315D01*
X034440Y007302D01*
X034381Y007243D01*
X034379Y007238D01*
@ -1685,7 +1687,9 @@ G36*
X018386D02*
X018085Y007199D01*
X017981Y007302D01*
X017981Y007302D01*
X017943Y007318D01*
X017937Y007315D01*
X017905Y007302D01*
X017845Y007243D01*
X017843Y007238D01*
@ -1816,7 +1820,7 @@ X017477Y006145D01*
X017329Y005972D01*
X017281Y005895D01*
X017231Y005889D01*
X017095Y006026D01*
X017094Y006026D01*
X017073Y006058D01*
X016996Y006135D01*
X016964Y006157D01*
@ -2073,14 +2077,18 @@ D02*
G37*
%LPD*%
D10*
X037402Y003150D02*
X037795Y005906D02*
D03*
X001969Y025591D02*
X001969Y022835D02*
D03*
X038189D02*
X031102Y025197D02*
D03*
X001969Y001969D02*
D03*
X016535Y004724D02*
D03*
X015354Y015354D02*
D03*
X014498Y014370D02*
D03*
X013711D02*
@ -2093,7 +2101,9 @@ X008268Y006693D02*
D03*
Y019685D02*
D03*
X015354Y015354D02*
X033071Y004724D02*
D03*
X031890Y015354D02*
D03*
X031033Y014370D02*
D03*
@ -2107,8 +2117,6 @@ X024803Y006693D02*
D03*
Y019685D02*
D03*
X031890Y015354D02*
D03*
D11*
X008592Y011262D02*
G03*
@ -16097,9 +16105,7 @@ X019291Y012599D02*
D03*
X019291Y011811D02*
D03*
X016535Y004331D02*
D03*
X015748D02*
X015748Y004331D02*
D03*
X014961D02*
D03*
@ -17375,9 +17381,7 @@ X035827Y012599D02*
D03*
X035827Y011811D02*
D03*
X033071Y004331D02*
D03*
X032283D02*
X032283Y004331D02*
D03*
X031496D02*
D03*

View File

@ -182,7 +182,7 @@ Used DCodes :
*************************************************************
Generating : Mechanical 1
File : FPGA_Module_Panel_Board_Outline.gbr
File : FPGA_Module_Panel_Board Outline.gbr
Adding Layer : Mechanical 1
@ -204,7 +204,7 @@ Used DCodes :
*************************************************************
Generating : Drill Drawing
File : FPGA_Module_Panel_Drill_Drawing_1.gbr
File : FPGA_Module_Panel_Drill_Drawing.gbr
Adding Drill Pair : Top Layer-Bottom Layer
@ -219,7 +219,7 @@ Used DCodes :
*************************************************************
Generating : Drill Guide
File : FPGA_Module_Panel_Drill_Guide_1.gbr
File : FPGA_Module_Panel_Drillguide.gbr
Adding Drill Pair : Top Layer-Bottom Layer

View File

@ -6,7 +6,7 @@ G04 Layer_Color=128*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,CBA5B0EC-3C9A-411B-936C-A00E84A017FD*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
@ -223,10 +223,6 @@ X019251Y011811D02*
X019331D01*
X019291Y011771D02*
Y011851D01*
X016495Y004331D02*
X016575D01*
X016535Y004291D02*
Y004371D01*
X015708Y004331D02*
X015788D01*
X015748Y004291D02*
@ -2843,10 +2839,6 @@ X035787Y011811D02*
X035867D01*
X035827Y011771D02*
Y011851D01*
X033031Y004331D02*
X033111D01*
X033071Y004291D02*
Y004371D01*
X032243Y004331D02*
X032323D01*
X032283Y004291D02*

View File

@ -6,7 +6,7 @@ G04 Layer_Color=128*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,CBA5B0EC-3C9A-411B-936C-A00E84A017FD*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*

Some files were not shown because too many files have changed in this diff Show More