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Hw/aleksa/fpga module rev2 #240

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AleksaBjelogrlic merged 10 commits from HW/Aleksa/FPGA_Module_Rev2 into master 2022-11-01 02:51:38 +00:00
Conversation 0 Commits 10 Files Changed 41 +2 -126
4 changed files with 2 additions and 126 deletions
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Hardware/The Next Generation/DSO.PcbLib
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Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.PcbDoc
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126
Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.PrjPcb
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@ -259,137 +259,13 @@ GenerateClassCluster=0
DocumentUniqueId= DocumentUniqueId=
[GeneratedDocument1] [GeneratedDocument1]
DocumentPath=Project Outputs for FPGA_Module\Design Rule Check - FPGA_Module.html
DItemRevisionGUID=
[GeneratedDocument2]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.DRR DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.DRR
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument3] [GeneratedDocument2]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.EXTREP
DItemRevisionGUID=
[GeneratedDocument4]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G1
DItemRevisionGUID=
[GeneratedDocument5]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G2
DItemRevisionGUID=
[GeneratedDocument6]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G3
DItemRevisionGUID=
[GeneratedDocument7]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G4
DItemRevisionGUID=
[GeneratedDocument8]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBL
DItemRevisionGUID=
[GeneratedDocument9]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBO
DItemRevisionGUID=
[GeneratedDocument10]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBP
DItemRevisionGUID=
[GeneratedDocument11]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBS
DItemRevisionGUID=
[GeneratedDocument12]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GM1
DItemRevisionGUID=
[GeneratedDocument13]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTL
DItemRevisionGUID=
[GeneratedDocument14]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTO
DItemRevisionGUID=
[GeneratedDocument15]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTP
DItemRevisionGUID=
[GeneratedDocument16]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTS
DItemRevisionGUID=
[GeneratedDocument17]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.LDP DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.LDP
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument18]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.REP
DItemRevisionGUID=
[GeneratedDocument19]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.RUL
DItemRevisionGUID=
[GeneratedDocument20]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_1.gbr
DItemRevisionGUID=
[GeneratedDocument21]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_2.gbr
DItemRevisionGUID=
[GeneratedDocument22]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_3.gbr
DItemRevisionGUID=
[GeneratedDocument23]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_4.gbr
DItemRevisionGUID=
[GeneratedDocument24]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_Bot.gbr
DItemRevisionGUID=
[GeneratedDocument25]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_Top.gbr
DItemRevisionGUID=
[GeneratedDocument26]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Drawing_1.gbr
DItemRevisionGUID=
[GeneratedDocument27]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Legend_Bot.gbr
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[GeneratedDocument28]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Legend_Top.gbr
DItemRevisionGUID=
[GeneratedDocument29]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Mechanical_1.gbr
DItemRevisionGUID=
[GeneratedDocument30]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Paste_Bot.gbr
DItemRevisionGUID=
[GeneratedDocument31]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Paste_Top.gbr
DItemRevisionGUID=
[GeneratedDocument32]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Soldermask_Bot.gbr
DItemRevisionGUID=
[GeneratedDocument33]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Soldermask_Top.gbr
DItemRevisionGUID=
[Configuration1] [Configuration1]
Name=Sources Name=Sources
ParameterCount=0 ParameterCount=0

2
Hardware/The Next Generation/FPGA_Module_Rev2/Job1.OutJob
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@ -45,7 +45,7 @@ OutputEnabled1_OutputMedium3=1
OutputEnabled1_OutputMedium4=0 OutputEnabled1_OutputMedium4=0
OutputDefault1=0 OutputDefault1=0
Configuration1_Name1=OutputConfigurationParameter1 Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|BoardID=DWMBPBHF|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=KeepLeadingAndTrailingZeroes|MaxApertureSize=2500000|MergePadAndRegion=False|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16777220~1,16777218~1,16777219~1,16777221~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908295~1|PlotBoardProfile=False|PlotBoardProfileFileName=FPGA_Module.GM|PlotDrillDrawingLayerPair0_Backdrill=False|PlotDrillDrawingLayerPair0_Checked=True|PlotDrillDrawingLayerPair0_DrillType=Regular|PlotDrillDrawingLayerPair0_FileName=FPGA_Module.GD1|PlotDrillDrawingLayerPair0_HighLayer=Bottom Layer|PlotDrillDrawingLayerPair0_LowLayer=Top Layer|PlotDrillGuideLayerPair0_Backdrill=False|PlotDrillGuideLayerPair0_Checked=False|PlotDrillGuideLayerPair0_DrillType=Regular|PlotDrillGuideLayerPair0_FileName=FPGA_Module.GG1|PlotDrillGuideLayerPair0_HighLayer=Bottom Layer|PlotDrillGuideLayerPair0_LowLayer=Top Layer|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|UserLayerName.Caption0=FPGA_Module.GBO|UserLayerName.Caption1=FPGA_Module.GTP|UserLayerName.Caption10=FPGA_Module.GBS|UserLayerName.Caption11=FPGA_Module.GM7|UserLayerName.Caption12=FPGA_Module.G2|UserLayerName.Caption13=FPGA_Module.G3|UserLayerName.Caption14=FPGA_Module.GBL|UserLayerName.Caption15=FPGA_Module.GM1|UserLayerName.Caption16=FPGA_Module.GM15|UserLayerName.Caption17=FPGA_Module.G4|UserLayerName.Caption18=FPGA_Module.GM3|UserLayerName.Caption19=FPGA_Module.GTL|UserLayerName.Caption2=FPGA_Module.GTO|UserLayerName.Caption20=FPGA_Module.GBP|UserLayerName.Caption3=FPGA_Module.GTS|UserLayerName.Caption4=FPGA_Module.GM13|UserLayerName.Caption5=FPGA_Module.GM2|UserLayerName.Caption6=FPGA_Module.GPT|UserLayerName.Caption7=FPGA_Module.GPB|UserLayerName.Caption8=FPGA_Module.GKO|UserLayerName.Caption9=FPGA_Module.G1|UserLayerName.Count=21|UserLayerName.Layer0=16973831|UserLayerName.Layer1=16973832|UserLayerName.Layer10=16973835|UserLayerName.Layer11=16908295|UserLayerName.Layer12=16777219|UserLayerName.Layer13=16777220|UserLayerName.Layer14=16842751|UserLayerName.Layer15=16908289|UserLayerName.Layer16=16908303|UserLayerName.Layer17=16777221|UserLayerName.Layer18=16908291|UserLayerName.Layer19=16777217|UserLayerName.Layer2=16973830|UserLayerName.Layer20=16973833|UserLayerName.Layer3=16973834|UserLayerName.Layer4=16908301|UserLayerName.Layer5=16908290|UserLayerName.Layer6=16973848|UserLayerName.Layer7=16973849|UserLayerName.Layer8=16973837|UserLayerName.Layer9=16777218|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc Configuration1_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|BoardID=DWMBPBHF|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=KeepLeadingAndTrailingZeroes|MaxApertureSize=2500000|MergePadAndRegion=False|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16777220~1,16777218~1,16777219~1,16777221~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908295~1|PlotBoardProfile=False|PlotBoardProfileFileName=FPGA_Module_Profile.gbr|PlotDrillDrawingLayerPair0_Backdrill=False|PlotDrillDrawingLayerPair0_Checked=True|PlotDrillDrawingLayerPair0_DrillType=Regular|PlotDrillDrawingLayerPair0_FileName=FPGA_Module_Drawing_1.gbr|PlotDrillDrawingLayerPair0_HighLayer=Bottom Layer|PlotDrillDrawingLayerPair0_LowLayer=Top Layer|PlotDrillGuideLayerPair0_Backdrill=False|PlotDrillGuideLayerPair0_Checked=False|PlotDrillGuideLayerPair0_DrillType=Regular|PlotDrillGuideLayerPair0_FileName=FPGA_Module_Drillmap_1.gbr|PlotDrillGuideLayerPair0_HighLayer=Bottom Layer|PlotDrillGuideLayerPair0_LowLayer=Top Layer|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|UserLayerName.Caption0=FPGA_Module_Legend_Bot.gbr|UserLayerName.Caption1=FPGA_Module_Paste_Top.gbr|UserLayerName.Caption10=FPGA_Module_Soldermask_Bot.gbr|UserLayerName.Caption11=FPGA_Module_Mechanical_7.gbr|UserLayerName.Caption12=FPGA_Module_Copper_Signal_3.gbr|UserLayerName.Caption13=FPGA_Module_Copper_Signal_1.gbr|UserLayerName.Caption14=FPGA_Module_Copper_Signal_Bot.gbr|UserLayerName.Caption15=FPGA_Module_Mechanical_1.gbr|UserLayerName.Caption16=FPGA_Module_Mechanical_15.gbr|UserLayerName.Caption17=FPGA_Module_Copper_Signal_4.gbr|UserLayerName.Caption18=FPGA_Module_Bottom_Courtyard.gbr|UserLayerName.Caption19=FPGA_Module_Copper_Signal_Top.gbr|UserLayerName.Caption2=FPGA_Module_Legend_Top.gbr|UserLayerName.Caption20=FPGA_Module_Paste_Bot.gbr|UserLayerName.Caption3=FPGA_Module_Soldermask_Top.gbr|UserLayerName.Caption4=FPGA_Module_Mechanical_13.gbr|UserLayerName.Caption5=FPGA_Module_Top_Courtyard.gbr|UserLayerName.Caption6=FPGA_Module_Pads_Top.gbr|UserLayerName.Caption7=FPGA_Module_Pads_Bot.gbr|UserLayerName.Caption8=FPGA_Module_Keep-out.gbr|UserLayerName.Caption9=FPGA_Module_Copper_Signal_2.gbr|UserLayerName.Count=21|UserLayerName.Layer0=16973831|UserLayerName.Layer1=16973832|UserLayerName.Layer10=16973835|UserLayerName.Layer11=16908295|UserLayerName.Layer12=16777219|UserLayerName.Layer13=16777220|UserLayerName.Layer14=16842751|UserLayerName.Layer15=16908289|UserLayerName.Layer16=16908303|UserLayerName.Layer17=16777221|UserLayerName.Layer18=16908291|UserLayerName.Layer19=16777217|UserLayerName.Layer2=16973830|UserLayerName.Layer20=16973833|UserLayerName.Layer3=16973834|UserLayerName.Layer4=16908301|UserLayerName.Layer5=16908290|UserLayerName.Layer6=16973848|UserLayerName.Layer7=16973849|UserLayerName.Layer8=16973837|UserLayerName.Layer9=16777218|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc
OutputType2=NC Drill OutputType2=NC Drill
OutputName2=NC Drill Files OutputName2=NC Drill Files
OutputCategory2=Fabrication OutputCategory2=Fabrication