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Hw/aleksa/fpga module rev2 #240

Merged
AleksaBjelogrlic merged 10 commits from HW/Aleksa/FPGA_Module_Rev2 into master 2022-11-01 02:51:38 +00:00
Conversation 0 Commits 10 Files Changed 41 +49950 -49932
24 changed files with 49950 additions and 49932 deletions
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Showing only changes of commit 19786ae2d5 - Show all commits

70
Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.PrjPcb
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@ -33,7 +33,7 @@ FSMCodingStyle=eFMSDropDownList_OneProcess
FSMEncodingStyle=eFMSDropDownList_OneHot FSMEncodingStyle=eFMSDropDownList_OneHot
IsProjectConflictPreventionWarningsEnabled=0 IsProjectConflictPreventionWarningsEnabled=0
IsVirtualBomDocumentRemoved=0 IsVirtualBomDocumentRemoved=0
OutputPath= OutputPath=Project Outputs for FPGA_Module
LogFolderPath= LogFolderPath=
ManagedProjectGUID=FBDD5B7D-1FB1-4C39-A525-0E81901E11EE ManagedProjectGUID=FBDD5B7D-1FB1-4C39-A525-0E81901E11EE
VaultGUID=b03a642c-f334-40b3-b929-2941954f9f28 VaultGUID=b03a642c-f334-40b3-b929-2941954f9f28
@ -276,106 +276,122 @@ GenerateClassCluster=0
DocumentUniqueId=NWUHWUCY DocumentUniqueId=NWUHWUCY
[GeneratedDocument1] [GeneratedDocument1]
DocumentPath=Project Outputs for FPGA_Module\BOM\Bill of Materials-FPGA_Module_Panel.xlsx DocumentPath=Project Outputs for FPGA_Module\BOM\Bill of Materials-FPGA_Module.xlsx
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument2] [GeneratedDocument2]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.DRR DocumentPath=Project Outputs for FPGA_Module\BOM\Bill of Materials-FPGA_Module_Panel.xlsx
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument3] [GeneratedDocument3]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.EXTREP DocumentPath=Project Outputs for FPGA_Module\Design Rule Check - FPGA_Module.html
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument4] [GeneratedDocument4]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G1 DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.DRR
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument5] [GeneratedDocument5]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G2 DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.EXTREP
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument6] [GeneratedDocument6]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G3 DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G1
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument7] [GeneratedDocument7]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G4 DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G2
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument8] [GeneratedDocument8]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GBL DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G3
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument9] [GeneratedDocument9]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GTL DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G4
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument10] [GeneratedDocument10]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.LDP DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GBL
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument11] [GeneratedDocument11]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.RUL DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GTL
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument12] [GeneratedDocument12]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.TXT DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.LDP
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument13] [GeneratedDocument13]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Board_Outline.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.REP
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument14] [GeneratedDocument14]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Board Outline.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.RUL
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument15] [GeneratedDocument15]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Drawing.gbr DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.TXT
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument16] [GeneratedDocument16]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Drawing_1.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Board_Outline.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument17] [GeneratedDocument17]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Guide_1.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Board Outline.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument18] [GeneratedDocument18]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drillguide.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Drawing.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument19] [GeneratedDocument19]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Fab_Notes.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Drawing_1.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument20] [GeneratedDocument20]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Bot.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Guide_1.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument21] [GeneratedDocument21]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Top.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drillguide.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument22] [GeneratedDocument22]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Bot.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Fab_Notes.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument23] [GeneratedDocument23]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Top.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Bot.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument24] [GeneratedDocument24]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Bot.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Top.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument25] [GeneratedDocument25]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Top.gbr DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Bot.gbr
DItemRevisionGUID= DItemRevisionGUID=
[GeneratedDocument26] [GeneratedDocument26]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Top.gbr
DItemRevisionGUID=
[GeneratedDocument27]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Bot.gbr
DItemRevisionGUID=
[GeneratedDocument28]
DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Top.gbr
DItemRevisionGUID=
[GeneratedDocument29]
DocumentPath=Project Outputs for FPGA_Module\Pick Place\Pick Place for FPGA_Module.txt
DItemRevisionGUID=
[GeneratedDocument30]
DocumentPath=Project Outputs for FPGA_Module\Pick Place\Pick Place for FPGA_Module_Panel.txt DocumentPath=Project Outputs for FPGA_Module\Pick Place\Pick Place for FPGA_Module_Panel.txt
DItemRevisionGUID= DItemRevisionGUID=
@ -450,7 +466,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
SaveSettingsToOutJob=0 SaveSettingsToOutJob=0
[Generic_EDE] [Generic_EDE]
OutputDir= OutputDir=Project Outputs for FPGA_Module
[OutputGroup1] [OutputGroup1]
Name=Netlist Outputs Name=Netlist Outputs

Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module_Panel.PcbDoc
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LOADING

6
Hardware/The Next Generation/FPGA_Module_Rev2/Job1.OutJob
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@ -114,13 +114,15 @@ PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintS
Configuration5_Name1=ColumnNameFormat Configuration5_Name1=ColumnNameFormat
Configuration5_Item1=CaptionAsName Configuration5_Item1=CaptionAsName
Configuration5_Name2=General Configuration5_Name2=General
Configuration5_Item2=OpenExported=False|AddToProject=False|ReportBOMViolationsInMessages=False|ForceFit=False|NotFitted=False|Database=False|DatabasePriority=False|IncludePcbData=False|IncludeVaultData=False|IncludeCloudData=False|IncludeDocumentData=True|IncludeAlternatives=False|ShowExportOptions=True|TemplateFilename=|TemplateVaultGuid=|TemplateItemGuid=|TemplateRevisionGuid=|BatchMode=5|FormWidth=1200|FormHeight=710|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=USD|SolutionsPerItem=1|SuppliersPerSolution=1|ViewType=0|UseDirectApi=False|BomSetName= Configuration5_Item2=OpenExported=False|AddToProject=False|ReportBOMViolationsInMessages=False|ForceFit=False|NotFitted=False|Database=False|DatabasePriority=False|IncludePcbData=False|IncludeVaultData=False|IncludeCloudData=False|IncludeDocumentData=True|IncludeAlternatives=False|ShowExportOptions=True|TemplateFilename=|TemplateVaultGuid=|TemplateItemGuid=|TemplateRevisionGuid=|BatchMode=5|FormWidth=1913|FormHeight=710|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=USD|SolutionsPerItem=1|SuppliersPerSolution=1|ViewType=0|UseDirectApi=False|BomSetName=
Configuration5_Name3=GroupOrder Configuration5_Name3=GroupOrder
Configuration5_Item3=Comment=True|Footprint=True Configuration5_Item3=Comment=True|Footprint=True
Configuration5_Name4=SortOrder Configuration5_Name4=SortOrder
Configuration5_Item4=Designator=Up|Comment=Up|Footprint=Up Configuration5_Item4=Designator=Up|Comment=Up|Footprint=Up
Configuration5_Name5=VisibleOrder Configuration5_Name5=VisibleOrder
Configuration5_Item5=Comment=120|Description=120|Designator=120|Footprint=120|LibRef=120|Quantity=120 Configuration5_Item5=Comment=120|Designator=120|Footprint=120|LibRef=120|Quantity=120|Supplier Part Number 1=228
Configuration5_Name6=VisibleOrder_Flat
Configuration5_Item6=Comment=120|Designator=120|Footprint=120|LibRef=120|Quantity=120|Supplier Part Number 1=228
[PublishSettings] [PublishSettings]
OutputFilePath2=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Project Outputs for FPGA_Module\Job1.PDF OutputFilePath2=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Project Outputs for FPGA_Module\Job1.PDF

BIN
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/BOM/Bill of Materials-FPGA_Module.xlsx
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Binary file not shown.

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.EXTREP
View File

@ -1,5 +1,5 @@
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
Gerber File Extension Report For: FPGA_Module_Panel.GBR 2022-10-23 9:52:28 PM Gerber File Extension Report For: FPGA_Module_Panel.GBR 2022-10-23 10:05:51 PM
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G1
View File

@ -7,7 +7,7 @@ G04 Layer_Color=16777215*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G2
View File

@ -7,7 +7,7 @@ G04 Layer_Color=36540*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G3
View File

@ -7,7 +7,7 @@ G04 Layer_Color=10517442*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G4
View File

@ -7,7 +7,7 @@ G04 Layer_Color=16737945*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.GBL
View File

@ -7,7 +7,7 @@ G04 Layer_Color=16711680*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.GTL
View File

@ -7,7 +7,7 @@ G04 Layer_Color=255*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

4
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Board Outline.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=16711935*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*
@ -10176,7 +10176,7 @@ Y024409D01*
Y003150D02* Y003150D02*
X003937D01* X003937D01*
Y024409D01* Y024409D01*
X003150Y024803D02* X003150D02*
X003937D01* X003937D01*
X-000000Y027559D02* X-000000Y027559D02*
X000000Y000000D01* X000000Y000000D01*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Drill_Drawing.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=2752767*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Drillguide.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=128*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

99724
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Fab_Notes.gbr
View File

File diff suppressed because it is too large Load Diff

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Legend_Bot.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=32896*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

42
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Legend_Top.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=65535*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*
@ -8497,12 +8497,12 @@ X035891Y020663D01*
X035894Y020663D01* X035894Y020663D01*
X035899Y020662D01* X035899Y020662D01*
X035904Y020661D01* X035904Y020661D01*
X035910Y020660D01* X035910Y020661D01*
X035916Y020660D01* X035916Y020660D01*
X035916D01* X035916D01*
X035918D01* X035918D01*
X035919D01* X035919D01*
X035922Y020660D01* X035922Y020661D01*
X035925Y020661D01* X035925Y020661D01*
X035928Y020661D01* X035928Y020661D01*
X035932Y020661D01* X035932Y020661D01*
@ -8690,12 +8690,12 @@ X019355Y020663D01*
X019359Y020663D01* X019359Y020663D01*
X019363Y020662D01* X019363Y020662D01*
X019369Y020661D01* X019369Y020661D01*
X019374Y020660D01* X019374Y020661D01*
X019381Y020660D01* X019381Y020660D01*
X019381D01* X019381D01*
X019382D01* X019382D01*
X019384D01* X019384D01*
X019387Y020660D01* X019387Y020661D01*
X019390Y020661D01* X019390Y020661D01*
X019393Y020661D01* X019393Y020661D01*
X019397Y020661D01* X019397Y020661D01*
@ -9118,12 +9118,12 @@ X035770D01*
X035770Y020457D01* X035770Y020457D01*
X035769Y020456D01* X035769Y020456D01*
X035768Y020456D01* X035768Y020456D01*
X035764Y020455D01* X035764Y020456D01*
X035760Y020455D01* X035760Y020455D01*
X035760D01* X035760D01*
X035759D01* X035759D01*
X035758D01* X035758D01*
X035757Y020455D01* X035757Y020456D01*
X035753Y020456D01* X035753Y020456D01*
X035750Y020457D01* X035750Y020457D01*
X035750D01* X035750D01*
@ -9206,12 +9206,12 @@ X019235D01*
X019234Y020457D01* X019234Y020457D01*
X019233Y020456D01* X019233Y020456D01*
X019232Y020456D01* X019232Y020456D01*
X019229Y020455D01* X019229Y020456D01*
X019225Y020455D01* X019225Y020455D01*
X019225D01* X019225D01*
X019224D01* X019224D01*
X019223D01* X019223D01*
X019222Y020455D01* X019222Y020456D01*
X019218Y020456D01* X019218Y020456D01*
X019214Y020457D01* X019214Y020457D01*
X019214D01* X019214D01*
@ -9637,7 +9637,7 @@ X035677Y019972D01*
X035675Y019965D01* X035675Y019965D01*
Y019965D01* Y019965D01*
X035674Y019964D01* X035674Y019964D01*
X035674Y019963D01* X035674Y019964D01*
X035673Y019962D01* X035673Y019962D01*
X035672Y019959D01* X035672Y019959D01*
X035669Y019955D01* X035669Y019955D01*
@ -9835,7 +9835,7 @@ X019142Y019972D01*
X019139Y019965D01* X019139Y019965D01*
Y019965D01* Y019965D01*
X019139Y019964D01* X019139Y019964D01*
X019139Y019963D01* X019139Y019964D01*
X019138Y019962D01* X019138Y019962D01*
X019136Y019959D01* X019136Y019959D01*
X019134Y019955D01* X019134Y019955D01*
@ -10025,7 +10025,7 @@ X035521Y019847D01*
X035524Y019845D01* X035524Y019845D01*
X035528Y019843D01* X035528Y019843D01*
X035531Y019841D01* X035531Y019841D01*
X035531Y019840D01* X035531Y019841D01*
X035532Y019840D01* X035532Y019840D01*
X035534Y019838D01* X035534Y019838D01*
X035536Y019836D01* X035536Y019836D01*
@ -10141,7 +10141,7 @@ X018985Y019847D01*
X018989Y019845D01* X018989Y019845D01*
X018992Y019843D01* X018992Y019843D01*
X018996Y019841D01* X018996Y019841D01*
X018996Y019840D01* X018996Y019841D01*
X018997Y019840D01* X018997Y019840D01*
X018999Y019838D01* X018999Y019838D01*
X019001Y019836D01* X019001Y019836D01*
@ -10846,7 +10846,7 @@ X036013Y019562D01*
X036011Y019555D01* X036011Y019555D01*
Y019555D01* Y019555D01*
X036011Y019554D01* X036011Y019554D01*
X036010Y019553D01* X036010Y019554D01*
X036010Y019553D01* X036010Y019553D01*
X036008Y019549D01* X036008Y019549D01*
X036006Y019545D01* X036006Y019545D01*
@ -11004,7 +11004,7 @@ X019478Y019562D01*
X019475Y019555D01* X019475Y019555D01*
Y019555D01* Y019555D01*
X019475Y019554D01* X019475Y019554D01*
X019475Y019553D01* X019475Y019554D01*
X019474Y019553D01* X019474Y019553D01*
X019473Y019549D01* X019473Y019549D01*
X019471Y019545D01* X019471Y019545D01*
@ -14920,7 +14920,7 @@ X035422Y017550D01*
X035420Y017558D01* X035420Y017558D01*
X035418Y017566D01* X035418Y017566D01*
X035417Y017576D01* X035417Y017576D01*
X035417Y017585D01* X035417Y017586D01*
Y017592D01* Y017592D01*
X035417Y017596D01* X035417Y017596D01*
X035418Y017601D01* X035418Y017601D01*
@ -15166,7 +15166,7 @@ X018886Y017550D01*
X018884Y017558D01* X018884Y017558D01*
X018883Y017566D01* X018883Y017566D01*
X018882Y017576D01* X018882Y017576D01*
X018881Y017585D01* X018881Y017586D01*
Y017592D01* Y017592D01*
X018882Y017596D01* X018882Y017596D01*
X018882Y017601D01* X018882Y017601D01*
@ -29687,7 +29687,7 @@ X035513Y019972D01*
X035515Y019969D01* X035515Y019969D01*
X035518Y019966D01* X035518Y019966D01*
X035521Y019964D01* X035521Y019964D01*
X035521Y019963D01* X035521Y019964D01*
X035522Y019963D01* X035522Y019963D01*
X035524Y019962D01* X035524Y019962D01*
X035526Y019960D01* X035526Y019960D01*
@ -29755,7 +29755,7 @@ X018978Y019972D01*
X018980Y019969D01* X018980Y019969D01*
X018982Y019966D01* X018982Y019966D01*
X018985Y019964D01* X018985Y019964D01*
X018985Y019963D01* X018985Y019964D01*
X018986Y019963D01* X018986Y019963D01*
X018988Y019962D01* X018988Y019962D01*
X018990Y019960D01* X018990Y019960D01*
@ -30358,7 +30358,7 @@ X035959Y019546D01*
X035963Y019548D01* X035963Y019548D01*
X035967Y019551D01* X035967Y019551D01*
X035970Y019553D01* X035970Y019553D01*
X035971Y019553D01* X035971Y019554D01*
X035972Y019554D01* X035972Y019554D01*
X035974Y019556D01* X035974Y019556D01*
X035975Y019558D01* X035975Y019558D01*
@ -30492,7 +30492,7 @@ X019424Y019546D01*
X019427Y019548D01* X019427Y019548D01*
X019431Y019551D01* X019431Y019551D01*
X019435Y019553D01* X019435Y019553D01*
X019435Y019553D01* X019435Y019554D01*
X019436Y019554D01* X019436Y019554D01*
X019438Y019556D01* X019438Y019556D01*
X019440Y019558D01* X019440Y019558D01*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Paste_Bot.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=128*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Paste_Top.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=8421504*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Positive* G04 #@! TF.FilePolarity,Positive*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Soldermask_Bot.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=16711935*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Negative* G04 #@! TF.FilePolarity,Negative*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Soldermask_Top.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=8388736*
%MOIN*% %MOIN*%
G70* G70*
G04* G04*
G04 #@! TF.SameCoordinates,AB5D8D99-9076-4583-ABAD-60FF7F719BC9* G04 #@! TF.SameCoordinates,90E71517-61D5-4869-93FD-60EF0163E4CB*
G04* G04*
G04* G04*
G04 #@! TF.FilePolarity,Negative* G04 #@! TF.FilePolarity,Negative*

4
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/NC Drill/FPGA_Module_Panel.DRR
View File

@ -1,5 +1,5 @@
---------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------
NCDrill File Report For: FPGA_Module_Panel.PcbDoc 2022-10-23 9:52:39 PM NCDrill File Report For: FPGA_Module_Panel.PcbDoc 2022-10-23 10:06:01 PM
---------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer Layer Pair : Top Layer to Bottom Layer
@ -14,4 +14,4 @@ T4 59mil (1.501mm) Round
---------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------
Totals 1312 Totals 1312
Total Processing Time (hh:mm:ss) : 00:00:00 Total Processing Time (hh:mm:ss) : 00:00:01

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Pick Place/Pick Place for FPGA_Module.txt
View File

@ -5,7 +5,7 @@ C:\Users\Aleksa\Documents\Altium\FPGA_Module\Project Outputs for FPGA_Module\Pic
File Design Information: File Design Information:
Date: 23-10-22 Date: 23-10-22
Time: 21:52 Time: 22:06
Revision: fea2ccf2aa3b92b9095698990ed03057de3edde5 Revision: fea2ccf2aa3b92b9095698990ed03057de3edde5
Variant: No variations Variant: No variations
Units used: mil Units used: mil

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Status Report.Txt
View File

@ -7,4 +7,4 @@ From : Variant [[No Variations]] of PCB Document [FPGA_Module.PcbDoc]
Files Generated : 1 Files Generated : 1
Documents Printed : 0 Documents Printed : 0
Finished Output Generation At 9:52:42 PM On 2022-10-23 Finished Output Generation At 10:06:04 PM On 2022-10-23