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Hw/aleksa/fpga module rev2 #240

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AleksaBjelogrlic merged 10 commits from HW/Aleksa/FPGA_Module_Rev2 into master 2022-11-01 02:51:38 +00:00
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Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.PcbDoc
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Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/BOM/Bill of Materials-FPGA_Module.xlsx
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Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Design Rule Check - FPGA_Module.drc
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Protel Design System Design Rule Check
PCB File : C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc
Date : 2022-10-25
Time : 9:36:55 PM
Processing Rule : Clearance Constraint (Gap=0.1mm) (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (isVia),(isPad and (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')or HasFootprint('GEN_R_0402')or HasFootprint('GEN_C_0402')or HasFootprint('MX_WSON8')))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (InNet('PG_1V0')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (InComponent('U7')),(InComponent('U7'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (isVia),(IsPad or IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=0.254mm) (Preferred=0.127mm) (InNet('PG_1V0'))
Rule Violations :0
Processing Rule : Width Constraint (Min=0.127mm) (Max=0.213mm) (Preferred=0.127mm) ((InNetClass('DDR3 ADDR')) OR (InNetClass('DQ0')) OR (InNetClass('DQ1')) OR (InNetClass('DQ2')) OR (InNetClass('DQ3')))
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=3.2mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.098mm) (All),(All)
Rule Violations :0
Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS2') or InNetClass('DQ2'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS0') or InNetClass('DQ0'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS1') or InNetClass('DQ1'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps Target=DDR3_CLK_P_PP1) (InxSignalClass('xSignals_U1_U4,U5'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=1ps) (InDifferentialPairClass('PCIe'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS3') or InNetClass('DQ3'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('DDR3_CLK') or InDifferentialPairClass('DQS0') or InDifferentialPairClass('DQS1') or InDifferentialPairClass('DQS2') or InDifferentialPairClass('DQS3'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('ADC LVDS'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('ADC LVDS'))
Rule Violations :0
Processing Rule : Matched Lengths(Delay Tolerance=5ps) (Disabled)(InNetClass('DDR3 ADDR'))
Rule Violations :0
Processing Rule : Vias Under SMD Constraint (Allowed=Not Allowed) ((HasFootprint('GEN_C_0201') OR HasFootprint('GEN_R_0201') OR HasFootprint('GEN_C_0402') OR HasFootprint('GEN_R_0402')))
Rule Violations :0
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (All),(All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:02

396
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Design Rule Check - FPGA_Module.html
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</script><title>Design Rule Verification Report</title>
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<body onload=""><img ALT="Altium" src="
file://C:\Users\Public\Documents\Altium\AD21\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">2022-10-25</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">9:36:55 PM</td>
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<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:02</td>
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<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc" class="file"><acronym title="C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc">C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc</acronym></a></td>
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<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
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</table><a name="ID2I0ZKVMN2ZWKFTUVGFM1NQPYDEF0LDAP5SPPSTH0ACSRCR2G5GCB"><h2>Summary</h2></a><table>
<tr>
<th class="column1">Warnings</th>
<th class="column2">Count</th>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
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<tr>
<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDHNXY2IIZP2WXM4FW1LKV0UEAFKCNXBCZM1MN2RKZT5WSKOMIDFCP">Clearance Constraint (Gap=0.1mm) (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')),(All)</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDLXZTPPOY3EU3JEJIYSVNMNQPFLKHOSK02LT3ARM0WONPYVOY2FMH">Clearance Constraint (Gap=0.1mm) (isVia),(isPad and (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')or HasFootprint('GEN_R_0402')or HasFootprint('GEN_C_0402')or HasFootprint('MX_WSON8')))</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDFRANBISE4ZCCEUSHZLE5LNIKOIVEUSZXRRYKDPPNJKVX4RNEWVL">Clearance Constraint (Gap=0.127mm) (InNet('PG_1V0')),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDJZIBCRE4TLIFK4HYVKFK0HNYQBWHOQFOV4KH2DK4PJ1U5W05C4MB">Clearance Constraint (Gap=0.127mm) (InComponent('U7')),(InComponent('U7'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDWHFCBSAC4OISJFP2NBIZI3FB1JC15LF02COXPOFRJFSSAUU1Q3AG">Clearance Constraint (Gap=0.127mm) (isVia),(IsPad or IsVia)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDLYBJV0CUSIV1II41J0ZPSHCC1MLIZBNDKT5KZAHG5OJEX05ILM1H">Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3')),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDHCQBTFNJ51B1E3L540ZPIHRB2MXFYQF545QRSAHNRTYOZB1RDYAK">Clearance Constraint (Gap=0.127mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
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<td class="column1"><a href="#IDGJLEN5VSOZCYG3Y4XPTXUQR44PT51CIBC5HYBQ4ZV2R2TO3CFJO">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
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<td class="column1"><a href="#IDCZQVIMIFNVZLMXNIRKQYJTJPPCJNP3WPYEZAEDISFPTXORXGV11J">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column1"><a href="#IDUQAOFLQ1SK3REOOQOVVJ3TNZBMYHHLXM0RNA12HPWQIDE35RRKWK">Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDBZ5S01SLBF5RMZEWCAP5ZI4COCB1S53G51ZL5LDEMED1FGLTMGBM">Width Constraint (Min=0.1mm) (Max=0.254mm) (Preferred=0.127mm) (InNet('PG_1V0'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDBV4XI5XPR05ANGLJVI035NJ14HKFSQBUTANKQFNVSZ0KZN2GO0XF">Width Constraint (Min=0.127mm) (Max=0.213mm) (Preferred=0.127mm) ((InNetClass('DDR3 ADDR')) OR (InNetClass('DQ0')) OR (InNetClass('DQ1')) OR (InNetClass('DQ2')) OR (InNetClass('DQ3')))</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDSNHDKKBKKCENDP1PPMIHO4WVBKCUHLTB3RVT3EEVJD5LCX3YPPNC">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
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<td class="column2">0</td>
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<td class="column1"><a href="#ID23SAZJOM2JJOOJ1AKNFXYSORCITLES31QMVWQPMULE2RBBC502VO">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID2RFWHLSX5UUTGGABPESZHIBX5ID51WZ12R0S5FKYP2BPWRDOJB4L">Minimum Solder Mask Sliver (Gap=0.098mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDHHY5RZWHBIWTLINA1NGHKX0N1NOYQTZJCLIQTMOXP0DTAK132OOE">Board Clearance Constraint (Gap=0mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDY0XWKW04VAOBDAMDLCKLRV5HEBX0I2NRMLDSRKL2BDFL32QABKZK">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS2') or InNetClass('DQ2'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDVN3L4INACCRNFKLZ3CPBG0OMBJFB4JAD4LGCA3GN55SANGPSCU5M">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS0') or InNetClass('DQ0'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID0S4D4UC5XJ02PYDCNOXDOXUE0KINBVJ1KFCSD0DFE14BDEPA2NXP">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS1') or InNetClass('DQ1'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDURHWJSZBCFHGGDVPNAFUSENNVEUKFXS11OR4XTGQVIHTFMWGJCI">Matched Lengths(Delay Tolerance=5ps Target=DDR3_CLK_P_PP1) (InxSignalClass('xSignals_U1_U4,U5'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDKATP3RPI4VD3PG2KJJQ3TPNAHN4Z23KKCOLTVJL2HFMS0Q3XD51F">Matched Lengths(Delay Tolerance=1ps) (InDifferentialPairClass('PCIe'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#ID1KGVJ5XRQM3CKL2SKQKOV1EJQMHK5G3G0O3Y24NV2OZB0GULYDZL">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS3') or InNetClass('DQ3'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDJVIFPHV0BUC1KT1330O2XYXBPICQFLV1QRTDZOOUKF0OJEP4QSZJ">Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('DDR3_CLK') or InDifferentialPairClass('DQS0') or InDifferentialPairClass('DQS1') or InDifferentialPairClass('DQS2') or InDifferentialPairClass('DQS3'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDBSDTP00BQEG0GAKQY1BYGCWDOOZWJIPA5C42X2CT3CJYWH42YNRO">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('ADC LVDS'))</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAEJOSTWFQW03M5B4ZDTVF1YRBJVZMIN4DFWIXLECWNEOKH1BLKPE">Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('ADC LVDS'))</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDBR2Y5Y1TXDERLLBKJUC4BPLDILKMXRDMGNQCKM1MZQ0CWX00YRD">Matched Lengths(Delay Tolerance=5ps) (Disabled)(InNetClass('DDR3 ADDR'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID1XMLIMUCFWHRBHPYH43KKLK25MPN5RB3PJ5GKGG4ZMRIPACU35HB">Vias Under SMD Constraint (Allowed=Not Allowed) ((HasFootprint('GEN_C_0201') OR HasFootprint('GEN_R_0201') OR HasFootprint('GEN_C_0402') OR HasFootprint('GEN_R_0402')))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDOP4QHG15R4YTHC3DXKYM035ANH4KPPSOUPNUN3IFSXKWTEWYTC1I">Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (All),(All) </a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDFEWNOKENAVGGOVIMZ44DY1SU0HTI21VTC1MLJPN53BYR01KQ50CB">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
</table><br></body>
</html>

44
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel-macro.APR_LIB
View File

@ -1,14 +1,5 @@
G04:AMPARAMS|DCode=15|XSize=18.5mil|YSize=23.6mil|CornerRadius=4.6mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
G04:AMPARAMS|DCode=15|XSize=11.8mil|YSize=26.4mil|CornerRadius=3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD15*
21,1,0.0185,0.0144,0,0,90.0*
21,1,0.0093,0.0236,0,0,90.0*
1,1,0.0093,0.0072,0.0046*
1,1,0.0093,0.0072,-0.0046*
1,1,0.0093,-0.0072,-0.0046*
1,1,0.0093,-0.0072,0.0046*
%
G04:AMPARAMS|DCode=16|XSize=11.8mil|YSize=26.4mil|CornerRadius=3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD16*
21,1,0.0118,0.0205,0,0,270.0*
21,1,0.0059,0.0264,0,0,270.0*
1,1,0.0059,-0.0102,-0.0030*
@ -25,8 +16,17 @@ G04:AMPARAMS|DCode=18|XSize=21.7mil|YSize=39.4mil|CornerRadius=5.4mil|HoleSize=0
1,1,0.0108,-0.0063,-0.0139*
1,1,0.0108,-0.0139,-0.0063*
%
G04:AMPARAMS|DCode=20|XSize=7.9mil|YSize=27.6mil|CornerRadius=2mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
G04:AMPARAMS|DCode=20|XSize=18.5mil|YSize=23.6mil|CornerRadius=4.6mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD20*
21,1,0.0185,0.0144,0,0,90.0*
21,1,0.0093,0.0236,0,0,90.0*
1,1,0.0093,0.0072,0.0046*
1,1,0.0093,0.0072,-0.0046*
1,1,0.0093,-0.0072,-0.0046*
1,1,0.0093,-0.0072,0.0046*
%
G04:AMPARAMS|DCode=21|XSize=7.9mil|YSize=27.6mil|CornerRadius=2mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD21*
21,1,0.0079,0.0236,0,0,180.0*
21,1,0.0039,0.0276,0,0,180.0*
1,1,0.0039,-0.0020,0.0118*
@ -34,8 +34,8 @@ G04:AMPARAMS|DCode=20|XSize=7.9mil|YSize=27.6mil|CornerRadius=2mil|HoleSize=0mil
1,1,0.0039,0.0020,-0.0118*
1,1,0.0039,-0.0020,-0.0118*
%
G04:AMPARAMS|DCode=21|XSize=7.9mil|YSize=27.6mil|CornerRadius=2mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD21*
G04:AMPARAMS|DCode=22|XSize=7.9mil|YSize=27.6mil|CornerRadius=2mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD22*
21,1,0.0079,0.0236,0,0,270.0*
21,1,0.0039,0.0276,0,0,270.0*
1,1,0.0039,-0.0118,-0.0020*
@ -43,15 +43,6 @@ G04:AMPARAMS|DCode=21|XSize=7.9mil|YSize=27.6mil|CornerRadius=2mil|HoleSize=0mil
1,1,0.0039,0.0118,0.0020*
1,1,0.0039,0.0118,-0.0020*
%
G04:AMPARAMS|DCode=22|XSize=157.5mil|YSize=133.9mil|CornerRadius=3.3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD22*
21,1,0.1575,0.1272,0,0,180.0*
21,1,0.1508,0.1339,0,0,180.0*
1,1,0.0067,-0.0754,0.0636*
1,1,0.0067,0.0754,0.0636*
1,1,0.0067,0.0754,-0.0636*
1,1,0.0067,-0.0754,-0.0636*
%
G04:AMPARAMS|DCode=23|XSize=17.7mil|YSize=41.3mil|CornerRadius=4.4mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD23*
21,1,0.0177,0.0325,0,0,180.0*
@ -61,6 +52,15 @@ G04:AMPARAMS|DCode=23|XSize=17.7mil|YSize=41.3mil|CornerRadius=4.4mil|HoleSize=0
1,1,0.0089,0.0044,-0.0162*
1,1,0.0089,-0.0044,-0.0162*
%
G04:AMPARAMS|DCode=24|XSize=157.5mil|YSize=133.9mil|CornerRadius=3.3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD24*
21,1,0.1575,0.1272,0,0,180.0*
21,1,0.1508,0.1339,0,0,180.0*
1,1,0.0067,-0.0754,0.0636*
1,1,0.0067,0.0754,0.0636*
1,1,0.0067,0.0754,-0.0636*
1,1,0.0067,-0.0754,-0.0636*
%
G04:AMPARAMS|DCode=25|XSize=23.6mil|YSize=23.6mil|CornerRadius=5.9mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD25*
21,1,0.0236,0.0118,0,0,270.0*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.EXTREP
View File

@ -1,5 +1,5 @@
------------------------------------------------------------------------------------------
Gerber File Extension Report For: FPGA_Module_Panel.GBR 2022-10-23 10:26:38 PM
Gerber File Extension Report For: FPGA_Module_Panel.GBR 2022-10-25 9:53:14 PM
------------------------------------------------------------------------------------------

346
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G1
View File

@ -7,15 +7,15 @@ G04 Layer_Color=16777215*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,77042C60-C616-4B62-9F68-170708952660*
G04 #@! TF.SameCoordinates,47D04AF3-0F83-4A2C-8685-F63127AC0FBC*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
G04*
G01*
G75*
%ADD46C,0.2126*%
%ADD47C,0.0591*%
%ADD46C,0.0591*%
%ADD47C,0.2126*%
%ADD48C,0.0160*%
G36*
X034468Y023455D02*
@ -1834,7 +1834,8 @@ X028131Y017739D01*
X028094Y017775D01*
X028046Y017795D01*
X027995D01*
X027989Y017793D01*
X027947Y017775D01*
X027941Y017776D01*
X027931Y017802D01*
X027894Y017839D01*
X027846Y017859D01*
@ -2505,33 +2506,33 @@ X027870Y016163D01*
D02*
G37*
G36*
X035862Y016567D02*
X035811D01*
X035763Y016547D01*
X035726Y016511D01*
X035707Y016463D01*
Y016411D01*
X035726Y016363D01*
X035762Y016328D01*
X035726Y016292D01*
X035707Y016244D01*
Y016192D01*
X035726Y016144D01*
X035763Y016108D01*
X035811Y016088D01*
X035862D01*
X035910Y016108D01*
X035947Y016144D01*
X035967Y016192D01*
Y016244D01*
X035947Y016292D01*
X035911Y016328D01*
X035947Y016363D01*
X035967Y016411D01*
Y016463D01*
X035947Y016511D01*
X035910Y016547D01*
X035862Y016567D01*
X035843Y016550D02*
X035791D01*
X035743Y016530D01*
X035707Y016493D01*
X035687Y016446D01*
Y016394D01*
X035707Y016346D01*
X035743Y016310D01*
X035707Y016274D01*
X035687Y016227D01*
Y016175D01*
X035707Y016127D01*
X035743Y016091D01*
X035791Y016071D01*
X035843D01*
X035891Y016091D01*
X035927Y016127D01*
X035947Y016175D01*
Y016227D01*
X035927Y016274D01*
X035891Y016310D01*
X035927Y016346D01*
X035947Y016394D01*
Y016446D01*
X035927Y016493D01*
X035891Y016530D01*
X035843Y016550D01*
D02*
G37*
G36*
@ -2669,6 +2670,36 @@ X021770Y014992D01*
D02*
G37*
G36*
X035844Y014828D02*
X035793D01*
X035745Y014808D01*
X035708Y014772D01*
X035688Y014724D01*
Y014672D01*
X035708Y014625D01*
X035739Y014594D01*
X035707Y014562D01*
X035687Y014514D01*
Y014462D01*
X035707Y014415D01*
X035743Y014378D01*
X035791Y014358D01*
X035843D01*
X035891Y014378D01*
X035927Y014415D01*
X035947Y014462D01*
Y014514D01*
X035927Y014562D01*
X035897Y014592D01*
X035929Y014625D01*
X035948Y014672D01*
Y014724D01*
X035929Y014772D01*
X035892Y014808D01*
X035844Y014828D01*
D02*
G37*
G36*
X023235Y014598D02*
X023183D01*
X023135Y014579D01*
@ -2709,36 +2740,6 @@ X021770Y014598D01*
D02*
G37*
G36*
X035864Y014797D02*
X035812D01*
X035765Y014777D01*
X035728Y014740D01*
X035708Y014693D01*
Y014641D01*
X035728Y014593D01*
X035759Y014562D01*
X035726Y014530D01*
X035707Y014483D01*
Y014431D01*
X035726Y014383D01*
X035763Y014346D01*
X035811Y014327D01*
X035862D01*
X035910Y014346D01*
X035947Y014383D01*
X035967Y014431D01*
Y014483D01*
X035947Y014530D01*
X035916Y014561D01*
X035948Y014593D01*
X035968Y014641D01*
Y014693D01*
X035948Y014740D01*
X035912Y014777D01*
X035864Y014797D01*
D02*
G37*
G36*
X022376Y014402D02*
X022324D01*
X022277Y014382D01*
@ -10002,7 +10003,8 @@ X011595Y017739D01*
X011559Y017775D01*
X011511Y017795D01*
X011459D01*
X011453Y017793D01*
X011411Y017775D01*
X011406Y017776D01*
X011395Y017802D01*
X011359Y017839D01*
X011311Y017859D01*
@ -10673,33 +10675,33 @@ X011335Y016163D01*
D02*
G37*
G36*
X019327Y016567D02*
X019275D01*
X019228Y016547D01*
X019191Y016511D01*
X019171Y016463D01*
Y016411D01*
X019191Y016363D01*
X019227Y016328D01*
X019191Y016292D01*
X019171Y016244D01*
Y016192D01*
X019191Y016144D01*
X019228Y016108D01*
X019275Y016088D01*
X019327D01*
X019375Y016108D01*
X019411Y016144D01*
X019431Y016192D01*
Y016244D01*
X019411Y016292D01*
X019376Y016328D01*
X019411Y016363D01*
X019431Y016411D01*
Y016463D01*
X019411Y016511D01*
X019375Y016547D01*
X019327Y016567D01*
X019307Y016550D02*
X019256D01*
X019208Y016530D01*
X019171Y016493D01*
X019152Y016446D01*
Y016394D01*
X019171Y016346D01*
X019207Y016310D01*
X019171Y016274D01*
X019152Y016227D01*
Y016175D01*
X019171Y016127D01*
X019208Y016091D01*
X019256Y016071D01*
X019307D01*
X019355Y016091D01*
X019392Y016127D01*
X019411Y016175D01*
Y016227D01*
X019392Y016274D01*
X019356Y016310D01*
X019392Y016346D01*
X019411Y016394D01*
Y016446D01*
X019392Y016493D01*
X019355Y016530D01*
X019307Y016550D01*
D02*
G37*
G36*
@ -10837,6 +10839,36 @@ X005235Y014992D01*
D02*
G37*
G36*
X019309Y014828D02*
X019257D01*
X019209Y014808D01*
X019173Y014772D01*
X019153Y014724D01*
Y014672D01*
X019173Y014625D01*
X019203Y014594D01*
X019171Y014562D01*
X019152Y014514D01*
Y014462D01*
X019171Y014415D01*
X019208Y014378D01*
X019256Y014358D01*
X019307D01*
X019355Y014378D01*
X019392Y014415D01*
X019411Y014462D01*
Y014514D01*
X019392Y014562D01*
X019361Y014592D01*
X019393Y014625D01*
X019413Y014672D01*
Y014724D01*
X019393Y014772D01*
X019357Y014808D01*
X019309Y014828D01*
D02*
G37*
G36*
X006699Y014598D02*
X006647D01*
X006600Y014579D01*
@ -10877,36 +10909,6 @@ X005235Y014598D01*
D02*
G37*
G36*
X019329Y014797D02*
X019277D01*
X019229Y014777D01*
X019193Y014740D01*
X019173Y014693D01*
Y014641D01*
X019193Y014593D01*
X019223Y014562D01*
X019191Y014530D01*
X019171Y014483D01*
Y014431D01*
X019191Y014383D01*
X019228Y014346D01*
X019275Y014327D01*
X019327D01*
X019375Y014346D01*
X019411Y014383D01*
X019431Y014431D01*
Y014483D01*
X019411Y014530D01*
X019381Y014561D01*
X019413Y014593D01*
X019433Y014641D01*
Y014693D01*
X019413Y014740D01*
X019376Y014777D01*
X019329Y014797D01*
D02*
G37*
G36*
X005841Y014402D02*
X005789D01*
X005741Y014382D01*
@ -16548,6 +16550,31 @@ D02*
G37*
%LPD*%
D46*
X015738Y005059D02*
D03*
X007884D02*
D03*
X005059Y019675D02*
D03*
Y007884D02*
D03*
X017657Y019675D02*
D03*
Y007884D02*
D03*
X032274Y005059D02*
D03*
X024419D02*
D03*
X021594Y019675D02*
D03*
Y007884D02*
D03*
X034193Y019675D02*
D03*
Y007884D02*
D03*
D47*
X018504Y005118D02*
D03*
X005118D02*
@ -16564,32 +16591,21 @@ X035039Y022441D02*
D03*
X021654D02*
D03*
D47*
X007884Y005059D02*
D03*
X015738D02*
D03*
X005059Y019675D02*
D03*
Y007884D02*
D03*
X017657Y019675D02*
D03*
Y007884D02*
D03*
X024419Y005059D02*
D03*
X032274D02*
D03*
X021594Y019675D02*
D03*
Y007884D02*
D03*
X034193Y019675D02*
D03*
Y007884D02*
D03*
D48*
X013327Y004144D02*
D03*
X019261Y015967D02*
D03*
X019262Y013376D02*
D03*
X019262Y012590D02*
D03*
X019262Y011801D02*
D03*
X011319Y004350D02*
D03*
X012480D02*
D03*
X013356Y010955D02*
D03*
X012992Y023228D02*
@ -16638,12 +16654,6 @@ X019291Y007874D02*
D03*
Y007087D02*
D03*
Y013386D02*
D03*
X019291Y012599D02*
D03*
X019291Y011811D02*
D03*
X015748Y004331D02*
D03*
X014961D02*
@ -16816,14 +16826,10 @@ X019301Y014911D02*
D03*
Y016703D02*
D03*
X019281Y015984D02*
D03*
X011167Y005478D02*
D03*
X010335Y004331D02*
D03*
X011319D02*
D03*
X011865Y005208D02*
D03*
X010342Y005657D02*
@ -16836,10 +16842,6 @@ X018159Y006811D02*
D03*
X016407Y007274D02*
D03*
X013289Y004129D02*
D03*
X012487Y004339D02*
D03*
X005512Y016230D02*
D03*
X005797Y015846D02*
@ -17004,6 +17006,20 @@ X009606D02*
D03*
X008976Y007795D02*
D03*
X029862Y004144D02*
D03*
X035797Y015967D02*
D03*
X035797Y013376D02*
D03*
X035797Y012590D02*
D03*
X035797Y011801D02*
D03*
X027854Y004350D02*
D03*
X029016D02*
D03*
X029892Y010955D02*
D03*
X029528Y023228D02*
@ -17052,12 +17068,6 @@ X035827Y007874D02*
D03*
Y007087D02*
D03*
Y013386D02*
D03*
X035827Y012599D02*
D03*
X035827Y011811D02*
D03*
X032283Y004331D02*
D03*
X031496D02*
@ -17230,14 +17240,10 @@ X035837Y014911D02*
D03*
Y016703D02*
D03*
X035817Y015984D02*
D03*
X027702Y005478D02*
D03*
X026870Y004331D02*
D03*
X027854D02*
D03*
X028401Y005208D02*
D03*
X026878Y005657D02*
@ -17250,10 +17256,6 @@ X034695Y006811D02*
D03*
X032943Y007274D02*
D03*
X029824Y004129D02*
D03*
X029023Y004339D02*
D03*
X022047Y016230D02*
D03*
X022333Y015846D02*

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G2
View File

@ -7,7 +7,7 @@ G04 Layer_Color=36540*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,77042C60-C616-4B62-9F68-170708952660*
G04 #@! TF.SameCoordinates,47D04AF3-0F83-4A2C-8685-F63127AC0FBC*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*

622
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G3
View File

@ -7,7 +7,7 @@ G04 Layer_Color=10517442*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,77042C60-C616-4B62-9F68-170708952660*
G04 #@! TF.SameCoordinates,47D04AF3-0F83-4A2C-8685-F63127AC0FBC*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
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@ -20507,6 +20500,27 @@ X012264D02*
X012319Y005240D01*
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X014088Y004379D01*
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X029977Y004414D01*
X027210Y008505D02*
X027275Y008570D01*
X027380Y008446D02*
@ -20555,40 +20569,18 @@ X025512Y008681D02*
Y008740D01*
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Y008382D01*
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346
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G4
View File

@ -7,15 +7,15 @@ G04 Layer_Color=16737945*
%MOIN*%
G70*
G04*
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G04 #@! TF.SameCoordinates,47D04AF3-0F83-4A2C-8685-F63127AC0FBC*
G04*
G04*
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G04*
G01*
G75*
%ADD46C,0.2126*%
%ADD47C,0.0591*%
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%ADD47C,0.2126*%
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G36*
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@ -1834,7 +1834,8 @@ X028131Y017739D01*
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@ -2505,33 +2506,33 @@ X027870Y016163D01*
D02*
G37*
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D02*
G37*
G36*
@ -2669,6 +2670,36 @@ X021770Y014992D01*
D02*
G37*
G36*
X035844Y014828D02*
X035793D01*
X035745Y014808D01*
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D02*
G37*
G36*
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X023183D01*
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@ -2709,36 +2740,6 @@ X021770Y014598D01*
D02*
G37*
G36*
X035864Y014797D02*
X035812D01*
X035765Y014777D01*
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D02*
G37*
G36*
X022376Y014402D02*
X022324D01*
X022277Y014382D01*
@ -10002,7 +10003,8 @@ X011595Y017739D01*
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@ -10673,33 +10675,33 @@ X011335Y016163D01*
D02*
G37*
G36*
X019327Y016567D02*
X019275D01*
X019228Y016547D01*
X019191Y016511D01*
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X019431Y016411D01*
Y016463D01*
X019411Y016511D01*
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X019307Y016550D02*
X019256D01*
X019208Y016530D01*
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X019152Y016446D01*
Y016394D01*
X019171Y016346D01*
X019207Y016310D01*
X019171Y016274D01*
X019152Y016227D01*
Y016175D01*
X019171Y016127D01*
X019208Y016091D01*
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X019355Y016091D01*
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Y016227D01*
X019392Y016274D01*
X019356Y016310D01*
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X019411Y016394D01*
Y016446D01*
X019392Y016493D01*
X019355Y016530D01*
X019307Y016550D01*
D02*
G37*
G36*
@ -10837,6 +10839,36 @@ X005235Y014992D01*
D02*
G37*
G36*
X019309Y014828D02*
X019257D01*
X019209Y014808D01*
X019173Y014772D01*
X019153Y014724D01*
Y014672D01*
X019173Y014625D01*
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X019152Y014514D01*
Y014462D01*
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Y014514D01*
X019392Y014562D01*
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X019413Y014672D01*
Y014724D01*
X019393Y014772D01*
X019357Y014808D01*
X019309Y014828D01*
D02*
G37*
G36*
X006699Y014598D02*
X006647D01*
X006600Y014579D01*
@ -10877,36 +10909,6 @@ X005235Y014598D01*
D02*
G37*
G36*
X019329Y014797D02*
X019277D01*
X019229Y014777D01*
X019193Y014740D01*
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Y014641D01*
X019193Y014593D01*
X019223Y014562D01*
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Y014431D01*
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Y014483D01*
X019411Y014530D01*
X019381Y014561D01*
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X019433Y014641D01*
Y014693D01*
X019413Y014740D01*
X019376Y014777D01*
X019329Y014797D01*
D02*
G37*
G36*
X005841Y014402D02*
X005789D01*
X005741Y014382D01*
@ -16548,6 +16550,31 @@ D02*
G37*
%LPD*%
D46*
X015738Y005059D02*
D03*
X007884D02*
D03*
X005059Y019675D02*
D03*
Y007884D02*
D03*
X017657Y019675D02*
D03*
Y007884D02*
D03*
X032274Y005059D02*
D03*
X024419D02*
D03*
X021594Y019675D02*
D03*
Y007884D02*
D03*
X034193Y019675D02*
D03*
Y007884D02*
D03*
D47*
X018504Y005118D02*
D03*
X005118D02*
@ -16564,32 +16591,21 @@ X035039Y022441D02*
D03*
X021654D02*
D03*
D47*
X007884Y005059D02*
D03*
X015738D02*
D03*
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D03*
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D03*
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D03*
Y007884D02*
D03*
X024419Y005059D02*
D03*
X032274D02*
D03*
X021594Y019675D02*
D03*
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D03*
X034193Y019675D02*
D03*
Y007884D02*
D03*
D48*
X013327Y004144D02*
D03*
X019261Y015967D02*
D03*
X019262Y013376D02*
D03*
X019262Y012590D02*
D03*
X019262Y011801D02*
D03*
X011319Y004350D02*
D03*
X012480D02*
D03*
X013356Y010955D02*
D03*
X012992Y023228D02*
@ -16638,12 +16654,6 @@ X019291Y007874D02*
D03*
Y007087D02*
D03*
Y013386D02*
D03*
X019291Y012599D02*
D03*
X019291Y011811D02*
D03*
X015748Y004331D02*
D03*
X014961D02*
@ -16816,14 +16826,10 @@ X019301Y014911D02*
D03*
Y016703D02*
D03*
X019281Y015984D02*
D03*
X011167Y005478D02*
D03*
X010335Y004331D02*
D03*
X011319D02*
D03*
X011865Y005208D02*
D03*
X010342Y005657D02*
@ -16836,10 +16842,6 @@ X018159Y006811D02*
D03*
X016407Y007274D02*
D03*
X013289Y004129D02*
D03*
X012487Y004339D02*
D03*
X005512Y016230D02*
D03*
X005797Y015846D02*
@ -17004,6 +17006,20 @@ X009606D02*
D03*
X008976Y007795D02*
D03*
X029862Y004144D02*
D03*
X035797Y015967D02*
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D03*
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D03*
X029016D02*
D03*
X029892Y010955D02*
D03*
X029528Y023228D02*
@ -17052,12 +17068,6 @@ X035827Y007874D02*
D03*
Y007087D02*
D03*
Y013386D02*
D03*
X035827Y012599D02*
D03*
X035827Y011811D02*
D03*
X032283Y004331D02*
D03*
X031496D02*
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D03*
Y016703D02*
D03*
X035817Y015984D02*
D03*
X027702Y005478D02*
D03*
X026870Y004331D02*
D03*
X027854D02*
D03*
X028401Y005208D02*
D03*
X026878Y005657D02*
@ -17250,10 +17256,6 @@ X034695Y006811D02*
D03*
X032943Y007274D02*
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X029023Y004339D02*
D03*
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D03*
X022333Y015846D02*

2180
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.GBL
View File

File diff suppressed because it is too large Load Diff

4538
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.GTL
View File

File diff suppressed because it is too large Load Diff

10
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.REP
View File

@ -14,7 +14,7 @@ Used DCodes :
D10
D11
D12
D19
D16
D25
D26
D29
@ -187,8 +187,8 @@ Used DCodes :
D19
D20
D21
D22
D23
D24
D25
D26
D27
@ -229,7 +229,7 @@ Used DCodes :
D17
D18
D19
D22
D20
D23
D24
D25
@ -269,7 +269,7 @@ Generating : Bottom Solder
Used DCodes :
D10
D19
D16
D25
D26
D29
@ -302,7 +302,7 @@ Generating : Bottom Paste
Used DCodes :
D19
D16
D25
D26
D29

10
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.apr
View File

@ -3,16 +3,16 @@ D11 ROUNDED 5.000 5.000 0.000 LINE 0.000
D12 ROUNDED 3.937 3.937 0.000 LINE 0.000
D13 ROUNDED 3.937 3.937 0.000 FLASH 0.000
D14 ROUNDED 5.118 5.118 0.000 LINE 0.000
D17 ROUNDED 11.000 11.000 0.000 FLASH 0.000
D19 ROUNDED 15.748 15.748 0.000 FLASH 0.000
D24 ROUNDED 13.780 13.780 0.000 FLASH 0.000
D16 ROUNDED 15.748 15.748 0.000 FLASH 0.000
D17 ROUNDED 13.780 13.780 0.000 FLASH 0.000
D19 ROUNDED 11.000 11.000 0.000 FLASH 0.000
D41 ROUNDED 10.000 10.000 0.000 LINE 0.000
D42 ROUNDED 4.990 4.990 0.000 LINE 0.000
D43 ROUNDED 19.685 19.685 0.000 LINE 0.000
D44 ROUNDED 7.511 7.511 0.000 LINE 0.000
D45 ROUNDED 125.984 125.984 0.000 FLASH 0.000
D46 ROUNDED 212.598 212.598 0.000 FLASH 0.000
D47 ROUNDED 59.055 59.055 0.000 FLASH 0.000
D46 ROUNDED 59.055 59.055 0.000 FLASH 0.000
D47 ROUNDED 212.598 212.598 0.000 FLASH 0.000
D48 ROUNDED 16.000 16.000 0.000 FLASH 0.000
D49 ROUNDED 4.882 4.882 0.000 LINE 0.000
D50 ROUNDED 4.320 4.320 0.000 LINE 0.000

2
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Board Outline.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=16711935*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,77042C60-C616-4B62-9F68-170708952660*
G04 #@! TF.SameCoordinates,47D04AF3-0F83-4A2C-8685-F63127AC0FBC*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*

65034
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Drill_Drawing.gbr
View File

File diff suppressed because it is too large Load Diff

370
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Drillguide.gbr
View File

@ -6,7 +6,7 @@ G04 Layer_Color=128*
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,77042C60-C616-4B62-9F68-170708952660*
G04 #@! TF.SameCoordinates,47D04AF3-0F83-4A2C-8685-F63127AC0FBC*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
@ -31,6 +31,54 @@ X005276Y025591D02*
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@ -211,18 +255,6 @@ X019251Y007087D02*
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@ -1147,10 +1179,6 @@ X019261Y016703D02*
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@ -1159,10 +1187,6 @@ X010295Y004331D02*
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@ -1203,14 +1227,6 @@ X015201Y006395D02*
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@ -1679,14 +1695,6 @@ X005775Y017815D02*
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@ -1767,14 +1775,6 @@ X012716Y009370D02*
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@ -2647,6 +2647,54 @@ X012401Y007795D02*
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@ -2663,54 +2711,50 @@ X021024Y022441D02*
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@ -2827,18 +2871,6 @@ X035787Y007087D02*
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@ -3775,10 +3803,6 @@ X026830Y004331D02*
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@ -4295,14 +4311,6 @@ X022310Y017815D02*
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@ -4383,14 +4391,6 @@ X029251Y009370D02*
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92610
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Fab_Notes.gbr
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File diff suppressed because it is too large Load Diff

41189
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Legend_Bot.gbr
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File diff suppressed because it is too large Load Diff

36751
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Legend_Top.gbr
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File diff suppressed because it is too large Load Diff

1764
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Paste_Bot.gbr
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File diff suppressed because it is too large Load Diff

3666
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Paste_Top.gbr
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File diff suppressed because it is too large Load Diff

1866
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Soldermask_Bot.gbr
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File diff suppressed because it is too large Load Diff

3778
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Soldermask_Top.gbr
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File diff suppressed because it is too large Load Diff

7
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/NC Drill/FPGA_Module_Panel.DRR
View File

@ -1,5 +1,5 @@
----------------------------------------------------------------------------------------------------------------------------------
NCDrill File Report For: FPGA_Module_Panel.PcbDoc 2022-10-23 10:26:49 PM
NCDrill File Report For: FPGA_Module_Panel.PcbDoc 2022-10-25 9:53:24 PM
----------------------------------------------------------------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
@ -7,10 +7,11 @@ ASCII RoundHoles File : FPGA_Module_Panel.TXT
Tool Hole Size Hole Tolerance Hole Type Hole Count Plated Tool Travel
----------------------------------------------------------------------------------------------------------------------------------
T1 8mil (0.203mm) Round 1276 PTH 75.79inch (1925.01mm)
T1 8mil (0.203mm) Round 1276 PTH 75.30inch (1912.68mm)
T2 39mil (1.001mm) Round 12 PTH 10.02inch (254.47mm)
T3 126mil (3.2mm) Round 12 PTH 11.84inch (300.78mm)
T3 126mil (3.2mm) Round 8 PTH 7.72inch (196.00mm)
T4 59mil (1.501mm) Round 12 NPTH 9.63inch (244.67mm)
T5 126mil (3.2mm) Round 4 NPTH 9.36inch (237.72mm)
----------------------------------------------------------------------------------------------------------------------------------
Totals 1312

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