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Hw/aleksa/fpga module rev2 #240

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AleksaBjelogrlic merged 10 commits from HW/Aleksa/FPGA_Module_Rev2 into master 2022-11-01 02:51:38 +00:00
Conversation 0 Commits 10 Files Changed 41 +430257 -311001
38 changed files with 430257 additions and 311001 deletions
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3
Hardware/The Next Generation/FPGA_Module_Rev2/.gitignore vendored
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@ -8,8 +8,7 @@
# Project Logs # Project Logs
Project Logs*/ Project Logs*/
# Project Outputs # Project Outputs Project Outputs*/
Project Outputs*/
# Auto-conversion notices # Auto-conversion notices
*.PcbDoc.htm *.PcbDoc.htm

Hardware/The Next Generation/FPGA_Module_Rev2/Copy of FPGA_Module.PcbDoc
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Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.PcbDoc
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Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.PrjPcb
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@ -33,7 +33,7 @@ FSMCodingStyle=eFMSDropDownList_OneProcess
FSMEncodingStyle=eFMSDropDownList_OneHot FSMEncodingStyle=eFMSDropDownList_OneHot
IsProjectConflictPreventionWarningsEnabled=0 IsProjectConflictPreventionWarningsEnabled=0
IsVirtualBomDocumentRemoved=0 IsVirtualBomDocumentRemoved=0
OutputPath= OutputPath=Project Outputs for FPGA_Module
LogFolderPath= LogFolderPath=
ManagedProjectGUID=FBDD5B7D-1FB1-4C39-A525-0E81901E11EE ManagedProjectGUID=FBDD5B7D-1FB1-4C39-A525-0E81901E11EE
VaultGUID=b03a642c-f334-40b3-b929-2941954f9f28 VaultGUID=b03a642c-f334-40b3-b929-2941954f9f28
@ -225,23 +225,6 @@ GenerateClassCluster=0
DocumentUniqueId=BOVLKBAJ DocumentUniqueId=BOVLKBAJ
[Document11] [Document11]
DocumentPath=FPGA_Module.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=DWMBPBHF
[Document12]
DocumentPath=Job1.OutJob DocumentPath=Job1.OutJob
AnnotationEnabled=1 AnnotationEnabled=1
AnnotateStartValue=1 AnnotateStartValue=1
@ -258,13 +241,39 @@ DItemRevisionGUID=
GenerateClassCluster=0 GenerateClassCluster=0
DocumentUniqueId= DocumentUniqueId=
[GeneratedDocument1] [Document12]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.DRR DocumentPath=FPGA_Module.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID= DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=DWMBPBHF
[GeneratedDocument2] [Document13]
DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.LDP DocumentPath=FPGA_Module_Panel.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID= DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=DWMBPBHF
[Configuration1] [Configuration1]
Name=Sources Name=Sources
@ -307,7 +316,7 @@ AutoOpenOutJob=0
[Generic_SmartPDFSettings] [Generic_SmartPDFSettings]
ProjectMode=-1 ProjectMode=-1
ZoomPrecision=50 ZoomPrecision=50
AddNetsInformation=-1 AddNetsInformation=0
AddNetPins=-1 AddNetPins=-1
AddNetNetLabels=-1 AddNetNetLabels=-1
AddNetPorts=-1 AddNetPorts=-1
@ -337,7 +346,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
SaveSettingsToOutJob=0 SaveSettingsToOutJob=0
[Generic_EDE] [Generic_EDE]
OutputDir= OutputDir=Project Outputs for FPGA_Module
[OutputGroup1] [OutputGroup1]
Name=Netlist Outputs Name=Netlist Outputs
@ -455,7 +464,7 @@ PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate
Name=Documentation Outputs Name=Documentation Outputs
Description= Description=
TargetPrinter=Virtual Printer TargetPrinter=Virtual Printer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=0
OutputType1=Composite OutputType1=Composite
OutputName1=Composite Drawing OutputName1=Composite Drawing
OutputDocumentPath1= OutputDocumentPath1=
@ -515,7 +524,9 @@ OutputName10=Schematic Prints
OutputDocumentPath10= OutputDocumentPath10=
OutputVariantName10= OutputVariantName10=
OutputDefault10=0 OutputDefault10=0
PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4|PaperIndex=9
Configuration10_Name1=OutputConfigurationParameter1
Configuration10_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ShowOpenEnds=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Connectors.SchDoc
OutputType11=SimView Print OutputType11=SimView Print
OutputName11=SimView Prints OutputName11=SimView Prints
OutputDocumentPath11= OutputDocumentPath11=

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Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.layerset Normal file
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LAYERSET6NAME=My Layers|LAYERSET6LAYERS=MultiLayer,TopPaste,TopOverlay,TopSolder,TopLayer,BottomLayer,BottomSolder,BottomOverlay,BottomPaste,MidLayer1,MidLayer2,MidLayer3,MidLayer4,DrillGuide,KeepOutLayer,Mechanical1,Mechanical2,Mechanical3,Mechanical7,Mechanical9,Mechanical10,Mechanical11,Mechanical12,Mechanical13,Mechanical14,DrillDrawing|LAYERSET6ACTIVELAYER.7=TOP|LAYERSET6ISCURRENT=FALSE|LAYERSET6ISLOCKED=FALSE|LAYERSET6FLIPBOARD=FALSE

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Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.pdf
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Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Assembly Drawing.PDF Normal file
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Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/FPGA_Module_20221007.zip Normal file
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Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel-macro.APR_LIB Normal file
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1,1,0.0059,0.0030,-0.0266*
1,1,0.0059,-0.0030,-0.0266*
1,1,0.0059,-0.0030,0.0266*
1,1,0.0059,0.0030,0.0266*
%
G04:AMPARAMS|DCode=52|XSize=11.8mil|YSize=59.1mil|CornerRadius=3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD52*
21,1,0.0118,0.0531,0,0,270.0*
21,1,0.0059,0.0591,0,0,270.0*
1,1,0.0059,-0.0266,-0.0030*
1,1,0.0059,-0.0266,0.0030*
1,1,0.0059,0.0266,0.0030*
1,1,0.0059,0.0266,-0.0030*
%
G04:AMPARAMS|DCode=53|XSize=16.5mil|YSize=18.1mil|CornerRadius=4.1mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD53*
21,1,0.0165,0.0098,0,0,180.0*
21,1,0.0083,0.0181,0,0,180.0*
1,1,0.0083,-0.0041,0.0049*
1,1,0.0083,0.0041,0.0049*
1,1,0.0083,0.0041,-0.0049*
1,1,0.0083,-0.0041,-0.0049*
%
G04:AMPARAMS|DCode=54|XSize=110.2mil|YSize=65mil|CornerRadius=8.1mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=45.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD54*
21,1,0.1102,0.0487,0,0,45.0*
21,1,0.0940,0.0650,0,0,45.0*
1,1,0.0162,0.0505,0.0160*
1,1,0.0162,-0.0160,-0.0505*
1,1,0.0162,-0.0505,-0.0160*
1,1,0.0162,0.0160,0.0505*
%
G04:AMPARAMS|DCode=55|XSize=16.5mil|YSize=18.1mil|CornerRadius=4.1mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=135.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD55*
21,1,0.0165,0.0098,0,0,135.0*
21,1,0.0083,0.0181,0,0,135.0*
1,1,0.0083,0.0006,0.0064*
1,1,0.0083,0.0064,0.0006*
1,1,0.0083,-0.0006,-0.0064*
1,1,0.0083,-0.0064,-0.0006*
%
G04:AMPARAMS|DCode=65|XSize=11.9mil|YSize=31.6mil|CornerRadius=4mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD65*
21,1,0.0119,0.0236,0,0,180.0*
21,1,0.0039,0.0316,0,0,180.0*
1,1,0.0079,-0.0020,0.0118*
1,1,0.0079,0.0020,0.0118*
1,1,0.0079,0.0020,-0.0118*
1,1,0.0079,-0.0020,-0.0118*
%
G04:AMPARAMS|DCode=66|XSize=11.9mil|YSize=31.6mil|CornerRadius=4mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD66*
21,1,0.0119,0.0236,0,0,270.0*
21,1,0.0039,0.0316,0,0,270.0*
1,1,0.0079,-0.0118,-0.0020*
1,1,0.0079,-0.0118,0.0020*
1,1,0.0079,0.0118,0.0020*
1,1,0.0079,0.0118,-0.0020*
%

25
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.EXTREP Normal file
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------------------------------------------------------------------------------------------
Gerber File Extension Report For: FPGA_Module_Panel.GBR 2022-10-19 10:28:49 PM
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.gbr Top Overlay
.gbr Top Paste
.gbr Top Solder
.GTL Top Layer
.G1 Int1 (GND)
.G2 Int2 (Sign)
.G3 Int3 (Sign)
.G4 Int4 (GND)
.GBL Bottom Layer
.gbr Bottom Solder
.gbr Bottom Paste
.gbr Bottom Overlay
.gbr Mechanical 1
.gbr Mechanical 7
.gbr Drill Drawing
.gbr Drill Guide
------------------------------------------------------------------------------------------

17409
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G1 Normal file
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15889
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G2 Normal file
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20795
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G3 Normal file
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17409
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.G4 Normal file
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15147
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.GBL Normal file
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18592
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.GTL Normal file
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384
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.REP Normal file
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*************************************************************
FileName = FPGA_Module_Panel.GBR
AutoAperture = True
*************************************************************
Generating : Top Overlay
File : FPGA_Module_Panel_Legend_Top.gbr
Adding Layer : Top Overlay
Used DCodes :
D12
D41
D56
D58
D59
*************************************************************
*************************************************************
Generating : Top Paste
File : FPGA_Module_Panel_Paste_Top.gbr
Adding Layer : Top Paste
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D15
D16
D17
D18
D19
D20
D21
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D60
D61
D62
D63
*************************************************************
*************************************************************
Generating : Top Solder
File : FPGA_Module_Panel_Soldermask_Top.gbr
Adding Layer : Top Solder
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D15
D16
D17
D18
D19
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D45
D46
D47
D64
D65
D66
*************************************************************
*************************************************************
Generating : Bottom Solder
File : FPGA_Module_Panel_Soldermask_Bot.gbr
Adding Layer : Bottom Solder
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D19
D25
D26
D29
D30
D33
D34
D37
D39
D40
D45
D46
D47
D51
D52
D53
D54
D55
D64
*************************************************************
*************************************************************
Generating : Bottom Paste
File : FPGA_Module_Panel_Paste_Bot.gbr
Adding Layer : Bottom Paste
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D19
D25
D26
D29
D30
D33
D34
D37
D39
D40
D51
D52
D53
D54
D55
*************************************************************
*************************************************************
Generating : Bottom Overlay
File : FPGA_Module_Panel_Legend_Bot.gbr
Adding Layer : Bottom Overlay
Used DCodes :
D12
D56
D59
*************************************************************
*************************************************************
Generating : Mechanical 1
File : FPGA_Module_Panel_Board_Outline.gbr
Adding Layer : Mechanical 1
Used DCodes :
D12
*************************************************************
*************************************************************
Generating : Mechanical 7
File : FPGA_Module_Panel_Fab_Notes.gbr
Adding Layer : Mechanical 7
Used DCodes :
D67
*************************************************************
*************************************************************
Generating : Drill Drawing
File : FPGA_Module_Panel_Drill_Drawing_1.gbr
Adding Drill Pair : Top Layer-Bottom Layer
Adding Layer : Drill Drawing
Used DCodes :
D41
D68
D69
*************************************************************
*************************************************************
Generating : Drill Guide
File : FPGA_Module_Panel_Drill_Guide_1.gbr
Adding Drill Pair : Top Layer-Bottom Layer
Adding Layer : Drill Guide
Used DCodes :
D68
*************************************************************
*************************************************************
Generating : Top Layer
File : FPGA_Module_Panel.GTL
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
*************************************************************
*************************************************************
Generating : Int1 (GND)
File : FPGA_Module_Panel.G1
Adding Layer : Int1 (GND)
Adding Layer : Multi-Layer
Used DCodes :
D46
D47
D48
*************************************************************
*************************************************************
Generating : Int2 (Sign)
File : FPGA_Module_Panel.G2
Adding Layer : Int2 (Sign)
Adding Layer : Multi-Layer
Used DCodes :
D11
D12
D48
*************************************************************
*************************************************************
Generating : Int3 (Sign)
File : FPGA_Module_Panel.G3
Adding Layer : Int3 (Sign)
Adding Layer : Multi-Layer
Used DCodes :
D11
D12
D41
D48
D49
D50
*************************************************************
*************************************************************
Generating : Int4 (GND)
File : FPGA_Module_Panel.G4
Adding Layer : Int4 (GND)
Adding Layer : Multi-Layer
Used DCodes :
D46
D47
D48
*************************************************************
*************************************************************
Generating : Bottom Layer
File : FPGA_Module_Panel.GBL
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D11
D12
D19
D25
D26
D29
D30
D33
D34
D37
D39
D40
D41
D44
D45
D46
D47
D48
D51
D52
D53
D54
D55
D56
D57
*************************************************************

13
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.RUL Normal file
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DRC Rules Export File for PCB: C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
RuleKind=Clearance|RuleName=Clearance_1|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=Via to Pad_0201|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=Clearance_0201|Scope=Board|Minimum=3.94
RuleKind=Width|RuleName=Width_PG_1V0|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=Clearance_PG_1V0|Scope=Board|Minimum=5.00
RuleKind=Clearance|RuleName=Clearance_U7|Scope=Board|Minimum=5.00
RuleKind=Clearance|RuleName=Via to Pad|Scope=Board|Minimum=5.00
RuleKind=Width|RuleName=50Z|Scope=Board|Minimum=5.00
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=0.00
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=5.00
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=5.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0

30
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.apr Normal file
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D10 ROUNDED 39.370 39.370 0.000 FLASH 0.000
D11 ROUNDED 5.000 5.000 0.000 LINE 0.000
D12 ROUNDED 3.937 3.937 0.000 LINE 0.000
D13 ROUNDED 3.937 3.937 0.000 FLASH 0.000
D14 ROUNDED 5.118 5.118 0.000 LINE 0.000
D17 ROUNDED 11.000 11.000 0.000 FLASH 0.000
D19 ROUNDED 15.748 15.748 0.000 FLASH 0.000
D24 ROUNDED 13.780 13.780 0.000 FLASH 0.000
D41 ROUNDED 10.000 10.000 0.000 LINE 0.000
D42 ROUNDED 4.990 4.990 0.000 LINE 0.000
D43 ROUNDED 19.685 19.685 0.000 LINE 0.000
D44 ROUNDED 7.511 7.511 0.000 LINE 0.000
D45 ROUNDED 125.984 125.984 0.000 FLASH 0.000
D46 ROUNDED 236.220 236.220 0.000 FLASH 0.000
D47 ROUNDED 59.055 59.055 0.000 FLASH 0.000
D48 ROUNDED 16.000 16.000 0.000 FLASH 0.000
D49 ROUNDED 4.882 4.882 0.000 LINE 0.000
D50 ROUNDED 4.320 4.320 0.000 LINE 0.000
D56 ROUNDED 7.874 7.874 0.000 LINE 0.000
D57 ROUNDED 8.000 8.000 0.000 LINE 0.000
D58 ROUNDED 6.102 6.102 0.000 LINE 0.000
D59 ROUNDED 9.842 9.842 0.000 LINE 0.000
D60 RECTANGULAR 70.866 59.055 0.000 FLASH 0.000
D61 RECTANGULAR 70.866 59.055 0.000 FLASH 0.000
D62 RECTANGULAR 70.866 59.055 0.000 FLASH 0.000
D63 RECTANGULAR 70.866 59.055 0.000 FLASH 0.000
D64 ROUNDED 78.740 78.740 0.000 FLASH 0.000
D67 ROUNDED 11.811 11.811 0.000 LINE 0.000
D68 ROUNDED 2.000 2.000 0.000 LINE 0.000
D69 ROUNDED 15.000 15.000 0.000 LINE 0.000

6853
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Board_Outline.gbr Normal file
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90354
Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel_Drill_Drawing_1.gbr Normal file
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