Hardware/The Next Generation/FPGA_Module_Rev2/.gitignore

@@ -8,8 +8,7 @@
 # Project Logs
 Project Logs*/
 
-# Project Outputs
+# Project Outputs Project Outputs*/
-Project Outputs*/
 
 # Auto-conversion notices
 *.PcbDoc.htm

Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.PrjPcb

@@ -225,23 +225,6 @@ GenerateClassCluster=0
 DocumentUniqueId=BOVLKBAJ
 
 [Document11]
-DocumentPath=FPGA_Module.PcbDoc
-AnnotationEnabled=1
-AnnotateStartValue=1
-AnnotationIndexControlEnabled=0
-AnnotateSuffix=
-AnnotateScope=All
-AnnotateOrder=-1
-DoLibraryUpdate=1
-DoDatabaseUpdate=1
-ClassGenCCAutoEnabled=1
-ClassGenCCAutoRoomEnabled=1
-ClassGenNCAutoScope=None
-DItemRevisionGUID=
-GenerateClassCluster=0
-DocumentUniqueId=DWMBPBHF
-
-[Document12]
 DocumentPath=Job1.OutJob
 AnnotationEnabled=1
 AnnotateStartValue=1
@@ -258,144 +241,138 @@ DItemRevisionGUID=
 GenerateClassCluster=0
 DocumentUniqueId=
 
+[Document12]
+DocumentPath=FPGA_Module.PcbDoc
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=DWMBPBHF
+
+[Document13]
+DocumentPath=FPGA_Module_Panel.PcbDoc
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=NWUHWUCY
+
 [GeneratedDocument1]
-DocumentPath=Project Outputs for FPGA_Module\Design Rule Check - FPGA_Module.html
+DocumentPath=Project Outputs for FPGA_Module\BOM\Bill of Materials-FPGA_Module.xlsx
 DItemRevisionGUID=
 
 [GeneratedDocument2]
-DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.DRR
+DocumentPath=Project Outputs for FPGA_Module\Design Rule Check - FPGA_Module.html
 DItemRevisionGUID=
 
 [GeneratedDocument3]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.EXTREP
+DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.DRR
 DItemRevisionGUID=
 
 [GeneratedDocument4]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G1
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.EXTREP
 DItemRevisionGUID=
 
 [GeneratedDocument5]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G2
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G1
 DItemRevisionGUID=
 
 [GeneratedDocument6]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G3
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G2
 DItemRevisionGUID=
 
 [GeneratedDocument7]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.G4
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G3
 DItemRevisionGUID=
 
 [GeneratedDocument8]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBL
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.G4
 DItemRevisionGUID=
 
 [GeneratedDocument9]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBO
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GBL
 DItemRevisionGUID=
 
 [GeneratedDocument10]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBP
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.GTL
 DItemRevisionGUID=
 
 [GeneratedDocument11]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GBS
+DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.LDP
 DItemRevisionGUID=
 
 [GeneratedDocument12]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GM1
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.REP
 DItemRevisionGUID=
 
 [GeneratedDocument13]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTL
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel.RUL
 DItemRevisionGUID=
 
 [GeneratedDocument14]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTO
+DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module_Panel.TXT
 DItemRevisionGUID=
 
 [GeneratedDocument15]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTP
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Board Outline.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument16]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.GTS
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drill_Drawing.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument17]
-DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.LDP
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Drillguide.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument18]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.REP
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Fab_Notes.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument19]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module.RUL
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Bot.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument20]
-DocumentPath=Project Outputs for FPGA_Module\NC Drill\FPGA_Module.TXT
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Legend_Top.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument21]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_1.gbr
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Bot.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument22]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_2.gbr
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Paste_Top.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument23]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_3.gbr
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Bot.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument24]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_4.gbr
+DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Panel_Soldermask_Top.gbr
 DItemRevisionGUID=
 
 [GeneratedDocument25]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_Bot.gbr
+DocumentPath=Project Outputs for FPGA_Module\Pick Place\Pick Place for FPGA_Module.txt
-DItemRevisionGUID=
-
-[GeneratedDocument26]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Copper_Signal_Top.gbr
-DItemRevisionGUID=
-
-[GeneratedDocument27]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Drawing_1.gbr
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-
-[GeneratedDocument28]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Legend_Bot.gbr
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-[GeneratedDocument29]
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-DItemRevisionGUID=
-
-[GeneratedDocument30]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Mechanical_1.gbr
-DItemRevisionGUID=
-
-[GeneratedDocument31]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Mechanical_7.gbr
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-
-[GeneratedDocument32]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Paste_Bot.gbr
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-
-[GeneratedDocument33]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Paste_Top.gbr
-DItemRevisionGUID=
-
-[GeneratedDocument34]
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-DItemRevisionGUID=
-
-[GeneratedDocument35]
-DocumentPath=Project Outputs for FPGA_Module\Gerber\FPGA_Module_Soldermask_Top.gbr
 DItemRevisionGUID=
 
 [Configuration1]
@@ -439,7 +416,7 @@ AutoOpenOutJob=0
 [Generic_SmartPDFSettings]
 ProjectMode=-1
 ZoomPrecision=50
-AddNetsInformation=-1
+AddNetsInformation=0
 AddNetPins=-1
 AddNetNetLabels=-1
 AddNetPorts=-1
@@ -587,7 +564,7 @@ PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate
 Name=Documentation Outputs
 Description=
 TargetPrinter=Virtual Printer
-PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=0
 OutputType1=Composite
 OutputName1=Composite Drawing
 OutputDocumentPath1=
@@ -647,7 +624,9 @@ OutputName10=Schematic Prints
 OutputDocumentPath10=
 OutputVariantName10=
 OutputDefault10=0
-PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4|PaperIndex=9
+Configuration10_Name1=OutputConfigurationParameter1
+Configuration10_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ShowOpenEnds=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Connectors.SchDoc
 OutputType11=SimView Print
 OutputName11=SimView Prints
 OutputDocumentPath11=

Hardware/The Next Generation/FPGA_Module_Rev2/FPGA_Module.layerset

@@ -0,0 +1 @@
+LAYERSET6NAME=My Layers|LAYERSET6LAYERS=MultiLayer,TopPaste,TopOverlay,TopSolder,TopLayer,BottomLayer,BottomSolder,BottomOverlay,BottomPaste,MidLayer1,MidLayer2,MidLayer3,MidLayer4,DrillGuide,KeepOutLayer,Mechanical1,Mechanical2,Mechanical3,Mechanical7,Mechanical9,Mechanical10,Mechanical11,Mechanical12,Mechanical13,Mechanical14,DrillDrawing|LAYERSET6ACTIVELAYER.7=TOP|LAYERSET6ISCURRENT=FALSE|LAYERSET6ISLOCKED=FALSE|LAYERSET6FLIPBOARD=FALSE

Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel-macro.APR_LIB

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+1,1,0.0187,0.0113,-0.0094*
+%
+G04:AMPARAMS|DCode=36|XSize=25.2mil|YSize=25.2mil|CornerRadius=6.3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=315.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD36*
+21,1,0.0252,0.0126,0,0,315.0*
+21,1,0.0126,0.0252,0,0,315.0*
+1,1,0.0126,0.0000,-0.0089*
+1,1,0.0126,-0.0089,0.0000*
+1,1,0.0126,0.0000,0.0089*
+1,1,0.0126,0.0089,0.0000*
+%
+G04:AMPARAMS|DCode=37|XSize=25.2mil|YSize=25.2mil|CornerRadius=6.3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=225.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD37*
+21,1,0.0252,0.0126,0,0,225.0*
+21,1,0.0126,0.0252,0,0,225.0*
+1,1,0.0126,-0.0089,0.0000*
+1,1,0.0126,0.0000,0.0089*
+1,1,0.0126,0.0089,0.0000*
+1,1,0.0126,0.0000,-0.0089*
+%
+G04:AMPARAMS|DCode=38|XSize=59.1mil|YSize=51.2mil|CornerRadius=12.8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=45.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD38*
+21,1,0.0591,0.0256,0,0,45.0*
+21,1,0.0335,0.0512,0,0,45.0*
+1,1,0.0256,0.0209,0.0028*
+1,1,0.0256,-0.0028,-0.0209*
+1,1,0.0256,-0.0209,-0.0028*
+1,1,0.0256,0.0028,0.0209*
+%
+G04:AMPARAMS|DCode=39|XSize=59.1mil|YSize=51.2mil|CornerRadius=12.8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD39*
+21,1,0.0591,0.0256,0,0,90.0*
+21,1,0.0335,0.0512,0,0,90.0*
+1,1,0.0256,0.0128,0.0167*
+1,1,0.0256,0.0128,-0.0167*
+1,1,0.0256,-0.0128,-0.0167*
+1,1,0.0256,-0.0128,0.0167*
+%
+G04:AMPARAMS|DCode=40|XSize=16.5mil|YSize=18.1mil|CornerRadius=4.1mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD40*
+21,1,0.0165,0.0098,0,0,270.0*
+21,1,0.0083,0.0181,0,0,270.0*
+1,1,0.0083,-0.0049,-0.0041*
+1,1,0.0083,-0.0049,0.0041*
+1,1,0.0083,0.0049,0.0041*
+1,1,0.0083,0.0049,-0.0041*
+%
+G04:AMPARAMS|DCode=51|XSize=11.8mil|YSize=59.1mil|CornerRadius=3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD51*
+21,1,0.0118,0.0531,0,0,0.0*
+21,1,0.0059,0.0591,0,0,0.0*
+1,1,0.0059,0.0030,-0.0266*
+1,1,0.0059,-0.0030,-0.0266*
+1,1,0.0059,-0.0030,0.0266*
+1,1,0.0059,0.0030,0.0266*
+%
+G04:AMPARAMS|DCode=52|XSize=11.8mil|YSize=59.1mil|CornerRadius=3mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD52*
+21,1,0.0118,0.0531,0,0,270.0*
+21,1,0.0059,0.0591,0,0,270.0*
+1,1,0.0059,-0.0266,-0.0030*
+1,1,0.0059,-0.0266,0.0030*
+1,1,0.0059,0.0266,0.0030*
+1,1,0.0059,0.0266,-0.0030*
+%
+G04:AMPARAMS|DCode=53|XSize=16.5mil|YSize=18.1mil|CornerRadius=4.1mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD53*
+21,1,0.0165,0.0098,0,0,180.0*
+21,1,0.0083,0.0181,0,0,180.0*
+1,1,0.0083,-0.0041,0.0049*
+1,1,0.0083,0.0041,0.0049*
+1,1,0.0083,0.0041,-0.0049*
+1,1,0.0083,-0.0041,-0.0049*
+%
+G04:AMPARAMS|DCode=54|XSize=110.2mil|YSize=65mil|CornerRadius=8.1mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=45.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD54*
+21,1,0.1102,0.0487,0,0,45.0*
+21,1,0.0940,0.0650,0,0,45.0*
+1,1,0.0162,0.0505,0.0160*
+1,1,0.0162,-0.0160,-0.0505*
+1,1,0.0162,-0.0505,-0.0160*
+1,1,0.0162,0.0160,0.0505*
+%
+G04:AMPARAMS|DCode=55|XSize=16.5mil|YSize=18.1mil|CornerRadius=4.1mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=135.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD55*
+21,1,0.0165,0.0098,0,0,135.0*
+21,1,0.0083,0.0181,0,0,135.0*
+1,1,0.0083,0.0006,0.0064*
+1,1,0.0083,0.0064,0.0006*
+1,1,0.0083,-0.0006,-0.0064*
+1,1,0.0083,-0.0064,-0.0006*
+%
+G04:AMPARAMS|DCode=65|XSize=11.9mil|YSize=31.6mil|CornerRadius=4mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD65*
+21,1,0.0119,0.0236,0,0,180.0*
+21,1,0.0039,0.0316,0,0,180.0*
+1,1,0.0079,-0.0020,0.0118*
+1,1,0.0079,0.0020,0.0118*
+1,1,0.0079,0.0020,-0.0118*
+1,1,0.0079,-0.0020,-0.0118*
+%
+G04:AMPARAMS|DCode=66|XSize=11.9mil|YSize=31.6mil|CornerRadius=4mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*
+%AMROUNDEDRECTD66*
+21,1,0.0119,0.0236,0,0,270.0*
+21,1,0.0039,0.0316,0,0,270.0*
+1,1,0.0079,-0.0118,-0.0020*
+1,1,0.0079,-0.0118,0.0020*
+1,1,0.0079,0.0118,0.0020*
+1,1,0.0079,0.0118,-0.0020*
+%

Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.EXTREP

@@ -0,0 +1,25 @@
+------------------------------------------------------------------------------------------
+Gerber File Extension Report For: FPGA_Module_Panel.GBR   2022-10-25  9:53:14 PM
+------------------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------------------
+Layer Extension     Layer Description                      
+------------------------------------------------------------------------------------------
+.gbr                Top Overlay                             
+.gbr                Top Paste                               
+.gbr                Top Solder                              
+.GTL                Top Layer                               
+.G1                 Int1 (GND)                              
+.G2                 Int2 (Sign)                             
+.G3                 Int3 (Sign)                             
+.G4                 Int4 (GND)                              
+.GBL                Bottom Layer                            
+.gbr                Bottom Solder                           
+.gbr                Bottom Paste                            
+.gbr                Bottom Overlay                          
+.gbr                Mechanical 1                            
+.gbr                Mechanical 7                            
+.gbr                Drill Drawing                           
+.gbr                Drill Guide                             
+------------------------------------------------------------------------------------------

Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.REP

@@ -0,0 +1,384 @@
+*************************************************************
+FileName = FPGA_Module_Panel.GBR
+AutoAperture = True
+*************************************************************
+Generating : Bottom Layer
+      File : FPGA_Module_Panel.GBL
+
+    Adding Layer      : Bottom Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D11
+    D12
+    D16
+    D25
+    D26
+    D29
+    D30
+    D33
+    D34
+    D37
+    D39
+    D40
+    D41
+    D44
+    D45
+    D46
+    D47
+    D48
+    D51
+    D52
+    D53
+    D54
+    D55
+    D56
+    D57
+*************************************************************
+
+*************************************************************
+Generating : Int4 (GND)
+      File : FPGA_Module_Panel.G4
+
+    Adding Layer      : Int4 (GND)
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D46
+    D47
+    D48
+*************************************************************
+
+*************************************************************
+Generating : Int3 (Sign)
+      File : FPGA_Module_Panel.G3
+
+    Adding Layer      : Int3 (Sign)
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D11
+    D12
+    D41
+    D48
+    D49
+    D50
+*************************************************************
+
+*************************************************************
+Generating : Int2 (Sign)
+      File : FPGA_Module_Panel.G2
+
+    Adding Layer      : Int2 (Sign)
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D11
+    D12
+    D48
+*************************************************************
+
+*************************************************************
+Generating : Int1 (GND)
+      File : FPGA_Module_Panel.G1
+
+    Adding Layer      : Int1 (GND)
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D46
+    D47
+    D48
+*************************************************************
+
+*************************************************************
+Generating : Top Layer
+      File : FPGA_Module_Panel.GTL
+
+    Adding Layer      : Top Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D11
+    D12
+    D13
+    D14
+    D15
+    D16
+    D17
+    D18
+    D19
+    D20
+    D21
+    D22
+    D23
+    D24
+    D25
+    D26
+    D27
+    D28
+    D29
+    D30
+    D31
+    D32
+    D33
+    D34
+    D35
+    D36
+    D37
+    D38
+    D39
+    D40
+    D41
+    D42
+    D43
+    D44
+    D45
+    D46
+    D47
+    D48
+*************************************************************
+
+*************************************************************
+Generating : Top Overlay
+      File : FPGA_Module_Panel_Legend_Top.gbr
+
+    Adding Layer      : Top Overlay
+
+
+Used DCodes :
+    D12
+    D41
+    D56
+    D58
+    D59
+*************************************************************
+
+*************************************************************
+Generating : Top Paste
+      File : FPGA_Module_Panel_Paste_Top.gbr
+
+    Adding Layer      : Top Paste
+
+    Adding Layer      : Top Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D15
+    D16
+    D17
+    D18
+    D19
+    D20
+    D21
+    D22
+    D23
+    D25
+    D26
+    D27
+    D28
+    D29
+    D30
+    D31
+    D32
+    D33
+    D34
+    D35
+    D36
+    D37
+    D38
+    D39
+    D40
+    D60
+    D61
+    D62
+    D63
+*************************************************************
+
+*************************************************************
+Generating : Top Solder
+      File : FPGA_Module_Panel_Soldermask_Top.gbr
+
+    Adding Layer      : Top Solder
+
+    Adding Layer      : Top Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D15
+    D16
+    D17
+    D18
+    D19
+    D20
+    D23
+    D24
+    D25
+    D26
+    D27
+    D28
+    D29
+    D30
+    D31
+    D32
+    D33
+    D34
+    D35
+    D36
+    D37
+    D38
+    D39
+    D40
+    D45
+    D46
+    D47
+    D64
+    D65
+    D66
+*************************************************************
+
+*************************************************************
+Generating : Bottom Solder
+      File : FPGA_Module_Panel_Soldermask_Bot.gbr
+
+    Adding Layer      : Bottom Solder
+
+    Adding Layer      : Bottom Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D10
+    D16
+    D25
+    D26
+    D29
+    D30
+    D33
+    D34
+    D37
+    D39
+    D40
+    D45
+    D46
+    D47
+    D51
+    D52
+    D53
+    D54
+    D55
+    D64
+*************************************************************
+
+*************************************************************
+Generating : Bottom Paste
+      File : FPGA_Module_Panel_Paste_Bot.gbr
+
+    Adding Layer      : Bottom Paste
+
+    Adding Layer      : Bottom Layer
+
+    Adding Layer      : Multi-Layer
+
+
+Used DCodes :
+    D16
+    D25
+    D26
+    D29
+    D30
+    D33
+    D34
+    D37
+    D39
+    D40
+    D51
+    D52
+    D53
+    D54
+    D55
+*************************************************************
+
+*************************************************************
+Generating : Bottom Overlay
+      File : FPGA_Module_Panel_Legend_Bot.gbr
+
+    Adding Layer      : Bottom Overlay
+
+
+Used DCodes :
+    D12
+    D56
+    D59
+*************************************************************
+
+*************************************************************
+Generating : Mechanical 1
+      File : FPGA_Module_Panel_Board Outline.gbr
+
+    Adding Layer      : Mechanical 1
+
+
+Used DCodes :
+    D12
+*************************************************************
+
+*************************************************************
+Generating : Mechanical 7
+      File : FPGA_Module_Panel_Fab_Notes.gbr
+
+    Adding Layer      : Mechanical 7
+
+
+Used DCodes :
+    D67
+*************************************************************
+
+*************************************************************
+Generating : Drill Drawing
+      File : FPGA_Module_Panel_Drill_Drawing.gbr
+
+    Adding Drill Pair : Top Layer-Bottom Layer
+
+    Adding Layer      : Drill Drawing
+
+
+Used DCodes :
+    D41
+    D68
+    D69
+*************************************************************
+
+*************************************************************
+Generating : Drill Guide
+      File : FPGA_Module_Panel_Drillguide.gbr
+
+    Adding Drill Pair : Top Layer-Bottom Layer
+
+    Adding Layer      : Drill Guide
+
+
+Used DCodes :
+    D68
+*************************************************************
+

Hardware/The Next Generation/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Gerber/FPGA_Module_Panel.RUL

@@ -0,0 +1,13 @@
+DRC Rules Export File for PCB: C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
+RuleKind=Clearance|RuleName=Clearance_1|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=Via to Pad_0201|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=Clearance_0201|Scope=Board|Minimum=3.94
+RuleKind=Width|RuleName=Width_PG_1V0|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=Clearance_PG_1V0|Scope=Board|Minimum=5.00
+RuleKind=Clearance|RuleName=Clearance_U7|Scope=Board|Minimum=5.00
+RuleKind=Clearance|RuleName=Via to Pad|Scope=Board|Minimum=5.00
+RuleKind=Width|RuleName=50Z|Scope=Board|Minimum=5.00
+RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=0.00
+RuleKind=Width|RuleName=Width|Scope=Board|Minimum=5.00
+RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=5.00
+RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0