Hardware/FPGA_Module_Rev2/Job1.OutJob

@@ -45,7 +45,7 @@ OutputEnabled1_OutputMedium3=1
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+Configuration1_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|BoardID=NWUHWUCY|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=KeepLeadingAndTrailingZeroes|MaxApertureSize=2500000|MergePadAndRegion=False|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16973835~1,16973833~1,16973831~1,16908289~1,16908295~1,16777217~1,16777220~1,16777218~1,16777219~1,16777221~1,16842751~1|PlotBoardProfile=False|PlotBoardProfileFileName=FPGA_Module_Panel_Profile.gbr|PlotDrillDrawingLayerPair0_Backdrill=False|PlotDrillDrawingLayerPair0_Checked=True|PlotDrillDrawingLayerPair0_DrillType=Regular|PlotDrillDrawingLayerPair0_FileName=FPGA_Module_Panel_Drill_Drawing.gbr|PlotDrillDrawingLayerPair0_HighLayer=Bottom Layer|PlotDrillDrawingLayerPair0_LowLayer=Top Layer|PlotDrillGuideLayerPair0_Backdrill=False|PlotDrillGuideLayerPair0_Checked=True|PlotDrillGuideLayerPair0_DrillType=Regular|PlotDrillGuideLayerPair0_FileName=FPGA_Module_Panel_Drillguide.gbr|PlotDrillGuideLayerPair0_HighLayer=Bottom Layer|PlotDrillGuideLayerPair0_LowLayer=Top Layer|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|UserLayerName.Caption0=FPGA_Module_Panel_Keep-out.gbr|UserLayerName.Caption1=FPGA_Module_Panel_Paste_Top.gbr|UserLayerName.Caption10=FPGA_Module_Panel_Soldermask_Bot.gbr|UserLayerName.Caption11=FPGA_Module_Panel_Copper_Inner_3.gbr|UserLayerName.Caption12=FPGA_Module_Panel_Copper_Bottom.gbr|UserLayerName.Caption13=FPGA_Module_Panel_Bottom_3D_Body.gbr|UserLayerName.Caption14=FPGA_Module_Panel_Copper_Top.gbr|UserLayerName.Caption15=FPGA_Module_Panel_Legend_Bot.gbr|UserLayerName.Caption16=FPGA_Module_Panel_Pads_Top.gbr|UserLayerName.Caption17=FPGA_Module_Panel_Top_3D_Body.gbr|UserLayerName.Caption18=FPGA_Module_Panel_Top_Assembly.gbr|UserLayerName.Caption19=FPGA_Module_Panel_Top_Component_Center.gbr|UserLayerName.Caption2=FPGA_Module_Panel_Legend_Top.gbr|UserLayerName.Caption20=FPGA_Module_Panel_Copper_Inner_1.gbr|UserLayerName.Caption21=FPGA_Module_Panel_Board Outline.gbr|UserLayerName.Caption22=FPGA_Module_Panel_Copper_Inner_4.gbr|UserLayerName.Caption23=FPGA_Module_Panel_Bottom_Courtyard.gbr|UserLayerName.Caption24=FPGA_Module_Panel_Paste_Bot.gbr|UserLayerName.Caption3=FPGA_Module_Panel_Soldermask_Top.gbr|UserLayerName.Caption4=FPGA_Module_Panel_Bottom_Component_Center.gbr|UserLayerName.Caption5=FPGA_Module_Panel_Top_Courtyard.gbr|UserLayerName.Caption6=FPGA_Module_Panel_Pads_Bot.gbr|UserLayerName.Caption7=FPGA_Module_Panel_Copper_Inner_2.gbr|UserLayerName.Caption8=FPGA_Module_Panel_Bottom_Assembly.gbr|UserLayerName.Caption9=FPGA_Module_Panel_Fab_Notes.gbr|UserLayerName.Count=25|UserLayerName.Layer0=16973837|UserLayerName.Layer1=16973832|UserLayerName.Layer10=16973835|UserLayerName.Layer11=16777219|UserLayerName.Layer12=16842751|UserLayerName.Layer13=16908302|UserLayerName.Layer14=16777217|UserLayerName.Layer15=16973831|UserLayerName.Layer16=16973848|UserLayerName.Layer17=16908301|UserLayerName.Layer18=16908297|UserLayerName.Layer19=16908299|UserLayerName.Layer2=16973830|UserLayerName.Layer20=16777220|UserLayerName.Layer21=16908289|UserLayerName.Layer22=16777221|UserLayerName.Layer23=16908291|UserLayerName.Layer24=16973833|UserLayerName.Layer3=16973834|UserLayerName.Layer4=16908300|UserLayerName.Layer5=16908290|UserLayerName.Layer6=16973849|UserLayerName.Layer7=16777218|UserLayerName.Layer8=16908298|UserLayerName.Layer9=16908295|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
 OutputType2=NC Drill
 OutputName2=NC Drill Files
 OutputCategory2=Fabrication

Hardware/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Fab Release/FPGA_Module_Panel_Board Outline.gbr

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 G04*
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Hardware/FPGA_Module_Rev2/Project Outputs for FPGA_Module/Fab Release/FPGA_Module_Panel_Drillguide.gbr

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 X028356Y012460D02*
 Y012540D01*
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 X023484Y018593D02*
 X023564D01*
 X023524Y018553D02*
@@ -4631,14 +4695,6 @@ X030519Y009384D02*
 X030599D01*
 X030559Y009344D02*
 Y009424D01*
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 X028621Y008110D02*
 X028701D01*
 X028661Y008070D02*
@@ -5047,10 +5103,6 @@ X031141Y010945D02*
 X031221D01*
 X031181Y010905D02*
 Y010985D01*
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 X030836Y008746D02*
 X030916D01*
 X030876Y008706D02*
@@ -5195,10 +5247,6 @@ X027677Y008740D02*
 X027757D01*
 X027717Y008700D02*
 Y008780D01*
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 X025787Y009685D02*
 X025867D01*
 X025827Y009645D02*
@@ -5363,10 +5411,6 @@ X029881Y008740D02*
 X029961D01*
 X029921Y008700D02*
 Y008780D01*
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 X031171Y009380D02*
 X031251D01*
 X031211Y009340D02*
@@ -5423,10 +5467,6 @@ X030196Y008425D02*
 X030276D01*
 X030236Y008385D02*
 Y008465D01*
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 X029251Y008425D02*
 X029331D01*
 X029291Y008385D02*