Hw/aleksa/fpga module rev2 #241
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Protel Design System Design Rule Check
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PCB File : C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc
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Date : 2022-11-01
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Time : 11:02:27 PM
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WARNING: Unplated multi-layer pad(s) detected
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Pad MH4-1(37mm,3mm) on Multi-Layer on Net GND
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Pad MH3-1(3mm,3mm) on Multi-Layer on Net GND
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Pad MH2-1(37mm,47mm) on Multi-Layer on Net GND
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Pad MH1-1(3mm,47mm) on Multi-Layer on Net GND
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Processing Rule : Clearance Constraint (Gap=0.1mm) (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')),(All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.127mm) (All),(All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.127mm) (InNet('PG_1V0')),(All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.127mm) (InComponent('U7')),(InComponent('U7'))
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.127mm) (isVia),((IsPad and not InComponent('MH*')) or IsVia)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3')),(All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3') or InDifferentialPair('DDR3_CLK')),(InNet('GND'))
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.1mm) (isVia),(isPad and (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')or HasFootprint('GEN_R_0402')or HasFootprint('GEN_C_0402')or HasFootprint('MX_WSON8')))
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Rule Violations :0
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Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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Rule Violations :0
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Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.254mm) (All)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.1mm) (Max=0.254mm) (Preferred=0.127mm) (InNet('PG_1V0'))
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.127mm) (Max=0.213mm) (Preferred=0.127mm) ((InNetClass('DDR3 ADDR')) OR (InNetClass('DQ0')) OR (InNetClass('DQ1')) OR (InNetClass('DQ2')) OR (InNetClass('DQ3')))
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Rule Violations :0
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Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
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Rule Violations :0
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Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=3.2mm) (All)
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Rule Violations :0
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Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Minimum Solder Mask Sliver (Gap=0.098mm) (All),(All)
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Rule Violations :0
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Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS2') or InNetClass('DQ2'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS0') or InNetClass('DQ0'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS1') or InNetClass('DQ1'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps Target=DDR3_CLK_P_PP1) (InxSignalClass('xSignals_U1_U4,U5'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=1ps) (InDifferentialPairClass('PCIe'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS3') or InNetClass('DQ3'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('DDR3_CLK') or InDifferentialPairClass('DQS0') or InDifferentialPairClass('DQS1') or InDifferentialPairClass('DQS2') or InDifferentialPairClass('DQS3'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('ADC LVDS'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('ADC LVDS'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (Disabled)(InNetClass('DDR3 ADDR'))
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Rule Violations :0
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Processing Rule : Vias Under SMD Constraint (Allowed=Not Allowed) ((HasFootprint('GEN_C_0201') OR HasFootprint('GEN_R_0201') OR HasFootprint('GEN_C_0402') OR HasFootprint('GEN_R_0402')))
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Rule Violations :0
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Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (All),(All)
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Rule Violations :0
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Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
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Rule Violations :0
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Violations Detected : 0
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Waived Violations : 0
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Time Elapsed : 00:00:03
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@ -1,420 +0,0 @@
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<html>
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<head>
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<META http-equiv="Content-Type" content="text/html">
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<style type="text/css">
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h1, h2, h3, h4, h5, h6 {
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table {
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width : 100%;
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font-size: 0.9em;
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.DRC_summary_header {
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padding-bottom : 0.1em;
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border : 0px solid black;
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padding-bottom 0.2em;
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font-weight: bold;
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width : auto;
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.header_holder {
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Width = 100%;
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border = 0px solid green;
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padding = 0;
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}
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.front_matter, .front_matter_column1, .front_matter_column2, .front_matter_column3
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text-align: left;
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}
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width : 8em;
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font-weight : bold;
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text-align : left;
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.warning, .error {
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font-size : 110%;
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position : relative;
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left : 20px;
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margin : 0.5em;
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||||
}
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</script><title>Design Rule Verification Report</title>
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</head>
|
||||
<body onload=""><img ALT="Altium" src="
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file://C:\Users\Public\Documents\Altium\AD21\Templates\AD_logo.png
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"><h1>Design Rule Verification Report</h1>
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<table class="header_holder">
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||||
<td class="column1">
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<table class="front_matter">
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||||
<tr class="front_matter">
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<td class="front_matter_column1">Date:</td>
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<td class="front_matter_column2"></td>
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<td class="front_matter_column3">2022-11-01</td>
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</tr>
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<tr class="front_matter">
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<td class="front_matter_column1">Time:</td>
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<td class="front_matter_column2"></td>
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<td class="front_matter_column3">11:02:27 PM</td>
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</tr>
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<tr class="front_matter">
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<td class="front_matter_column1">Elapsed Time:</td>
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<td class="front_matter_column2"></td>
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<td class="front_matter_column3">00:00:03</td>
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</tr>
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<tr class="front_matter">
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<td class="front_matter_column1">Filename:</td>
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<td class="front_matter_column2"></td>
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<td class="front_matter_column3"><a href="file:///C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc" class="file"><acronym title="C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc">C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc</acronym></a></td>
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</tr>
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||||
</table>
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||||
</td>
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||||
<td class="column2">
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<table class="DRC_summary_header">
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<tr>
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<td class="DRC_summary_header_col1">Warnings:</td>
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<td class="DRC_summary_header_col2"></td>
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<td class="DRC_summary_header_col3" style="color : red">4</td></tr>
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<tr>
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<td class="DRC_summary_header_col1">Rule Violations:</td>
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<td class="DRC_summary_header_col2"></td>
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||||
<td class="DRC_summary_header_col3">0</td></tr>
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||||
</table>
|
||||
</td>
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||||
</table><a name="ID5PFZKYWSE5UEI3YAVERZJGROBEFEXXDB1OOUXKGWQGMKRKO2UVTI"><h2>Summary</h2></a><table>
|
||||
<tr>
|
||||
<th class="column1">Warnings</th>
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||||
<th class="column2">Count</th>
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||||
</tr>
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||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID032PEIWSBHA5JYSVYMW4X5RPTDINYUR2TW5OSLHQ2OENA1PLDYVD">Unplated multi-layer pad(s) detected</a></td>
|
||||
<td class="column2">4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">4</td>
|
||||
</tr>
|
||||
</table><br><table>
|
||||
<tr>
|
||||
<th class="column1">Rule Violations</th>
|
||||
<th class="column2">Count</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDYM1JM2OY52Q5DKO3OGXSSK3QQJG34KZ4GRNYKQCWP0OVGTZENNG">Clearance Constraint (Gap=0.1mm) (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDZ15OZFPJVMJYBI4EQS103152TOML1GMYD5VPMRH4KNSK4DEZCRIM">Clearance Constraint (Gap=0.127mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDD4MDFURGNL1CC3GUOG4DTT45RNQTSNMYI5J5Z1K2NSS14JINBBKO">Clearance Constraint (Gap=0.127mm) (InNet('PG_1V0')),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDRH5XDBXGASW2HWADJL0NCBURVKPJ5QBMKWG510GCXDXJ4IDNBLYB">Clearance Constraint (Gap=0.127mm) (InComponent('U7')),(InComponent('U7'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID4FPCUOMGN0MZGUM20XJYTGENJH1OEKLL0IDUNKEVYKPLL5XQ3IMH">Clearance Constraint (Gap=0.127mm) (isVia),((IsPad and not InComponent('MH*')) or IsVia)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID4RXI01F0Y2POCPIOFMIUMDESUHNTKRTMGDMRP1XZWQYRKLEBXJC">Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3')),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID0EX0ZVGCYYCPLRGHMJQPXK12BCLBF1JTERYYMMFYIZHIVCZZSDEF">Clearance Constraint (Gap=0.1mm) (InNetClass('DDR3 ADDR') or InNetClass('DQ0') or InNetClass('DQ1') or InNetClass('DQ2') or InNetClass('DQ3') or InDifferentialPair('DDR3_CLK')),(InNet('GND'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID5XDRBJEOIRI4GVNI5QS22QGAWIL3CPAMXFPJO3HPDE2YZWD0REPH">Clearance Constraint (Gap=0.1mm) (isVia),(isPad and (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')or HasFootprint('GEN_R_0402')or HasFootprint('GEN_C_0402')or HasFootprint('MX_WSON8')))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDUTXLGCM1IKS1BVMR5PDM3PNCPIEQSUZ3KB1K54MJXTWMNGJG4QEJ">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID4BPZDTIDHFB0JOILIS3XFZLWLJB2V55YQZRYKFHE41E40PHMDCNF">Un-Routed Net Constraint ( (All) )</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDD0JLFPIJA1L4CZR2JIBXBKGD3OAZUCPQFXGVHJJFC5MVUED0A3MB">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID0N0MYAE4WCL4EBMXCRQFCB0W0IPWWV3UPG2HODNVGHCEDAOLKYCB">Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID3DZBYKFRFH4CL4HF55YMQJCEOEK01Y3YW4T1T0IMRSD2CPRRQKAE">Width Constraint (Min=0.1mm) (Max=0.254mm) (Preferred=0.127mm) (InNet('PG_1V0'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDECYGENQEY4WBKRKWDRVNZWP4IEITM4FZ21T3VVL513X2GBRMWE0K">Width Constraint (Min=0.127mm) (Max=0.213mm) (Preferred=0.127mm) ((InNetClass('DDR3 ADDR')) OR (InNetClass('DQ0')) OR (InNetClass('DQ1')) OR (InNetClass('DQ2')) OR (InNetClass('DQ3')))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDAYHMASNH5Z0UDF0YRVLDRHPJFLH3IGRVODF3VONWGA4LNZPJIYXO">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDZ4QE1MYSDQZPGCEDZ1F2SRW5OEZ5JAXBFQQ0VCLXUE3QCFPCUERI">Hole Size Constraint (Min=0.025mm) (Max=3.2mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDVL3JQ3SPGG3OKAFFHT3MYMUKJMIMICBKSW1RB0C3JFT3DE0NST2J">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDDSDOVRKKSRTOIT1HPPSCLMLW5BSCACIM4HVXJJLCG0RDQVNSQOFM">Minimum Solder Mask Sliver (Gap=0.098mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID5XXU0T4UVMWDH2JT3VSVDQ3GXPSBPGW5EVHP1ILQ0C0ZRMMB01FJ">Board Clearance Constraint (Gap=0mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDE5GHLIOTRQIXOWDL5AUTSZB3GE2HOM5E4SWM1OJQD0E5PGTWIA0L">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS2') or InNetClass('DQ2'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDIYSP31H0FXSBBVAP0KQZJMZNT24RZZPVIB4YIKTYMGT3ZCRJGRJ">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS0') or InNetClass('DQ0'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDZFP1QJOOVYDNER03LYHBJ0Y1HHAE5C40ZXJTGEOZN2Z3KTRUTGTH">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS1') or InNetClass('DQ1'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID1J1DN4ACXJJUEMS0RDHQKAOWVOQXJLEINVOUKYOBIWNJAPZPTHBL">Matched Lengths(Delay Tolerance=5ps Target=DDR3_CLK_P_PP1) (InxSignalClass('xSignals_U1_U4,U5'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDOBT0MTDIGAJQFRF01PBIOYSVSBUKLMYA5CFMJXBYVL2Y3VYSZ0LO">Matched Lengths(Delay Tolerance=1ps) (InDifferentialPairClass('PCIe'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDOCHTWUJFPLCLHQI3CIQM4ZYNFHG12T3TUSSJQLK01HWV44ULPFGI">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS3') or InNetClass('DQ3'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDXJAUGDEEPHGUDK13IASJU21AGP3LUA43435I02LFPKR24XK0WXHI">Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('DDR3_CLK') or InDifferentialPairClass('DQS0') or InDifferentialPairClass('DQS1') or InDifferentialPairClass('DQS2') or InDifferentialPairClass('DQS3'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDWOMT40AVY23LG2JQHHVKJGE0HL2C2WRHDIJAJBBMXWEFVDX3LCUK">Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('ADC LVDS'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDOYRIBWPKB0FUJ14SIZBGOLHY5I44BA5QFZJGXM2WQUCQJM1B4QF">Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('ADC LVDS'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID4T5EIC3KXHA2BA4OQNNRVL0UXIG3VR5MAZ4MU1JTEGJRVAQ2C31L">Matched Lengths(Delay Tolerance=5ps) (Disabled)(InNetClass('DDR3 ADDR'))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDBPN3HAAMIQ0YDTBRD5T5ZKBEWGJY5WF0HPXDCYMF0XB4VBEP3F5O">Vias Under SMD Constraint (Allowed=Not Allowed) ((HasFootprint('GEN_C_0201') OR HasFootprint('GEN_R_0201') OR HasFootprint('GEN_C_0402') OR HasFootprint('GEN_R_0402')))</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDHP3HBB124QFOIDFKOLUQM3Y03IOCMKW2ZFI3QMIWBKT5UFIMRQ1N">Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (All),(All) </a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDO4CSZKQMTFBFIJBLLIOZ4LUJOKINV0NBU3EWPSMFRAONTSFKJA0C">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">0</td>
|
||||
</tr>
|
||||
</table><br><a name="IDJENMQEWAFESHDOAY20P2HPQVSI0WIRM4D15BJ5MXHFES3PLMIRWF"><h2>Warnings</h2></a><a name="ID032PEIWSBHA5JYSVYMW4X5RPTDINYUR2TW5OSLHQ2OENA1PLDYVD"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="warning">Unplated multi-layer pad(s) detected</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2374.016mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=1248.031mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2374.016mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=1248.031mil|Absolute=True">Pad MH4-1(37mm,3mm) on Multi-Layer</acronym></a> on <a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True">Net GND</acronym></a></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=1248.031mil|Location1.Y=1035.433mil|Location2.Y=1248.031mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=1248.031mil|Location1.Y=1035.433mil|Location2.Y=1248.031mil|Absolute=True">Pad MH3-1(3mm,3mm) on Multi-Layer</acronym></a> on <a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True">Net GND</acronym></a></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2374.016mil|Location2.X=2586.614mil|Location1.Y=2767.716mil|Location2.Y=2980.315mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2374.016mil|Location2.X=2586.614mil|Location1.Y=2767.716mil|Location2.Y=2980.315mil|Absolute=True">Pad MH2-1(37mm,47mm) on Multi-Layer</acronym></a> on <a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True">Net GND</acronym></a></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=1248.031mil|Location1.Y=2767.716mil|Location2.Y=2980.315mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=1248.031mil|Location1.Y=2767.716mil|Location2.Y=2980.315mil|Absolute=True">Pad MH1-1(3mm,47mm) on Multi-Layer</acronym></a> on <a href="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1035.433mil|Location2.X=2586.614mil|Location1.Y=1035.433mil|Location2.Y=2980.315mil|Absolute=True">Net GND</acronym></a></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br></body>
|
||||
</html>
|
||||
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Reference in New Issue