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Add FW changes for Rev3
#245
Merged
AleksaBjelogrlic
merged 2 commits from
FW/Aleksa/TE0712_Rev3_Baseboard
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master
2023-04-04 01:57:52 +00:00
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/README.txt → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/README.txt
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_auto_cc_0/sim/design_1_auto_cc_0.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_auto_cc_0/sim/design_1_auto_cc_0.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_auto_us_df_0/sim/design_1_auto_us_df_0.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_auto_us_df_0/sim/design_1_auto_us_df_0.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_auto_us_df_1/sim/design_1_auto_us_df_1.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_auto_us_df_1/sim/design_1_auto_us_df_1.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_datamover_0_0/sim/design_1_axi_datamover_0_0.vhd → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_datamover_0_0/sim/design_1_axi_datamover_0_0.vhd
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_gpio_0_1/sim/design_1_axi_gpio_0_1.vhd → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_gpio_0_1/sim/design_1_axi_gpio_0_1.vhd
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_axi_gpio_1_0/sim/design_1_axi_gpio_1_0.vhd → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_gpio_1_0/sim/design_1_axi_gpio_1_0.vhd
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_m00_data_fifo_0/sim/design_1_m00_data_fifo_0.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_m00_data_fifo_0/sim/design_1_m00_data_fifo_0.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_addr_decode.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_addr_decode.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg_bank.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg_bank.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_ar_channel.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_ar_channel.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_arbiter.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_arbiter.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_fsm.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_fsm.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v
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Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v → Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v
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