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Add FW changes for Rev3 #245

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AleksaBjelogrlic merged 2 commits from FW/Aleksa/TE0712_Rev3_Baseboard into master 2023-04-04 01:57:52 +00:00
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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/README.txt Normal file
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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_auto_cc_0/sim/design_1_auto_cc_0.v Normal file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
// IP Revision: 20
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_cc_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [29 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [255 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [31 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [29 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [255 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
input wire m_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
input wire m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [29 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [255 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [31 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [29 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [255 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_WRITE_\
THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_clock_converter_v2_1_20_axi_clock_converter #(
.C_FAMILY("artix7"),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(30),
.C_AXI_DATA_WIDTH(256),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(1),
.C_AXI_PROTOCOL(0),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule

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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_auto_us_df_0/sim/design_1_auto_us_df_0.v Normal file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 21
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_df_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [3 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [3 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [3 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [3 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 32, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE\
_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [255 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [31 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [255 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 4, NUM_WRITE_OUTSTANDING 4, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_21_top #(
.C_FAMILY("artix7"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(4),
.C_SUPPORTS_ID(1),
.C_AXI_ADDR_WIDTH(64),
.C_S_AXI_DATA_WIDTH(128),
.C_M_AXI_DATA_WIDTH(256),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(1),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule

289
Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_auto_us_df_1/sim/design_1_auto_us_df_1.v Normal file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 21
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_df_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [3 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [3 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [255 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [31 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_21_top #(
.C_FAMILY("artix7"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(4),
.C_SUPPORTS_ID(1),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(128),
.C_M_AXI_DATA_WIDTH(256),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(1),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(4'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(256'H0000000000000000000000000000000000000000000000000000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule

390
Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_datamover_0_0/sim/design_1_axi_datamover_0_0.vhd Normal file
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-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_datamover:5.1
-- IP Revision: 23
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_datamover_v5_1_23;
USE axi_datamover_v5_1_23.axi_datamover;
ENTITY design_1_axi_datamover_0_0 IS
PORT (
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_halt : IN STD_LOGIC;
s2mm_halt_cmplt : OUT STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
s2mm_allow_addr_req : IN STD_LOGIC;
s2mm_addr_req_posted : OUT STD_LOGIC;
s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
s2mm_ld_nxt_len : OUT STD_LOGIC;
s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_datamover_0_0;
ARCHITECTURE design_1_axi_datamover_0_0_arch OF design_1_axi_datamover_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_datamover_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_datamover IS
GENERIC (
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_ARID : INTEGER;
C_M_AXI_MM2S_ID_WIDTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_STSFIFO : INTEGER;
C_MM2S_STSCMD_FIFO_DEPTH : INTEGER;
C_MM2S_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_MM2S_BTT_USED : INTEGER;
C_MM2S_ADDR_PIPE_DEPTH : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_AWID : INTEGER;
C_M_AXI_S2MM_ID_WIDTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_STSFIFO : INTEGER;
C_S2MM_STSCMD_FIFO_DEPTH : INTEGER;
C_S2MM_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_S2MM_BTT_USED : INTEGER;
C_S2MM_SUPPORT_INDET_BTT : INTEGER;
C_S2MM_ADDR_PIPE_DEPTH : INTEGER;
C_FAMILY : STRING;
C_MM2S_INCLUDE_SF : INTEGER;
C_S2MM_INCLUDE_SF : INTEGER;
C_ENABLE_CACHE_USER : INTEGER;
C_ENABLE_MM2S_TKEEP : INTEGER;
C_ENABLE_S2MM_TKEEP : INTEGER;
C_ENABLE_SKID_BUF : STRING;
C_ENABLE_S2MM_ADV_SIG : INTEGER;
C_ENABLE_MM2S_ADV_SIG : INTEGER;
C_CMD_WIDTH : INTEGER
);
PORT (
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_mm2s_aresetn : IN STD_LOGIC;
mm2s_halt : IN STD_LOGIC;
mm2s_halt_cmplt : OUT STD_LOGIC;
mm2s_err : OUT STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
m_axis_mm2s_sts_tready : IN STD_LOGIC;
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
mm2s_allow_addr_req : IN STD_LOGIC;
mm2s_addr_req_posted : OUT STD_LOGIC;
mm2s_rd_xfer_cmplt : OUT STD_LOGIC;
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
mm2s_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mm2s_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_halt : IN STD_LOGIC;
s2mm_halt_cmplt : OUT STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
s2mm_allow_addr_req : IN STD_LOGIC;
s2mm_addr_req_posted : OUT STD_LOGIC;
s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
s2mm_ld_nxt_len : OUT STD_LOGIC;
s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_datamover;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 16, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awuser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awid: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, NUM_WRITE_OUTSTANDING 2, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 4, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WR" &
"ITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_sts_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_CMDSTS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_S2MM_CMDSTS_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_CMDSTS_AWCLK, ASSOCIATED_BUSIF S_AXIS_S2MM_CMD:M_AXIS_S2MM_STS, ASSOCIATED_RESET m_axis_s2mm_cmdsts_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_S2MM_CMDSTS_AWCLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aresetn: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_S2MM_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_ACLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM, ASSOCIATED_RESET m_axi_s2mm_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
BEGIN
U0 : axi_datamover
GENERIC MAP (
C_INCLUDE_MM2S => 0,
C_M_AXI_MM2S_ARID => 0,
C_M_AXI_MM2S_ID_WIDTH => 4,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_STSFIFO => 0,
C_MM2S_STSCMD_FIFO_DEPTH => 4,
C_MM2S_STSCMD_IS_ASYNC => 0,
C_INCLUDE_MM2S_DRE => 0,
C_MM2S_BURST_SIZE => 16,
C_MM2S_BTT_USED => 16,
C_MM2S_ADDR_PIPE_DEPTH => 3,
C_INCLUDE_S2MM => 1,
C_M_AXI_S2MM_AWID => 0,
C_M_AXI_S2MM_ID_WIDTH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 128,
C_S_AXIS_S2MM_TDATA_WIDTH => 128,
C_INCLUDE_S2MM_STSFIFO => 1,
C_S2MM_STSCMD_FIFO_DEPTH => 4,
C_S2MM_STSCMD_IS_ASYNC => 0,
C_INCLUDE_S2MM_DRE => 0,
C_S2MM_BURST_SIZE => 256,
C_S2MM_BTT_USED => 16,
C_S2MM_SUPPORT_INDET_BTT => 0,
C_S2MM_ADDR_PIPE_DEPTH => 4,
C_FAMILY => "artix7",
C_MM2S_INCLUDE_SF => 0,
C_S2MM_INCLUDE_SF => 1,
C_ENABLE_CACHE_USER => 0,
C_ENABLE_MM2S_TKEEP => 1,
C_ENABLE_S2MM_TKEEP => 1,
C_ENABLE_SKID_BUF => "11111",
C_ENABLE_S2MM_ADV_SIG => 1,
C_ENABLE_MM2S_ADV_SIG => 0,
C_CMD_WIDTH => 72
)
PORT MAP (
m_axi_mm2s_aclk => '0',
m_axi_mm2s_aresetn => '1',
mm2s_halt => '0',
m_axis_mm2s_cmdsts_aclk => '0',
m_axis_mm2s_cmdsts_aresetn => '1',
s_axis_mm2s_cmd_tvalid => '0',
s_axis_mm2s_cmd_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 72)),
m_axis_mm2s_sts_tready => '0',
mm2s_allow_addr_req => '1',
m_axi_mm2s_arready => '0',
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_mm2s_rlast => '0',
m_axi_mm2s_rvalid => '0',
m_axis_mm2s_tready => '0',
mm2s_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn,
s2mm_halt => s2mm_halt,
s2mm_halt_cmplt => s2mm_halt_cmplt,
s2mm_err => s2mm_err,
m_axis_s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk,
m_axis_s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata,
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep,
m_axis_s2mm_sts_tlast => m_axis_s2mm_sts_tlast,
s2mm_allow_addr_req => s2mm_allow_addr_req,
s2mm_addr_req_posted => s2mm_addr_req_posted,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt,
s2mm_ld_nxt_len => s2mm_ld_nxt_len,
s2mm_wr_len => s2mm_wr_len,
m_axi_s2mm_awid => m_axi_s2mm_awid,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awuser => m_axi_s2mm_awuser,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s2mm_dbg_sel => s2mm_dbg_sel,
s2mm_dbg_data => s2mm_dbg_data
);
END design_1_axi_datamover_0_0_arch;

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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/sim/design_1_axi_fifo_mm_s_0_0.vhd Normal file
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-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
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-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_fifo_mm_s:4.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_fifo_mm_s_v4_2_3;
USE axi_fifo_mm_s_v4_2_3.axi_fifo_mm_s;
ENTITY design_1_axi_fifo_mm_s_0_0 IS
PORT (
interrupt : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
axi_str_txd_tvalid : OUT STD_LOGIC;
axi_str_txd_tready : IN STD_LOGIC;
axi_str_txd_tlast : OUT STD_LOGIC;
axi_str_txd_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_fifo_mm_s_0_0;
ARCHITECTURE design_1_axi_fifo_mm_s_0_0_arch OF design_1_axi_fifo_mm_s_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_fifo_mm_s_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_fifo_mm_s IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_TX_FIFO_DEPTH : INTEGER;
C_RX_FIFO_DEPTH : INTEGER;
C_TX_CASCADE_HEIGHT : INTEGER;
C_RX_CASCADE_HEIGHT : INTEGER;
C_TX_FIFO_PF_THRESHOLD : INTEGER;
C_TX_FIFO_PE_THRESHOLD : INTEGER;
C_RX_FIFO_PF_THRESHOLD : INTEGER;
C_RX_FIFO_PE_THRESHOLD : INTEGER;
C_USE_TX_CUT_THROUGH : INTEGER;
C_DATA_INTERFACE_TYPE : INTEGER;
C_BASEADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_HIGHADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_AXI4_BASEADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_AXI4_HIGHADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_USE_RX_CUT_THROUGH : INTEGER;
C_USE_TX_DATA : INTEGER;
C_USE_TX_CTRL : INTEGER;
C_USE_RX_DATA : INTEGER
);
PORT (
interrupt : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
axi_str_txd_tvalid : OUT STD_LOGIC;
axi_str_txd_tready : IN STD_LOGIC;
axi_str_txd_tlast : OUT STD_LOGIC;
axi_str_txd_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txd_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axi_str_txd_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txd_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txd_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txd_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
axi_str_txc_tvalid : OUT STD_LOGIC;
axi_str_txc_tready : IN STD_LOGIC;
axi_str_txc_tlast : OUT STD_LOGIC;
axi_str_txc_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txc_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axi_str_txc_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txc_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txc_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_txc_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
axi_str_rxd_tvalid : IN STD_LOGIC;
axi_str_rxd_tready : OUT STD_LOGIC;
axi_str_rxd_tlast : IN STD_LOGIC;
axi_str_rxd_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_rxd_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
axi_str_rxd_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_rxd_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_rxd_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_str_rxd_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT axi_fifo_mm_s;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TLAST";
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_str_txd_tvalid: SIGNAL IS "XIL_INTERFACENAME AXI_STR_TXD, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME rst_axi_str_txd, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 rst_axi_str_txd RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_" &
"THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME rst_s_axi, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 rst_s_axi RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME aclk_s_axi, ASSOCIATED_BUSIF S_AXI:S_AXI_FULL:AXI_STR_TXD:AXI_STR_TXC:AXI_STR_RXD, ASSOCIATED_RESET s_axi_aresetn:mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n:s2mm_prmry_reset_out_n, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_s_axi CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF interrupt: SIGNAL IS "XIL_INTERFACENAME interrupt_intf, SENSITIVITY LEVEL_HIGH, PortWidth 1";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_intf INTERRUPT";
BEGIN
U0 : axi_fifo_mm_s
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ID_WIDTH => 4,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_DATA_WIDTH => 32,
C_TX_FIFO_DEPTH => 512,
C_RX_FIFO_DEPTH => 512,
C_TX_CASCADE_HEIGHT => 0,
C_RX_CASCADE_HEIGHT => 0,
C_TX_FIFO_PF_THRESHOLD => 507,
C_TX_FIFO_PE_THRESHOLD => 5,
C_RX_FIFO_PF_THRESHOLD => 507,
C_RX_FIFO_PE_THRESHOLD => 5,
C_USE_TX_CUT_THROUGH => 0,
C_DATA_INTERFACE_TYPE => 0,
C_BASEADDR => X"40020000",
C_HIGHADDR => X"4002FFFF",
C_AXI4_BASEADDR => X"80001000",
C_AXI4_HIGHADDR => X"80002FFF",
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TID_WIDTH => 4,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_USE_RX_CUT_THROUGH => 0,
C_USE_TX_DATA => 1,
C_USE_TX_CTRL => 0,
C_USE_RX_DATA => 0
)
PORT MAP (
interrupt => interrupt,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
axi_str_txd_tvalid => axi_str_txd_tvalid,
axi_str_txd_tready => axi_str_txd_tready,
axi_str_txd_tlast => axi_str_txd_tlast,
axi_str_txd_tdata => axi_str_txd_tdata,
axi_str_txc_tready => '0',
axi_str_rxd_tvalid => '0',
axi_str_rxd_tlast => '0',
axi_str_rxd_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_str_rxd_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
axi_str_rxd_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_str_rxd_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_str_rxd_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_str_rxd_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4))
);
END design_1_axi_fifo_mm_s_0_0_arch;

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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_gpio_0_1/sim/design_1_axi_gpio_0_1.vhd Normal file
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--
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-- laws.
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--
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-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 23
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_23;
USE axi_gpio_v2_0_23.axi_gpio;
ENTITY design_1_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_gpio_0_1;
ARCHITECTURE design_1_axi_gpio_0_1_arch OF design_1_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T" &
"HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 32,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
gpio_io_o => gpio_io_o,
gpio2_io_i => gpio2_io_i
);
END design_1_axi_gpio_0_1_arch;

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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_axi_gpio_1_0/sim/design_1_axi_gpio_1_0.vhd Normal file
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-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 23
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_23;
USE axi_gpio_v2_0_23.axi_gpio;
ENTITY design_1_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_gpio_1_0;
ARCHITECTURE design_1_axi_gpio_1_0_arch OF design_1_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T" &
"HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 32,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
gpio_io_o => gpio_io_o,
gpio2_io_i => gpio2_io_i
);
END design_1_axi_gpio_1_0_arch;

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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v Normal file
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// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__200.00000______0.000______50.0______109.241_____96.948
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "design_1_clk_wiz_0_0,clk_wiz_v6_0_5_0_0,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=8.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module design_1_clk_wiz_0_0
(
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input clk_in1
);
design_1_clk_wiz_0_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.resetn(resetn),
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule

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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v Normal file
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// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__200.00000______0.000______50.0______109.241_____96.948
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
module design_1_clk_wiz_0_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_design_1_clk_wiz_0_0;
wire clk_in2_design_1_clk_wiz_0_0;
assign clk_in1_design_1_clk_wiz_0_0 = clk_in1;
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_design_1_clk_wiz_0_0;
wire clk_out2_design_1_clk_wiz_0_0;
wire clk_out3_design_1_clk_wiz_0_0;
wire clk_out4_design_1_clk_wiz_0_0;
wire clk_out5_design_1_clk_wiz_0_0;
wire clk_out6_design_1_clk_wiz_0_0;
wire clk_out7_design_1_clk_wiz_0_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_design_1_clk_wiz_0_0;
wire clkfbout_buf_design_1_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (8.000))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
.I (clkfbout_design_1_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_design_1_clk_wiz_0_0));
endmodule

418
Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_m00_data_fifo_0/sim/design_1_m00_data_fifo_0.v Normal file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_data_fifo:2.1
// IP Revision: 20
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_m00_data_fifo_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [29 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [255 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [31 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [29 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [255 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [29 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [255 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [31 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [29 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [255 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_data_fifo_v2_1_20_axi_data_fifo #(
.C_FAMILY("artix7"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(30),
.C_AXI_DATA_WIDTH(256),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_WRITE_FIFO_DEPTH(512),
.C_AXI_WRITE_FIFO_TYPE("bram"),
.C_AXI_WRITE_FIFO_DELAY(1),
.C_AXI_READ_FIFO_DEPTH(512),
.C_AXI_READ_FIFO_TYPE("bram"),
.C_AXI_READ_FIFO_DELAY(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_ecc_top.v
//
// Description:
//
// Specifications:
//
// Structure:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_ctrl_addr_decode #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_RDWR_ARRAY = 5'b00101
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire [C_ADDR_WIDTH-1:0] axaddr ,
// Slave Interface Write Data Ports
output wire [C_NUM_REG_WIDTH-1:0] reg_decode_num
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
function [C_ADDR_WIDTH-1:0] calc_bit_mask (
input [C_NUM_REG*C_ADDR_WIDTH-1:0] addr_decode_array
);
begin : func_calc_bit_mask
integer i;
reg [C_ADDR_WIDTH-1:0] first_addr;
reg [C_ADDR_WIDTH-1:0] bit_mask;
calc_bit_mask = {C_ADDR_WIDTH{1'b0}};
first_addr = addr_decode_array[C_ADDR_WIDTH+:C_ADDR_WIDTH];
for (i = 2; i < C_NUM_REG; i = i + 1) begin
bit_mask = first_addr ^ addr_decode_array[C_ADDR_WIDTH*i +: C_ADDR_WIDTH];
calc_bit_mask = calc_bit_mask | bit_mask;
end
end
endfunction
function integer lsb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_lsb_mask_index
lsb_mask_index = 0;
while ((lsb_mask_index < C_ADDR_WIDTH-1) && ~mask[lsb_mask_index]) begin
lsb_mask_index = lsb_mask_index + 1;
end
end
endfunction
function integer msb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_msb_mask_index
msb_mask_index = C_ADDR_WIDTH-1;
while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin
msb_mask_index = msb_mask_index - 1;
end
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_ADDR_BIT_MASK = calc_bit_mask(C_REG_ADDR_ARRAY);
localparam P_MASK_LSB = lsb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_MSB = msb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_WIDTH = P_MASK_MSB - P_MASK_LSB + 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
integer i;
(* rom_extract = "no" *)
reg [C_NUM_REG_WIDTH-1:0] reg_decode_num_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(*) begin
reg_decode_num_i = {C_NUM_REG_WIDTH{1'b0}};
for (i = 1; i < C_NUM_REG; i = i + 1) begin : decode_addr
if ((axaddr[P_MASK_MSB:P_MASK_LSB] == C_REG_ADDR_ARRAY[i*C_ADDR_WIDTH+P_MASK_LSB+:P_MASK_WIDTH])
&& C_REG_RDWR_ARRAY[i] ) begin
reg_decode_num_i = i[C_NUM_REG_WIDTH-1:0];
end
end
end
assign reg_decode_num = reg_decode_num_i;
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_read.v
//
// Description:
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_ctrl_read #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter integer C_DATA_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_RDAC_ARRAY = 5'b11111
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ADDR_WIDTH-1:0] araddr ,
// Slave Interface Read Data Ports
output wire rvalid ,
input wire rready ,
output wire [C_DATA_WIDTH-1:0] rdata ,
output wire [1:0] rresp ,
input wire pending ,
// MC Internal Signals
input wire [C_DATA_WIDTH*C_NUM_REG-1:0] reg_bank_array
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_NUM_REG_WIDTH-1:0] reg_decode_num;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
mig_7series_v4_2_axi_ctrl_addr_decode #
(
.C_ADDR_WIDTH ( C_ADDR_WIDTH ) ,
.C_NUM_REG ( C_NUM_REG ) ,
.C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) ,
.C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) ,
.C_REG_RDWR_ARRAY ( C_REG_RDAC_ARRAY )
)
axi_ctrl_addr_decode_0
(
.axaddr ( araddr ) ,
.reg_decode_num ( reg_decode_num )
);
assign rdata = reg_bank_array[ reg_decode_num*32+:32];
assign rresp = 2'b0; // Okay
assign rvalid = pending;
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_reg.v
//
// Description:
// This is just a general register. It has two write enables and two data ins
// to simplify the operation. Typically one write enable (we) comes from the
// external interface and the second write enable is used for internal writing
// to the register. A mask parameter is used to only write to the bits that
// are used in the register.
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_ctrl_reg #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_REG_WIDTH = 32,
parameter integer C_DATA_WIDTH = 32,
parameter C_INIT = 32'h0,
parameter C_MASK = 32'h1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_REG_WIDTH-1:0] data_in ,
input wire we ,
input wire we_int ,
input wire [C_REG_WIDTH-1:0] data_in_int ,
output wire [C_DATA_WIDTH-1:0] data_out
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [C_REG_WIDTH-1:0] data;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
data <= C_INIT[0+:C_REG_WIDTH];
end
else if (we) begin
data <= data_in;
end
else if (we_int) begin
data <= data_in_int;
end
else begin
data <= data;
end
end
// Does not supprot case where P_MASK_LSB > 0
generate
if (C_REG_WIDTH == C_DATA_WIDTH) begin : assign_no_zero_pad
assign data_out = data;
end
else begin : assign_zero_pad
assign data_out = {{C_DATA_WIDTH-C_REG_WIDTH{1'b0}}, data};
end
endgenerate
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
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// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
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///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_ecc_top.v
//
// Description:
//
// Specifications:
//
// Structure:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_ctrl_reg_bank #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter C_ADDR_WIDTH = 32,
parameter C_DATA_WIDTH = 32,
parameter C_DQ_WIDTH = 72,
parameter C_ECC_CE_COUNTER_WIDTH = 8,
parameter C_ECC_ONOFF_RESET_VALUE = 1,
parameter C_ECC_TEST = "ON",
parameter C_ECC_WIDTH = 8,
parameter C_MC_ERR_ADDR_WIDTH = 28,
parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// # of memory Bank Address bits.
parameter C_BANK_WIDTH = 3,
// # of memory Row Address bits.
parameter C_ROW_WIDTH = 14,
// # of memory Column Address bits.
parameter C_COL_WIDTH = 10,
parameter C_NCK_PER_CLK = 2,
parameter C_NUM_REG = 24,
parameter C_NUM_REG_WIDTH = 5,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Register arrays
parameter C_REG_WIDTH_ARRAY = 160'h0,
parameter C_REG_RDAC_ARRAY = 5'b0,
parameter C_REG_WRAC_ARRAY = 5'b0,
parameter C_REG_INIT_ARRAY = 160'h0,
parameter C_REG_MASK_ARRAY = 160'h0,
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
// Register Indices
parameter integer C_REG_FI_ECC_INDX = 23,
parameter integer C_REG_FI_D_127_96_INDX = 22,
parameter integer C_REG_FI_D_95_64_INDX = 21,
parameter integer C_REG_FI_D_63_32_INDX = 20,
parameter integer C_REG_FI_D_31_00_INDX = 19,
parameter integer C_REG_UE_FFA_63_32_INDX = 18,
parameter integer C_REG_UE_FFA_31_00_INDX = 17,
parameter integer C_REG_UE_FFE_INDX = 16,
parameter integer C_REG_UE_FFD_127_96_INDX = 15,
parameter integer C_REG_UE_FFD_95_64_INDX = 14,
parameter integer C_REG_UE_FFD_63_32_INDX = 13,
parameter integer C_REG_UE_FFD_31_00_INDX = 12,
parameter integer C_REG_CE_FFA_63_32_INDX = 11,
parameter integer C_REG_CE_FFA_31_00_INDX = 10,
parameter integer C_REG_CE_FFE_INDX = 9 ,
parameter integer C_REG_CE_FFD_127_96_INDX = 8 ,
parameter integer C_REG_CE_FFD_95_64_INDX = 7 ,
parameter integer C_REG_CE_FFD_63_32_INDX = 6 ,
parameter integer C_REG_CE_FFD_31_00_INDX = 5 ,
parameter integer C_REG_CE_CNT_INDX = 4 ,
parameter integer C_REG_ECC_ON_OFF_INDX = 3 ,
parameter integer C_REG_ECC_EN_IRQ_INDX = 2 ,
parameter integer C_REG_ECC_STATUS_INDX = 1 ,
parameter integer C_REG_DUMMY_INDX = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
input wire [C_NUM_REG_WIDTH-1:0] reg_data_sel ,
input wire reg_data_write ,
input wire [C_DATA_WIDTH-1:0] reg_data_in ,
output wire [C_DATA_WIDTH*C_NUM_REG-1:0] reg_data_out ,
output wire interrupt ,
input wire [2*C_NCK_PER_CLK-1:0] ecc_single ,
input wire [2*C_NCK_PER_CLK-1:0] ecc_multiple ,
input wire [C_MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr ,
output wire app_correct_en ,
input wire [2*C_NCK_PER_CLK*C_DQ_WIDTH-1:0] dfi_rddata ,
output wire [C_DQ_WIDTH/8-1:0] fi_xor_we ,
output wire [C_DQ_WIDTH-1:0] fi_xor_wrdata
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_FI_XOR_WE_WIDTH = (C_DQ_WIDTH%C_DATA_WIDTH)/8;
localparam P_SHIFT_BY = C_DQ_WIDTH == 72 ? 3 : 4;
localparam P_CS_WIDTH = C_MC_ERR_ADDR_WIDTH - C_COL_WIDTH - C_ROW_WIDTH - C_BANK_WIDTH - 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
integer beat;
reg [C_DQ_WIDTH-1:0] ffs;
reg [C_DQ_WIDTH-1:0] ffm;
wire [7:0] ecc_single_expanded;
wire [7:0] ecc_multiple_expanded;
reg [C_S_AXI_ADDR_WIDTH-1:0] ffas;
reg [C_S_AXI_ADDR_WIDTH-1:0] ffam;
reg [2:0] ffas_lsb;
reg [2:0] ffam_lsb;
wire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_real;
wire ecc_err_addr_offset;
wire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_swap_row_bank;
wire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_swapped;
wire [C_NUM_REG-1:0] we;
wire [C_DATA_WIDTH*C_NUM_REG-1:0] data_in;
wire [C_NUM_REG-1:0] we_int;
wire [C_DATA_WIDTH*C_NUM_REG-1:0] data_in_int;
wire [C_DATA_WIDTH*C_NUM_REG-1:0] data_out;
reg interrupt_r;
reg ecc_on_off_r;
reg ce_clr_r;
reg ue_clr_r;
wire ce_set_i;
wire ue_set_i;
reg [C_DQ_WIDTH/8-1:0] fi_xor_we_r;
reg [C_DQ_WIDTH-1:0] fi_xor_wrdata_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Assign outputs
assign reg_data_out = data_out;
assign interrupt = interrupt_r & ecc_on_off_r;
assign app_correct_en = ecc_on_off_r;
assign fi_xor_wrdata = fi_xor_wrdata_r;
assign fi_xor_we = fi_xor_we_r & {C_DQ_WIDTH/8{ecc_on_off_r}};
// Calculate inputs
// Always block selects the first failing beat out C_NCK_PER_CLK*2 beats. If
// no failing beats, default to last beat.
always @(*) begin
ffs = dfi_rddata[(C_NCK_PER_CLK*2-1)*C_DQ_WIDTH+:C_DQ_WIDTH];
ffm = dfi_rddata[(C_NCK_PER_CLK*2-1)*C_DQ_WIDTH+:C_DQ_WIDTH];
for( beat = C_NCK_PER_CLK*2-2; beat >= 0 ; beat = beat - 1) begin : find_first_failing_beat
if (ecc_single[beat]) begin
ffs = dfi_rddata[beat*C_DQ_WIDTH+:C_DQ_WIDTH];
// ffas_lsb = beat[2:0]; // | {ecc_err_addr_offset| ecc_err_addr_real[2], 2'b0};
end
if (ecc_multiple[beat]) begin
ffm = dfi_rddata[beat*C_DQ_WIDTH+:C_DQ_WIDTH];
// ffam_lsb = beat[2:0]; // | {ecc_err_addr_offset| ecc_err_addr_real[2], 2'b0};
end
end
end
generate
if (C_NCK_PER_CLK == 2) begin : ecc_zero_extened
assign ecc_single_expanded = {4'b0, ecc_single[3:0]};
assign ecc_multiple_expanded = {4'b0, ecc_multiple[3:0]};
end
else begin : no_ecc_zero_extend
assign ecc_single_expanded = ecc_single[7:0];
assign ecc_multiple_expanded = ecc_multiple[7:0];
end
endgenerate
always @(*) begin
(* full_case *) (* parallel_case *)
casex (ecc_single_expanded)
8'bxxxx_xxx1:
ffas_lsb = 3'o0;
8'bxxxx_xx10:
ffas_lsb = 3'o1;
8'bxxxx_x100:
ffas_lsb = 3'o2;
8'bxxxx_1000:
ffas_lsb = 3'o3;
8'bxxx1_0000:
ffas_lsb = 3'o4;
8'bxx10_0000:
ffas_lsb = 3'o5;
8'bx100_0000:
ffas_lsb = 3'o6;
8'b1000_0000:
ffas_lsb = 3'o7;
default:
ffas_lsb = 3'o0;
endcase
end
always @(*) begin
(* full_case *) (* parallel_case *)
casex (ecc_multiple_expanded)
8'bxxxx_xxx1:
ffam_lsb = 3'o0;
8'bxxxx_xx10:
ffam_lsb = 3'o1;
8'bxxxx_x100:
ffam_lsb = 3'o2;
8'bxxxx_1000:
ffam_lsb = 3'o3;
8'bxxx1_0000:
ffam_lsb = 3'o4;
8'bxx10_0000:
ffam_lsb = 3'o5;
8'bx100_0000:
ffam_lsb = 3'o6;
8'b1000_0000:
ffam_lsb = 3'o7;
default:
ffam_lsb = 3'o0;
endcase
end
// Calculate first failing address
// Split ecc_err_addr, lower bit of ecc_err_addr is the offset, and not part
// of the column address.
assign ecc_err_addr_real[C_MC_ERR_ADDR_WIDTH-2:3] = ecc_err_addr[C_MC_ERR_ADDR_WIDTH-1:4];
// if ecc_err_addr[0] == 1, then the error is on the 2nd 4 beats of BL8.
assign ecc_err_addr_real[2] = ecc_err_addr[3] | ecc_err_addr[0];
// Lower two bits always expected to be 0b00
assign ecc_err_addr_real[1:0] = ecc_err_addr[2:1];
// Swap Row Bank bits if we need it. Special case for no cs bits.
assign ecc_err_addr_swap_row_bank[C_COL_WIDTH+:C_ROW_WIDTH+C_BANK_WIDTH] =
{ecc_err_addr_real[C_COL_WIDTH+:C_ROW_WIDTH], ecc_err_addr_real[C_COL_WIDTH+C_ROW_WIDTH+:C_BANK_WIDTH]};
assign ecc_err_addr_swap_row_bank[0+:C_COL_WIDTH] = ecc_err_addr_real[0+:C_COL_WIDTH];
generate
begin
if (P_CS_WIDTH > 0) begin : CS_WIDTH_ASSIGN
assign ecc_err_addr_swap_row_bank[C_COL_WIDTH+C_ROW_WIDTH+C_BANK_WIDTH+:P_CS_WIDTH] =
ecc_err_addr_real[C_COL_WIDTH+C_ROW_WIDTH+C_BANK_WIDTH+:P_CS_WIDTH];
end
end
endgenerate
// swap row/bank if necessary
assign ecc_err_addr_swapped = (C_MEM_ADDR_ORDER == "BANK_ROW_COLUMN") ? ecc_err_addr_real : ecc_err_addr_swap_row_bank;
// Assign final result
always @(*) begin
ffas = ({ecc_err_addr_swapped[3+:C_MC_ERR_ADDR_WIDTH-4], (ffas_lsb[2] | ecc_err_addr_real[2]), ffas_lsb[1:0]}
<< P_SHIFT_BY) | C_S_AXI_BASEADDR;
ffam = ({ecc_err_addr_swapped[3+:C_MC_ERR_ADDR_WIDTH-4], (ffam_lsb[2] | ecc_err_addr_real[2]), ffam_lsb[1:0]}
<< P_SHIFT_BY) | C_S_AXI_BASEADDR;
end
generate
genvar i;
genvar j;
for (i = 0; i < C_NUM_REG; i = i + 1) begin : inst_reg
if (C_REG_MASK_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] > 0) begin
mig_7series_v4_2_axi_ctrl_reg #
(
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_REG_WIDTH ( C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]) ,
.C_INIT ( C_REG_INIT_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] ) ,
.C_MASK ( C_REG_MASK_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] )
)
axi_ctrl_reg
(
.clk ( clk ) ,
.reset ( reset ) ,
.data_in ( data_in[i*C_DATA_WIDTH+:C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]] ) ,
.we ( we[i] ) ,
.data_in_int ( data_in_int[i*C_DATA_WIDTH+:C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]] ) ,
.we_int ( we_int[i] ) ,
.data_out ( data_out[i*C_DATA_WIDTH+:C_DATA_WIDTH] )
);
end
else begin : no_reg
assign data_out[i*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
end
// Determine write logic for each register
for (j = 0; j < C_NUM_REG; j = j + 1) begin : inst_reg_logic_
case (j)
C_REG_ECC_STATUS_INDX:
begin
// Bit Name Desc
// 1 CE_STATUS If '1' a correctable error has occurred. Cleared when '1' is written to this bit
// position.
// 0 UE_STATUS If '1' a uncorrectable error has occurred. Cleared when '1' is written to this bit
// position.
assign we[j] = (reg_data_sel == j) && reg_data_write;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ~reg_data_in & data_out[j*C_DATA_WIDTH+:C_DATA_WIDTH];
assign we_int[j] = ecc_on_off_r;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {30'b0, (|ecc_single | data_out[j*C_DATA_WIDTH + 1]),
(|ecc_multiple | data_out[j*C_DATA_WIDTH + 0])};
// Drive internal signals to write to other registers
always @(posedge clk) begin
ce_clr_r <= ~data_in[j*C_DATA_WIDTH + 1] & we[j];
ue_clr_r <= ~data_in[j*C_DATA_WIDTH + 0] & we[j];
end
assign ce_set_i = data_in_int[j*C_DATA_WIDTH + 1] & we_int[j] & ~data_out[j*C_DATA_WIDTH + 1];
assign ue_set_i = data_in_int[j*C_DATA_WIDTH + 0] & we_int[j] & ~data_out[j*C_DATA_WIDTH + 0];
end
C_REG_ECC_EN_IRQ_INDX:
begin
// Bit Name Desc
// 1 CE_EN_IRQ If '1' the value of the CE_STATUS bit of ECC Status Register will be propagated to the
// Interrupt signal. If '0' the value of the CE_STATUS bit of ECC Status Register will not
// be propagated to the Interrupt signal.
// position.
// 0 UE_EN_IRQ See above
//
assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in;
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
always @(posedge clk) begin
interrupt_r <= |(data_out[j*C_DATA_WIDTH+:C_DATA_WIDTH]
& data_out[C_REG_ECC_STATUS_INDX*C_DATA_WIDTH+:C_DATA_WIDTH]);
end
end
C_REG_ECC_ON_OFF_INDX:
begin
// Bit Name Desc
// 0 ECC_ON_OFF If '0', ECC checking is disable on read operations. If '1', ECC checking is enabled on
// read operations. All correctable and uncorrectable error condtions will be captured
// and status updated.
assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in;
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
always @(posedge clk) begin
ecc_on_off_r <= data_out[j*C_DATA_WIDTH+0];
end
end
C_REG_CE_CNT_INDX:
begin
// Bit Name Desc
// 7:0 CE_CNT Register holds number of correctable errors encountered.
assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in;
assign data_in_int[j*C_DATA_WIDTH+:C_ECC_CE_COUNTER_WIDTH+1]
= data_out[j*C_DATA_WIDTH+:C_ECC_CE_COUNTER_WIDTH+1] + 1'b1;
assign data_in_int[j*C_DATA_WIDTH+C_ECC_CE_COUNTER_WIDTH+1+:C_DATA_WIDTH-(C_ECC_CE_COUNTER_WIDTH+1)]
= {C_DATA_WIDTH-(C_ECC_CE_COUNTER_WIDTH+1){1'b0}};
// Only write if there is an error and it will not cause an overflow
assign we_int[j] = ecc_on_off_r & (|ecc_single) & ~data_in_int[j*C_DATA_WIDTH + C_ECC_CE_COUNTER_WIDTH];
end
C_REG_CE_FFD_31_00_INDX:
begin
assign we[j] = ce_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ce_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[0*C_DATA_WIDTH+:C_DATA_WIDTH];
end
C_REG_CE_FFD_63_32_INDX:
begin
assign we[j] = ce_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ce_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[1*C_DATA_WIDTH+:C_DATA_WIDTH];
end
C_REG_CE_FFD_95_64_INDX:
begin
if (C_DQ_WIDTH == 144) begin
assign we[j] = ce_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ce_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[2*C_DATA_WIDTH+:C_DATA_WIDTH];
end
else begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
end
C_REG_CE_FFD_127_96_INDX:
begin
if (C_DQ_WIDTH == 144) begin
assign we[j] = ce_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ce_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[3*C_DATA_WIDTH+:C_DATA_WIDTH];
end
else begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
end
C_REG_CE_FFE_INDX:
begin
assign we[j] = ce_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ce_set_i;
if (C_DQ_WIDTH == 144) begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffs[128+:C_ECC_WIDTH] };
end
else begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffs[ 64+:C_ECC_WIDTH] };
end
end
C_REG_CE_FFA_31_00_INDX:
begin
assign we[j] = ce_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ce_set_i;
if (C_S_AXI_ADDR_WIDTH < C_DATA_WIDTH) begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{(C_DATA_WIDTH-C_S_AXI_ADDR_WIDTH){1'b0}}, ffas[0*C_DATA_WIDTH+:C_S_AXI_ADDR_WIDTH]};
end else begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffas[0*C_DATA_WIDTH+:C_DATA_WIDTH];
end
end
C_REG_CE_FFA_63_32_INDX:
begin
assign we[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ce_clr_r : 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ce_set_i : 1'b0;
if (C_S_AXI_ADDR_WIDTH > C_DATA_WIDTH) begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{((2*C_DATA_WIDTH)-C_S_AXI_ADDR_WIDTH){1'b0}}, ffas[C_DATA_WIDTH+:(C_S_AXI_ADDR_WIDTH-C_DATA_WIDTH)]};
end else begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
end
C_REG_UE_FFD_31_00_INDX:
begin
assign we[j] = ue_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ue_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[0*C_DATA_WIDTH+:C_DATA_WIDTH];
end
C_REG_UE_FFD_63_32_INDX:
begin
assign we[j] = ue_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ue_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[1*C_DATA_WIDTH+:C_DATA_WIDTH];
end
C_REG_UE_FFD_95_64_INDX:
begin
if (C_DQ_WIDTH == 144) begin
assign we[j] = ue_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ue_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[2*C_DATA_WIDTH+:C_DATA_WIDTH];
end
else begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
end
C_REG_UE_FFD_127_96_INDX:
begin
if (C_DQ_WIDTH == 144) begin
assign we[j] = ue_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ue_set_i;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[3*C_DATA_WIDTH+:C_DATA_WIDTH];
end
else begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
end
C_REG_UE_FFE_INDX:
begin
assign we[j] = ue_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ue_set_i;
if (C_DQ_WIDTH == 144) begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffm[128+:C_ECC_WIDTH] };
end
else begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffm[ 64+:C_ECC_WIDTH] };
end
end
C_REG_UE_FFA_31_00_INDX:
begin
assign we[j] = ue_clr_r;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = ue_set_i;
if (C_S_AXI_ADDR_WIDTH < C_DATA_WIDTH) begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{(C_DATA_WIDTH-C_S_AXI_ADDR_WIDTH){1'b0}}, ffam[0*C_DATA_WIDTH+:C_S_AXI_ADDR_WIDTH]};
end else begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffam[0*C_DATA_WIDTH+:C_DATA_WIDTH];
end
end
C_REG_UE_FFA_63_32_INDX:
begin
assign we[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ue_clr_r : 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ue_set_i : 1'b0;
if (C_S_AXI_ADDR_WIDTH > C_DATA_WIDTH) begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{((2*C_DATA_WIDTH)-C_S_AXI_ADDR_WIDTH){1'b0}}, ffam[C_DATA_WIDTH+:(C_S_AXI_ADDR_WIDTH-C_DATA_WIDTH)]};
end else begin
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
end
C_REG_FI_D_31_00_INDX:
begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
//if (C_ECC_TEST == "ON") begin
always @(posedge clk) begin
fi_xor_we_r[0*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}}
: {C_DATA_WIDTH/8{1'b0}};
fi_xor_wrdata_r[0*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];
end
//end
end
C_REG_FI_D_63_32_INDX:
begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
//if (C_ECC_TEST == "ON") begin
always @(posedge clk) begin
fi_xor_we_r[1*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}}
: {C_DATA_WIDTH/8{1'b0}};
fi_xor_wrdata_r[1*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];
end
//end
end
C_REG_FI_D_95_64_INDX:
begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == "ON"*/) begin
always @(posedge clk) begin
fi_xor_we_r[2*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}}
: {C_DATA_WIDTH/8{1'b0}};
fi_xor_wrdata_r[2*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];
end
end
end
C_REG_FI_D_127_96_INDX:
begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == "ON"*/) begin
always @(posedge clk) begin
fi_xor_we_r[3*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}}
: {C_DATA_WIDTH/8{1'b0}};
fi_xor_wrdata_r[3*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];
end
end
end
C_REG_FI_ECC_INDX:
begin
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
if (C_DQ_WIDTH == 72 /*&& C_ECC_TEST == "ON"*/) begin
always @(posedge clk) begin
fi_xor_we_r[2*C_DATA_WIDTH/8+:P_FI_XOR_WE_WIDTH] <= (reg_data_sel == j) ? {P_FI_XOR_WE_WIDTH{reg_data_write}}
: {P_FI_XOR_WE_WIDTH{1'b0}};
fi_xor_wrdata_r[2*C_DATA_WIDTH+:C_DQ_WIDTH%C_DATA_WIDTH] <= reg_data_in[C_DQ_WIDTH%C_DATA_WIDTH-1:0];
end
end
if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == "ON"*/) begin
always @(posedge clk) begin
fi_xor_we_r[4*C_DATA_WIDTH/8+:P_FI_XOR_WE_WIDTH] <= (reg_data_sel == j) ? {P_FI_XOR_WE_WIDTH{reg_data_write}}
: {P_FI_XOR_WE_WIDTH{1'b0}};
fi_xor_wrdata_r[4*C_DATA_WIDTH+:C_DQ_WIDTH%C_DATA_WIDTH] <= reg_data_in[C_DQ_WIDTH%C_DATA_WIDTH-1:0];
end
end
end
default:
begin
// Tie off reg inputs
assign we[j] = 1'b0;
assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
assign we_int[j] = 1'b0;
assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};
end
endcase
end
endgenerate
endmodule
`default_nettype wire

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Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v Normal file
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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_top.v
//
// Description:
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_ctrl_top #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter integer C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4 Memory Mapped address bus
parameter integer C_S_AXI_ADDR_WIDTH = 32,
// Width of AXI-4 Memory Mapped address bus
parameter integer C_S_AXI_BASEADDR = 32'h0000_0000,
// Enable or disable fault injection logic test hardware.
parameter C_ECC_TEST = "ON",
// External Memory Data Width
parameter integer C_DQ_WIDTH = 72,
// Memory ECC Width
parameter integer C_ECC_WIDTH = 8,
// Memory Address Order
parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// # of memory Bank Address bits.
parameter C_BANK_WIDTH = 3,
// # of memory Row Address bits.
parameter C_ROW_WIDTH = 14,
// # of memory Column Address bits.
parameter C_COL_WIDTH = 10,
// Controls ECC on/off value at startup/reset
parameter integer C_ECC_ONOFF_RESET_VALUE = 1,
// Controls CE counter width
parameter integer C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
parameter integer C_NCK_PER_CLK = 2,
parameter C_MC_ERR_ADDR_WIDTH = 28
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire s_axi_awvalid ,
output wire s_axi_awready ,
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_awaddr ,
// Slave Interface Write Data Ports
input wire s_axi_wvalid ,
output wire s_axi_wready ,
input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_wdata ,
// Slave Interface Write Response Ports
output wire s_axi_bvalid ,
input wire s_axi_bready ,
output wire [1:0] s_axi_bresp ,
// Slave Interface Read Address Ports
input wire s_axi_arvalid ,
output wire s_axi_arready ,
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_araddr ,
// Slave Interface Read Data Ports
output wire s_axi_rvalid ,
input wire s_axi_rready ,
output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
// Interrupt output
output wire interrupt ,
// MC Internal Signals
input wire init_complete ,
input wire [2*C_NCK_PER_CLK-1:0] ecc_single ,
input wire [2*C_NCK_PER_CLK-1:0] ecc_multiple ,
input wire [C_MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr ,
output wire app_correct_en ,
input wire [2*C_NCK_PER_CLK*C_DQ_WIDTH-1:0] dfi_rddata ,
output wire [C_DQ_WIDTH/8-1:0] fi_xor_we ,
output wire [C_DQ_WIDTH-1:0] fi_xor_wrdata
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
function integer lsb_mask_index (
input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask
);
begin : my_lsb_mask_index
lsb_mask_index = 0;
while ((lsb_mask_index < C_S_AXI_CTRL_DATA_WIDTH-1) && ~mask[lsb_mask_index]) begin
lsb_mask_index = lsb_mask_index + 1;
end
end
endfunction
function integer msb_mask_index (
input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask
);
begin : my_msb_mask_index
msb_mask_index = C_S_AXI_CTRL_DATA_WIDTH-1;
while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin
msb_mask_index = msb_mask_index - 1;
end
end
endfunction
function integer mask_width (
input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask
);
begin : my_mask_width
if (msb_mask_index(mask) > lsb_mask_index(mask)) begin
mask_width = msb_mask_index(mask) - lsb_mask_index(mask) + 1;
end
else begin
mask_width = 1;
end
end
endfunction
// clog2.
function integer clog2;
// Value to calculate clog2 on
input integer value;
begin
for (clog2=0; value>0; clog2=clog2+1) begin
value = value >> 1;
end
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// BEGIN Auto-generated Register Mapping
localparam P_NUM_REG = 24;
localparam P_NUM_REG_WIDTH = clog2(P_NUM_REG);
localparam P_REG_FI_ECC_RDAC = 1'b0;
localparam P_REG_FI_ECC_INDX = 23;
localparam P_REG_FI_ECC_INIT = 32'h0000_0000;
localparam P_REG_FI_ECC_WRAC = (C_ECC_TEST == "ON") ? 1'b1 : 1'b0;
localparam P_REG_FI_ECC_ADDR = 32'h0000_0380;
localparam P_REG_FI_ECC_MASK = 32'h0000_0000;
localparam P_REG_FI_D_127_96_RDAC = 1'b0;
localparam P_REG_FI_D_127_96_INDX = 22;
localparam P_REG_FI_D_127_96_INIT = 32'h0000_0000;
localparam P_REG_FI_D_127_96_WRAC = (C_ECC_TEST == "ON") && (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0;
localparam P_REG_FI_D_127_96_ADDR = 32'h0000_030C;
localparam P_REG_FI_D_127_96_MASK = 32'h0000_0000;
localparam P_REG_FI_D_95_64_RDAC = 1'b0;
localparam P_REG_FI_D_95_64_INDX = 21;
localparam P_REG_FI_D_95_64_INIT = 32'h0000_0000;
localparam P_REG_FI_D_95_64_WRAC = (C_ECC_TEST == "ON") && (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0;
localparam P_REG_FI_D_95_64_ADDR = 32'h0000_0308;
localparam P_REG_FI_D_95_64_MASK = 32'h0000_0000;
localparam P_REG_FI_D_63_32_RDAC = 1'b0;
localparam P_REG_FI_D_63_32_INDX = 20;
localparam P_REG_FI_D_63_32_INIT = 32'h0000_0000;
localparam P_REG_FI_D_63_32_WRAC = (C_ECC_TEST == "ON") ? 1'b1 : 1'b0;
localparam P_REG_FI_D_63_32_ADDR = 32'h0000_0304;
localparam P_REG_FI_D_63_32_MASK = 32'h0000_0000;
localparam P_REG_FI_D_31_00_RDAC = 1'b0;
localparam P_REG_FI_D_31_00_INDX = 19;
localparam P_REG_FI_D_31_00_INIT = 32'h0000_0000;
localparam P_REG_FI_D_31_00_WRAC = (C_ECC_TEST == "ON") ? 1'b1 : 1'b0;
localparam P_REG_FI_D_31_00_ADDR = 32'h0000_0300;
localparam P_REG_FI_D_31_00_MASK = 32'h0000_0000;
localparam P_REG_UE_FFA_63_32_RDAC = (C_S_AXI_ADDR_WIDTH > 32) ? 1'b1 : 1'b0;
localparam P_REG_UE_FFA_63_32_INDX = 18;
localparam P_REG_UE_FFA_63_32_INIT = 32'h0000_0000;
localparam P_REG_UE_FFA_63_32_WRAC = 1'b0;
localparam P_REG_UE_FFA_63_32_ADDR = 32'h0000_02C4;
localparam P_REG_UE_FFA_63_32_MASK = 32'hFFFF_FFFF;
localparam P_REG_UE_FFA_31_00_RDAC = 1'b1;
localparam P_REG_UE_FFA_31_00_INDX = 17;
localparam P_REG_UE_FFA_31_00_INIT = 32'h0000_0000;
localparam P_REG_UE_FFA_31_00_WRAC = 1'b0;
localparam P_REG_UE_FFA_31_00_ADDR = 32'h0000_02C0;
localparam P_REG_UE_FFA_31_00_MASK = 32'hFFFF_FFFF;
localparam P_REG_UE_FFE_RDAC = 1'b1;
localparam P_REG_UE_FFE_INDX = 16;
localparam P_REG_UE_FFE_INIT = 32'h0000_0000;
localparam P_REG_UE_FFE_WRAC = 1'b0;
localparam P_REG_UE_FFE_ADDR = 32'h0000_0280;
localparam P_REG_UE_FFE_MASK = 32'h0000_FFFF;
localparam P_REG_UE_FFD_127_96_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;
localparam P_REG_UE_FFD_127_96_INDX = 15;
localparam P_REG_UE_FFD_127_96_INIT = 32'h0000_0000;
localparam P_REG_UE_FFD_127_96_WRAC = 1'b0;
localparam P_REG_UE_FFD_127_96_ADDR = 32'h0000_020C;
localparam P_REG_UE_FFD_127_96_MASK = 32'hFFFF_FFFF;
localparam P_REG_UE_FFD_95_64_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;
localparam P_REG_UE_FFD_95_64_INDX = 14;
localparam P_REG_UE_FFD_95_64_INIT = 32'h0000_0000;
localparam P_REG_UE_FFD_95_64_WRAC = 1'b0;
localparam P_REG_UE_FFD_95_64_ADDR = 32'h0000_0208;
localparam P_REG_UE_FFD_95_64_MASK = 32'hFFFF_FFFF;
localparam P_REG_UE_FFD_63_32_RDAC = 1'b1;
localparam P_REG_UE_FFD_63_32_INDX = 13;
localparam P_REG_UE_FFD_63_32_INIT = 32'h0000_0000;
localparam P_REG_UE_FFD_63_32_WRAC = 1'b0;
localparam P_REG_UE_FFD_63_32_ADDR = 32'h0000_0204;
localparam P_REG_UE_FFD_63_32_MASK = 32'hFFFF_FFFF;
localparam P_REG_UE_FFD_31_00_RDAC = 1'b1;
localparam P_REG_UE_FFD_31_00_INDX = 12;
localparam P_REG_UE_FFD_31_00_INIT = 32'h0000_0000;
localparam P_REG_UE_FFD_31_00_WRAC = 1'b0;
localparam P_REG_UE_FFD_31_00_ADDR = 32'h0000_0200;
localparam P_REG_UE_FFD_31_00_MASK = 32'hFFFF_FFFF;
localparam P_REG_CE_FFA_63_32_RDAC = (C_S_AXI_ADDR_WIDTH > 32) ? 1'b1 : 1'b0;
localparam P_REG_CE_FFA_63_32_INDX = 11;
localparam P_REG_CE_FFA_63_32_INIT = 32'h0000_0000;
localparam P_REG_CE_FFA_63_32_WRAC = 1'b0;
localparam P_REG_CE_FFA_63_32_ADDR = 32'h0000_01C4;
localparam P_REG_CE_FFA_63_32_MASK = 32'hFFFF_FFFF;
localparam P_REG_CE_FFA_31_00_RDAC = 1'b1;
localparam P_REG_CE_FFA_31_00_INDX = 10;
localparam P_REG_CE_FFA_31_00_INIT = 32'h0000_0000;
localparam P_REG_CE_FFA_31_00_WRAC = 1'b0;
localparam P_REG_CE_FFA_31_00_ADDR = 32'h0000_01C0;
localparam P_REG_CE_FFA_31_00_MASK = 32'hFFFF_FFFF;
localparam P_REG_CE_FFE_RDAC = 1'b1;
localparam P_REG_CE_FFE_INDX = 9;
localparam P_REG_CE_FFE_INIT = 32'h0000_0000;
localparam P_REG_CE_FFE_WRAC = 1'b0;
localparam P_REG_CE_FFE_ADDR = 32'h0000_0180;
localparam P_REG_CE_FFE_MASK = 32'h0000_FFFF;
localparam P_REG_CE_FFD_127_96_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;
localparam P_REG_CE_FFD_127_96_INDX = 8;
localparam P_REG_CE_FFD_127_96_INIT = 32'h0000_0000;
localparam P_REG_CE_FFD_127_96_WRAC = 1'b0;
localparam P_REG_CE_FFD_127_96_ADDR = 32'h0000_010C;
localparam P_REG_CE_FFD_127_96_MASK = 32'hFFFF_FFFF;
localparam P_REG_CE_FFD_95_64_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;
localparam P_REG_CE_FFD_95_64_INDX = 7;
localparam P_REG_CE_FFD_95_64_INIT = 32'h0000_0000;
localparam P_REG_CE_FFD_95_64_WRAC = 1'b0;
localparam P_REG_CE_FFD_95_64_ADDR = 32'h0000_0108;
localparam P_REG_CE_FFD_95_64_MASK = 32'hFFFF_FFFF;
localparam P_REG_CE_FFD_63_32_RDAC = 1'b1;
localparam P_REG_CE_FFD_63_32_INDX = 6;
localparam P_REG_CE_FFD_63_32_INIT = 32'h0000_0000;
localparam P_REG_CE_FFD_63_32_WRAC = 1'b0;
localparam P_REG_CE_FFD_63_32_ADDR = 32'h0000_0104;
localparam P_REG_CE_FFD_63_32_MASK = 32'hFFFF_FFFF;
localparam P_REG_CE_FFD_31_00_RDAC = 1'b1;
localparam P_REG_CE_FFD_31_00_INDX = 5;
localparam P_REG_CE_FFD_31_00_INIT = 32'h0000_0000;
localparam P_REG_CE_FFD_31_00_WRAC = 1'b0;
localparam P_REG_CE_FFD_31_00_ADDR = 32'h0000_0100;
localparam P_REG_CE_FFD_31_00_MASK = 32'hFFFF_FFFF;
localparam P_REG_CE_CNT_RDAC = 1'b1;
localparam P_REG_CE_CNT_INDX = 4;
localparam P_REG_CE_CNT_INIT = 32'h0000_0000;
localparam P_REG_CE_CNT_WRAC = 1'b1;
localparam P_REG_CE_CNT_ADDR = 32'h0000_000C;
localparam P_REG_CE_CNT_MASK = {{C_S_AXI_CTRL_DATA_WIDTH-C_ECC_CE_COUNTER_WIDTH{1'b0}}, {C_ECC_CE_COUNTER_WIDTH{1'b1}}};
localparam P_REG_ECC_ON_OFF_RDAC = 1'b1;
localparam P_REG_ECC_ON_OFF_INDX = 3;
localparam P_REG_ECC_ON_OFF_INIT = {{31{1'b0}}, C_ECC_ONOFF_RESET_VALUE[0]};
localparam P_REG_ECC_ON_OFF_WRAC = 1'b1;
localparam P_REG_ECC_ON_OFF_ADDR = 32'h0000_0008;
localparam P_REG_ECC_ON_OFF_MASK = 32'h0000_0001;
localparam P_REG_ECC_EN_IRQ_RDAC = 1'b1;
localparam P_REG_ECC_EN_IRQ_INDX = 2;
localparam P_REG_ECC_EN_IRQ_INIT = 32'h0000_0000;
localparam P_REG_ECC_EN_IRQ_WRAC = 1'b1;
localparam P_REG_ECC_EN_IRQ_ADDR = 32'h0000_0004;
localparam P_REG_ECC_EN_IRQ_MASK = 32'h0000_0003;
localparam P_REG_ECC_STATUS_RDAC = 1'b1;
localparam P_REG_ECC_STATUS_INDX = 1;
localparam P_REG_ECC_STATUS_INIT = 32'h0000_0000;
localparam P_REG_ECC_STATUS_WRAC = 1'b1;
localparam P_REG_ECC_STATUS_ADDR = 32'h0000_0000;
localparam P_REG_ECC_STATUS_MASK = 32'h0000_0003;
localparam P_REG_DUMMY_RDAC = 1'b1;
localparam P_REG_DUMMY_INDX = 0;
localparam P_REG_DUMMY_INIT = 32'hDEAD_DEAD;
localparam P_REG_DUMMY_WRAC = 1'b1;
localparam P_REG_DUMMY_ADDR = 32'hFFFF_FFFF;
localparam P_REG_DUMMY_MASK = 32'hFFFF_FFFF;
localparam P_REG_INDX_ARRAY = {
P_REG_FI_ECC_INDX,
P_REG_FI_D_127_96_INDX,
P_REG_FI_D_95_64_INDX,
P_REG_FI_D_63_32_INDX,
P_REG_FI_D_31_00_INDX,
P_REG_UE_FFA_63_32_INDX,
P_REG_UE_FFA_31_00_INDX,
P_REG_UE_FFE_INDX,
P_REG_UE_FFD_127_96_INDX,
P_REG_UE_FFD_95_64_INDX,
P_REG_UE_FFD_63_32_INDX,
P_REG_UE_FFD_31_00_INDX,
P_REG_CE_FFA_63_32_INDX,
P_REG_CE_FFA_31_00_INDX,
P_REG_CE_FFE_INDX,
P_REG_CE_FFD_127_96_INDX,
P_REG_CE_FFD_95_64_INDX,
P_REG_CE_FFD_63_32_INDX,
P_REG_CE_FFD_31_00_INDX,
P_REG_CE_CNT_INDX,
P_REG_ECC_ON_OFF_INDX,
P_REG_ECC_EN_IRQ_INDX,
P_REG_ECC_STATUS_INDX,
P_REG_DUMMY_INDX
};
localparam P_REG_RDAC_ARRAY = {
P_REG_FI_ECC_RDAC,
P_REG_FI_D_127_96_RDAC,
P_REG_FI_D_95_64_RDAC,
P_REG_FI_D_63_32_RDAC,
P_REG_FI_D_31_00_RDAC,
P_REG_UE_FFA_63_32_RDAC,
P_REG_UE_FFA_31_00_RDAC,
P_REG_UE_FFE_RDAC,
P_REG_UE_FFD_127_96_RDAC,
P_REG_UE_FFD_95_64_RDAC,
P_REG_UE_FFD_63_32_RDAC,
P_REG_UE_FFD_31_00_RDAC,
P_REG_CE_FFA_63_32_RDAC,
P_REG_CE_FFA_31_00_RDAC,
P_REG_CE_FFE_RDAC,
P_REG_CE_FFD_127_96_RDAC,
P_REG_CE_FFD_95_64_RDAC,
P_REG_CE_FFD_63_32_RDAC,
P_REG_CE_FFD_31_00_RDAC,
P_REG_CE_CNT_RDAC,
P_REG_ECC_ON_OFF_RDAC,
P_REG_ECC_EN_IRQ_RDAC,
P_REG_ECC_STATUS_RDAC,
P_REG_DUMMY_RDAC
};
localparam P_REG_INIT_ARRAY = {
P_REG_FI_ECC_INIT,
P_REG_FI_D_127_96_INIT,
P_REG_FI_D_95_64_INIT,
P_REG_FI_D_63_32_INIT,
P_REG_FI_D_31_00_INIT,
P_REG_UE_FFA_63_32_INIT,
P_REG_UE_FFA_31_00_INIT,
P_REG_UE_FFE_INIT,
P_REG_UE_FFD_127_96_INIT,
P_REG_UE_FFD_95_64_INIT,
P_REG_UE_FFD_63_32_INIT,
P_REG_UE_FFD_31_00_INIT,
P_REG_CE_FFA_63_32_INIT,
P_REG_CE_FFA_31_00_INIT,
P_REG_CE_FFE_INIT,
P_REG_CE_FFD_127_96_INIT,
P_REG_CE_FFD_95_64_INIT,
P_REG_CE_FFD_63_32_INIT,
P_REG_CE_FFD_31_00_INIT,
P_REG_CE_CNT_INIT,
P_REG_ECC_ON_OFF_INIT,
P_REG_ECC_EN_IRQ_INIT,
P_REG_ECC_STATUS_INIT,
P_REG_DUMMY_INIT
};
localparam P_REG_ADDR_ARRAY = {
P_REG_FI_ECC_ADDR,
P_REG_FI_D_127_96_ADDR,
P_REG_FI_D_95_64_ADDR,
P_REG_FI_D_63_32_ADDR,
P_REG_FI_D_31_00_ADDR,
P_REG_UE_FFA_63_32_ADDR,
P_REG_UE_FFA_31_00_ADDR,
P_REG_UE_FFE_ADDR,
P_REG_UE_FFD_127_96_ADDR,
P_REG_UE_FFD_95_64_ADDR,
P_REG_UE_FFD_63_32_ADDR,
P_REG_UE_FFD_31_00_ADDR,
P_REG_CE_FFA_63_32_ADDR,
P_REG_CE_FFA_31_00_ADDR,
P_REG_CE_FFE_ADDR,
P_REG_CE_FFD_127_96_ADDR,
P_REG_CE_FFD_95_64_ADDR,
P_REG_CE_FFD_63_32_ADDR,
P_REG_CE_FFD_31_00_ADDR,
P_REG_CE_CNT_ADDR,
P_REG_ECC_ON_OFF_ADDR,
P_REG_ECC_EN_IRQ_ADDR,
P_REG_ECC_STATUS_ADDR,
P_REG_DUMMY_ADDR
};
localparam P_REG_WRAC_ARRAY = {
P_REG_FI_ECC_WRAC,
P_REG_FI_D_127_96_WRAC,
P_REG_FI_D_95_64_WRAC,
P_REG_FI_D_63_32_WRAC,
P_REG_FI_D_31_00_WRAC,
P_REG_UE_FFA_63_32_WRAC,
P_REG_UE_FFA_31_00_WRAC,
P_REG_UE_FFE_WRAC,
P_REG_UE_FFD_127_96_WRAC,
P_REG_UE_FFD_95_64_WRAC,
P_REG_UE_FFD_63_32_WRAC,
P_REG_UE_FFD_31_00_WRAC,
P_REG_CE_FFA_63_32_WRAC,
P_REG_CE_FFA_31_00_WRAC,
P_REG_CE_FFE_WRAC,
P_REG_CE_FFD_127_96_WRAC,
P_REG_CE_FFD_95_64_WRAC,
P_REG_CE_FFD_63_32_WRAC,
P_REG_CE_FFD_31_00_WRAC,
P_REG_CE_CNT_WRAC,
P_REG_ECC_ON_OFF_WRAC,
P_REG_ECC_EN_IRQ_WRAC,
P_REG_ECC_STATUS_WRAC,
P_REG_DUMMY_WRAC
};
localparam P_REG_WIDTH_ARRAY = {
mask_width(P_REG_FI_ECC_MASK),
mask_width(P_REG_FI_D_127_96_MASK),
mask_width(P_REG_FI_D_95_64_MASK),
mask_width(P_REG_FI_D_63_32_MASK),
mask_width(P_REG_FI_D_31_00_MASK),
mask_width(P_REG_UE_FFA_63_32_MASK),
mask_width(P_REG_UE_FFA_31_00_MASK),
mask_width(P_REG_UE_FFE_MASK),
mask_width(P_REG_UE_FFD_127_96_MASK),
mask_width(P_REG_UE_FFD_95_64_MASK),
mask_width(P_REG_UE_FFD_63_32_MASK),
mask_width(P_REG_UE_FFD_31_00_MASK),
mask_width(P_REG_CE_FFA_63_32_MASK),
mask_width(P_REG_CE_FFA_31_00_MASK),
mask_width(P_REG_CE_FFE_MASK),
mask_width(P_REG_CE_FFD_127_96_MASK),
mask_width(P_REG_CE_FFD_95_64_MASK),
mask_width(P_REG_CE_FFD_63_32_MASK),
mask_width(P_REG_CE_FFD_31_00_MASK),
mask_width(P_REG_CE_CNT_MASK),
mask_width(P_REG_ECC_ON_OFF_MASK),
mask_width(P_REG_ECC_EN_IRQ_MASK),
mask_width(P_REG_ECC_STATUS_MASK),
mask_width(P_REG_DUMMY_MASK)
};
localparam P_REG_MASK_ARRAY = {
P_REG_FI_ECC_MASK,
P_REG_FI_D_127_96_MASK,
P_REG_FI_D_95_64_MASK,
P_REG_FI_D_63_32_MASK,
P_REG_FI_D_31_00_MASK,
P_REG_UE_FFA_63_32_MASK,
P_REG_UE_FFA_31_00_MASK,
P_REG_UE_FFE_MASK,
P_REG_UE_FFD_127_96_MASK,
P_REG_UE_FFD_95_64_MASK,
P_REG_UE_FFD_63_32_MASK,
P_REG_UE_FFD_31_00_MASK,
P_REG_CE_FFA_63_32_MASK,
P_REG_CE_FFA_31_00_MASK,
P_REG_CE_FFE_MASK,
P_REG_CE_FFD_127_96_MASK,
P_REG_CE_FFD_95_64_MASK,
P_REG_CE_FFD_63_32_MASK,
P_REG_CE_FFD_31_00_MASK,
P_REG_CE_CNT_MASK,
P_REG_ECC_ON_OFF_MASK,
P_REG_ECC_EN_IRQ_MASK,
P_REG_ECC_STATUS_MASK,
P_REG_DUMMY_MASK
};
// END Auto-generated Register Mapping
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [ P_NUM_REG_WIDTH-1:0 ] reg_data_sel;
wire reg_data_write;
wire [ C_S_AXI_CTRL_DATA_WIDTH-1:0 ] reg_data_in;
wire [ C_S_AXI_CTRL_DATA_WIDTH*P_NUM_REG-1:0 ] reg_data_out;
wire reset;
wire arhandshake;
wire rhandshake;
wire awhandshake;
wire bhandshake;
reg wr_pending;
reg rd_pending;
reg arready_r;
reg awready_r;
reg [ C_S_AXI_ADDR_WIDTH-1:0 ] addr;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
assign reset = ~aresetn;
assign arhandshake = s_axi_arvalid & s_axi_arready;
assign awhandshake = s_axi_awvalid & s_axi_awready;
assign rhandshake = s_axi_rvalid & s_axi_rready;
assign bhandshake = s_axi_bvalid & s_axi_bready;
assign s_axi_awready = awready_r;
assign s_axi_arready = arready_r;
always @(posedge aclk) begin
if (reset) begin
wr_pending <= 1'b0;
end
else begin
wr_pending <= (awhandshake | wr_pending) & ~bhandshake;
end
end
always @(posedge aclk) begin
if (reset) begin
rd_pending <= 1'b0;
end
else begin
rd_pending <= (arhandshake | rd_pending) & ~rhandshake;
end
end
always @(posedge aclk) begin
if (reset | ~init_complete) begin
awready_r <= 1'b0;
end
else begin
awready_r <= s_axi_awvalid & ~rd_pending & ~wr_pending & ~awready_r;
end
end
always @(posedge aclk) begin
if (reset | ~init_complete) begin
arready_r <= 1'b0;
end
else begin
arready_r <= s_axi_arvalid & ~rd_pending & ~wr_pending & ~s_axi_awvalid & ~arready_r;
end
end
always @(posedge aclk) begin
if (awhandshake) begin
addr <= s_axi_awaddr;
end else if (arhandshake) begin
addr <= s_axi_araddr;
end
end
// Instantiate AXI4-Lite write channel module
mig_7series_v4_2_axi_ctrl_write #
(
.C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) ,
.C_NUM_REG ( P_NUM_REG ) ,
.C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) ,
.C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) ,
.C_REG_WRAC_ARRAY ( P_REG_WRAC_ARRAY )
)
axi_ctrl_write_0
(
.clk ( aclk ) ,
.reset ( reset ) ,
.awvalid ( s_axi_awvalid ) ,
.awready ( s_axi_awready ) ,
.awaddr ( addr ) ,
.wvalid ( s_axi_wvalid ) ,
.wready ( s_axi_wready ) ,
.wdata ( s_axi_wdata ) ,
.bvalid ( s_axi_bvalid ) ,
.bready ( s_axi_bready ) ,
.bresp ( s_axi_bresp ) ,
.reg_data_sel ( reg_data_sel ) ,
.reg_data_write ( reg_data_write ) ,
.reg_data ( reg_data_in )
);
// Instantiate AXI4-Lite write channel module
mig_7series_v4_2_axi_ctrl_read #
(
.C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) ,
.C_NUM_REG ( P_NUM_REG ) ,
.C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) ,
.C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) ,
.C_REG_RDAC_ARRAY ( P_REG_RDAC_ARRAY )
)
axi_ctrl_read_0
(
.clk ( aclk ) ,
.reset ( reset ) ,
.araddr ( addr ) ,
.rvalid ( s_axi_rvalid ) ,
.rready ( s_axi_rready ) ,
.rresp ( s_axi_rresp ) ,
.rdata ( s_axi_rdata ) ,
.pending ( rd_pending ) ,
.reg_bank_array ( reg_data_out )
);
mig_7series_v4_2_axi_ctrl_reg_bank #
(
.C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) ,
.C_DQ_WIDTH ( C_DQ_WIDTH ) ,
.C_ECC_CE_COUNTER_WIDTH ( C_ECC_CE_COUNTER_WIDTH ) ,
.C_ECC_ONOFF_RESET_VALUE ( C_ECC_ONOFF_RESET_VALUE ) ,
.C_ECC_TEST ( C_ECC_TEST ) ,
.C_ECC_WIDTH ( C_ECC_WIDTH ) ,
.C_MC_ERR_ADDR_WIDTH ( C_MC_ERR_ADDR_WIDTH ) ,
.C_MEM_ADDR_ORDER ( C_MEM_ADDR_ORDER ) ,
.C_BANK_WIDTH ( C_BANK_WIDTH ) ,
.C_ROW_WIDTH ( C_ROW_WIDTH ) ,
.C_COL_WIDTH ( C_COL_WIDTH ) ,
.C_NCK_PER_CLK ( C_NCK_PER_CLK ) ,
.C_NUM_REG ( P_NUM_REG ) ,
.C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) ,
.C_S_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,
.C_S_AXI_BASEADDR ( C_S_AXI_BASEADDR ) ,
// Register arrays
.C_REG_RDAC_ARRAY ( P_REG_RDAC_ARRAY ) ,
.C_REG_WRAC_ARRAY ( P_REG_WRAC_ARRAY ) ,
.C_REG_INIT_ARRAY ( P_REG_INIT_ARRAY ) ,
.C_REG_MASK_ARRAY ( P_REG_MASK_ARRAY ) ,
.C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) ,
.C_REG_WIDTH_ARRAY ( P_REG_WIDTH_ARRAY ) ,
// Register Indices
.C_REG_FI_ECC_INDX ( P_REG_FI_ECC_INDX ) ,
.C_REG_FI_D_127_96_INDX ( P_REG_FI_D_127_96_INDX ) ,
.C_REG_FI_D_95_64_INDX ( P_REG_FI_D_95_64_INDX ) ,
.C_REG_FI_D_63_32_INDX ( P_REG_FI_D_63_32_INDX ) ,
.C_REG_FI_D_31_00_INDX ( P_REG_FI_D_31_00_INDX ) ,
.C_REG_UE_FFA_63_32_INDX ( P_REG_UE_FFA_63_32_INDX ) ,
.C_REG_UE_FFA_31_00_INDX ( P_REG_UE_FFA_31_00_INDX ) ,
.C_REG_UE_FFE_INDX ( P_REG_UE_FFE_INDX ) ,
.C_REG_UE_FFD_127_96_INDX ( P_REG_UE_FFD_127_96_INDX ) ,
.C_REG_UE_FFD_95_64_INDX ( P_REG_UE_FFD_95_64_INDX ) ,
.C_REG_UE_FFD_63_32_INDX ( P_REG_UE_FFD_63_32_INDX ) ,
.C_REG_UE_FFD_31_00_INDX ( P_REG_UE_FFD_31_00_INDX ) ,
.C_REG_CE_FFA_63_32_INDX ( P_REG_CE_FFA_63_32_INDX ) ,
.C_REG_CE_FFA_31_00_INDX ( P_REG_CE_FFA_31_00_INDX ) ,
.C_REG_CE_FFE_INDX ( P_REG_CE_FFE_INDX ) ,
.C_REG_CE_FFD_127_96_INDX ( P_REG_CE_FFD_127_96_INDX ) ,
.C_REG_CE_FFD_95_64_INDX ( P_REG_CE_FFD_95_64_INDX ) ,
.C_REG_CE_FFD_63_32_INDX ( P_REG_CE_FFD_63_32_INDX ) ,
.C_REG_CE_FFD_31_00_INDX ( P_REG_CE_FFD_31_00_INDX ) ,
.C_REG_CE_CNT_INDX ( P_REG_CE_CNT_INDX ) ,
.C_REG_ECC_ON_OFF_INDX ( P_REG_ECC_ON_OFF_INDX ) ,
.C_REG_ECC_EN_IRQ_INDX ( P_REG_ECC_EN_IRQ_INDX ) ,
.C_REG_ECC_STATUS_INDX ( P_REG_ECC_STATUS_INDX ) ,
.C_REG_DUMMY_INDX ( P_REG_DUMMY_INDX )
)
axi_ctrl_reg_bank_0
(
.clk ( aclk ) ,
.reset ( reset ) ,
.reg_data_sel ( reg_data_sel ) ,
.reg_data_write ( reg_data_write ) ,
.reg_data_in ( reg_data_in ) ,
.reg_data_out ( reg_data_out ) ,
.interrupt ( interrupt ) ,
.ecc_single ( ecc_single ) ,
.ecc_multiple ( ecc_multiple ) ,
.ecc_err_addr ( ecc_err_addr ) ,
.app_correct_en ( app_correct_en ) ,
.dfi_rddata ( dfi_rddata ) ,
.fi_xor_we ( fi_xor_we ) ,
.fi_xor_wrdata ( fi_xor_wrdata )
);
endmodule
`default_nettype wire

195
Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.ip_user_files/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v Normal file
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@ -0,0 +1,195 @@
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_write.v
//
// Description:
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_ctrl_write #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter integer C_DATA_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_WRAC_ARRAY = 5'b11111
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire awvalid ,
input wire awready ,
input wire [C_ADDR_WIDTH-1:0] awaddr ,
// Slave Interface Read Data Ports
input wire wvalid ,
output wire wready ,
input wire [C_DATA_WIDTH-1:0] wdata ,
output wire bvalid ,
input wire bready ,
output wire [1:0] bresp ,
// Internal Signals
output wire [C_NUM_REG_WIDTH-1:0] reg_data_sel ,
output wire reg_data_write ,
output wire [C_DATA_WIDTH-1:0] reg_data
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire awhandshake;
wire whandshake;
reg whandshake_d1;
wire bhandshake;
wire [C_NUM_REG_WIDTH-1:0] reg_decode_num;
reg awready_i;
reg wready_i;
reg bvalid_i;
reg [C_DATA_WIDTH-1:0] data;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Handshake signals
assign awhandshake = awvalid & awready;
assign whandshake = wvalid & wready;
assign bhandshake = bvalid & bready;
mig_7series_v4_2_axi_ctrl_addr_decode #
(
.C_ADDR_WIDTH ( C_ADDR_WIDTH ) ,
.C_NUM_REG ( C_NUM_REG ) ,
.C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) ,
.C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) ,
.C_REG_RDWR_ARRAY ( C_REG_WRAC_ARRAY )
)
axi_ctrl_addr_decode_0
(
.axaddr ( awaddr ) ,
.reg_decode_num ( reg_decode_num )
);
// wchannel only accepts data after aw handshake
assign wready = wready_i;
always @(posedge clk) begin
if (reset) begin
wready_i <= 1'b0;
end
else begin
wready_i <= (awhandshake | wready_i) & ~whandshake;
end
end
// Data is registered but not latched (like awaddr) since it used a cycle later
always @(posedge clk) begin
data <= wdata;
end
// bresponse is sent after successful w handshake
assign bvalid = bvalid_i;
assign bresp = 2'b0; // Okay
always @(posedge clk) begin
if (reset) begin
bvalid_i <= 1'b0;
end
else begin
bvalid_i <= (whandshake | bvalid_i) & ~bhandshake;
end
end
// Assign internal signals
assign reg_data = data;
assign reg_data_write = whandshake_d1;
assign reg_data_sel = reg_decode_num;
always @(posedge clk) begin
whandshake_d1 <= whandshake;
end
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_ar_channel.v
//
// Description:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_mc_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MC_ADDR_WIDTH = 30,
// Width of AXI xDATA and MC xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// DRAM clock to AXI clock ratio
// supported values 2, 4
parameter integer C_MC_nCK_PER_CLK = 2,
// Static value of axsize
// Range: 2-4
parameter integer C_AXSIZE = 2
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] araddr ,
input wire [7:0] arlen ,
input wire [2:0] arsize ,
input wire [1:0] arburst ,
input wire [1:0] arlock ,
input wire [3:0] arcache ,
input wire [2:0] arprot ,
input wire [3:0] arqos ,
input wire arvalid ,
output wire arready ,
// MC Master Interface
//CMD PORT
output wire cmd_en ,
output wire cmd_en_last ,
output wire [2:0] cmd_instr ,
output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr ,
input wire cmd_full ,
// Connections to/from axi_mc_r_channel module
input wire r_data_rdy ,
output reg r_push ,
output wire[C_ID_WIDTH-1:0] r_arid ,
output reg r_rlast ,
output wire r_ignore_begin ,
output wire r_ignore_end ,
output wire arvalid_int ,
output wire [3:0] arqos_int
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_CMD_WRITE = 3'b000;
localparam P_CMD_READ = 3'b001;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
reg [C_ID_WIDTH-1:0] axid ;
reg [C_AXI_ADDR_WIDTH-1:0] axaddr ;
reg [7:0] axlen ;
reg [3:0] axqos ;
reg [1:0] axburst ;
reg axvalid ;
wire [C_ID_WIDTH-1:0] axid_int ;
wire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ;
wire [7:0] axlen_int ;
wire [3:0] axqos_int ;
wire [1:0] axburst_int ;
wire axvalid_int ;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign arvalid_int = axvalid_int;
assign arqos_int = axqos_int;
assign axid_int = arready ? arid : axid;
assign axlen_int = arready ? arlen : axlen;
assign axqos_int = arready ? arqos : axqos;
assign axaddr_int = arready ? araddr : axaddr;
assign axburst_int = arready ? arburst : axburst;
assign axvalid_int = arready ? arvalid : axvalid;
always @(posedge clk) begin
if(reset)
axvalid <= 1'b0;
else
axvalid <= axvalid_int;
end
always @(posedge clk) begin
axid <= axid_int;
axlen <= axlen_int;
axqos <= axqos_int;
axaddr <= axaddr_int;
axburst <= axburst_int;
end
// Translate the AXI transaction to the MC transaction(s)
mig_7series_v4_2_axi_mc_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,
.C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) ,
.C_AXSIZE ( C_AXSIZE ) ,
.C_MC_RD_INST ( 1 )
)
axi_mc_cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr_int ) ,
.axlen ( axlen_int ) ,
.axsize ( arsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations.
.axburst ( axburst_int ) ,
.axvalid ( axvalid_int ) ,
.axready ( arready ) ,
.cmd_byte_addr ( cmd_byte_addr ) ,
.ignore_begin ( r_ignore_begin ) ,
.ignore_end ( r_ignore_end ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
mig_7series_v4_2_axi_mc_cmd_fsm #
(
.C_MC_BURST_LEN (C_MC_BURST_LEN ),
.C_MC_RD_INST (1 )
)
ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axready ( arready ) ,
.axvalid ( axvalid_int ) ,
.cmd_en ( cmd_en ) ,
.cmd_full ( cmd_full ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_rdy ( r_data_rdy ) ,
.cmd_en_last ( cmd_en_last )
);
assign cmd_instr = P_CMD_READ;
// these signals can be moved out of this block to the top level.
assign r_arid = axid;
always @(posedge clk) begin
r_push <= next;
r_rlast <= ~next_pending;
end
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_aw_channel.v
//
// Description:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_mc_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MC_ADDR_WIDTH = 30,
// Width of AXI xDATA and MC xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// DRAM clock to AXI clock ratio
// supported values 2, 4
parameter integer C_MC_nCK_PER_CLK = 2,
// Static value of axsize
// Range: 2-4
parameter integer C_AXSIZE = 2,
parameter C_ECC = "OFF"
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] awaddr ,
input wire [7:0] awlen ,
input wire [2:0] awsize ,
input wire [1:0] awburst ,
input wire [1:0] awlock ,
input wire [3:0] awcache ,
input wire [2:0] awprot ,
input wire [3:0] awqos ,
input wire awvalid ,
output wire awready ,
// MC Master Interface
//CMD PORT
output wire cmd_en ,
output wire cmd_en_last ,
output wire [2:0] cmd_instr ,
output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr ,
input wire cmd_full ,
// Connections to/from axi_mc_w_channel module
input wire w_data_rdy ,
input wire cmd_wr_bytes ,
output wire w_cmd_rdy ,
output wire w_ignore_begin ,
output wire w_ignore_end ,
output wire awvalid_int ,
output wire [3:0] awqos_int ,
// Connections to/from axi_mc_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_CMD_WRITE = 3'b000;
localparam P_CMD_READ = 3'b001;
localparam P_CMD_WRITE_BYTES = 3'b011;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
reg [C_ID_WIDTH-1:0] axid ;
reg [C_AXI_ADDR_WIDTH-1:0] axaddr ;
reg [7:0] axlen ;
reg [3:0] axqos ;
reg [1:0] axburst ;
reg axvalid ;
wire [C_ID_WIDTH-1:0] axid_int ;
wire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ;
wire [7:0] axlen_int ;
wire [3:0] axqos_int ;
wire [1:0] axburst_int ;
wire axvalid_int ;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign awvalid_int = axvalid_int;
assign awqos_int = axqos_int;
assign axid_int = awready ? awid : axid;
assign axlen_int = awready ? awlen : axlen;
assign axqos_int = awready ? awqos : axqos;
assign axaddr_int = awready ? awaddr : axaddr;
assign axburst_int = awready ? awburst : axburst;
assign axvalid_int = awready ? awvalid : axvalid;
always @(posedge clk) begin
if(reset)
axvalid <= 1'b0;
else
axvalid <= axvalid_int;
end
always @(posedge clk) begin
axid <= axid_int;
axlen <= axlen_int;
axqos <= axqos_int;
axaddr <= axaddr_int;
axburst <= axburst_int;
end
// Translate the AXI transaction to the MC transaction(s)
mig_7series_v4_2_axi_mc_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,
.C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) ,
.C_AXSIZE ( C_AXSIZE ) ,
.C_MC_RD_INST ( 0 )
)
axi_mc_cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr_int ) ,
.axlen ( axlen_int ) ,
.axsize ( awsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations.
.axburst ( axburst_int ) ,
.axvalid ( axvalid_int ) ,
.axready ( awready ) ,
.cmd_byte_addr ( cmd_byte_addr ) ,
.ignore_begin ( w_ignore_begin ) ,
.ignore_end ( w_ignore_end ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
mig_7series_v4_2_axi_mc_wr_cmd_fsm #
(
.C_MC_BURST_LEN (C_MC_BURST_LEN ),
.C_MC_RD_INST (0 )
)
aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axready ( awready ) ,
.axvalid ( axvalid_int ) ,
.cmd_en ( cmd_en ) ,
.cmd_full ( cmd_full ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_rdy ( w_data_rdy ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.cmd_en_last ( cmd_en_last )
);
// assign cmd_instr = (C_ECC == "ON") ? P_CMD_WRITE_BYTES : P_CMD_WRITE;
assign cmd_instr = ((C_ECC == "ON") & cmd_wr_bytes) ? P_CMD_WRITE_BYTES : P_CMD_WRITE;
assign b_awid = axid_int;
assign w_cmd_rdy = next;
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_b_channel.v
//
// Description:
// This module is responsible for returning the write response to the master
// that initiated the write. The write address channel module will push the
// transaction ID into a FIFO in the write response module after the
// completion of the address write phase of the transaction. If strict
// coherency is enabled (C_STRICT_COHERENCY == 1), then this module will
// monitor the MCB command/write FIFOs to determine when to send back the
// response. It will not send the response until it is guaranteed that the
// write has been committed completely to memory.
//
// ERROR RESPONSE
// If the MCB write channel indicates there is an error or write FIFO under
// run then the AXI SLVERR response is returned otherwise the OKAY response
// is returned.
//
// WRITE COHERENCY CHECKING
// The MCB hard block can have up to 6 independent ports to memory. If the
// MCB block is configured as single port or as multi-port with separate
// regions then write coherency logic is not required. In all other cases,
// once a transaction has been sent to the MCB CMD channel, it is not
// guaranteed that it will commit to memory before a transaction on another
// port. To ensure that the response is only sent after the data has been
// written to external memory the write response will not be sent until
// either the write data FIFO is empty or that the command FIFO is empty.
//
// Assertions:
// 1. Standard FIFO assertions on bid_fifo_0.
// 2. bvalid == 0, when C_STRICT_COHERENCY == 1 and mcb_empty == 0.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_mc_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] bid,
output wire [1:0] bresp,
output wire bvalid,
input wire bready,
// Signals to/from the axi_mc_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH;
localparam P_DEPTH = 8;
localparam P_AWIDTH = 3;
// AXI protocol responses:
localparam P_OKAY = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;
localparam B_RESP_PERF = 1'b1; // Set to 1 to increase the write response performance for back to back single beats.
// Set to 0 in case of timing issues, but performance degrades for back to back single beats.
wire empty;
wire bhandshake;
wire [C_ID_WIDTH-1:0] bid_i;
reg b_pop;
reg bvalid_i;
reg [C_ID_WIDTH-1:0] bid_t;
assign bresp = P_OKAY;
generate
if (B_RESP_PERF == 1) begin
assign bid = bid_t;
assign bvalid = bvalid_i;
assign bhandshake = ~bvalid | bready;
always @(*)
b_pop = bhandshake & ~empty;
always @(posedge clk) begin
if(reset) begin
bid_t <= 'b0;
bvalid_i <= 1'b0;
end else if(bhandshake) begin
bid_t <= bid_i;
bvalid_i <= ~empty;
end
end
end else begin // B_RESP_PERF
assign bid = bid_i;
assign bvalid = bvalid_i;
assign bhandshake = bvalid & bready;
always @(posedge clk)
b_pop <= bhandshake;
always @(posedge clk) begin
if (reset | bhandshake) begin
bvalid_i <= 1'b0;
end else if (~empty & (~b_pop)) begin
bvalid_i <= 1'b1;
end
end
end // B_RESP_PERF
endgenerate
mig_7series_v4_2_axi_mc_fifo #
(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( b_pop ) ,
.din ( b_awid ) ,
.dout ( bid_i ) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( empty )
);
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_cmd_arbiter.v
//
// Description:
// This arbiter arbitrates commands from the read and write address channels
// of AXI to the single CMD channel of the MC interface. The inputs are the
// read and write commands that have already been translated to the MC
// format.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_mc_cmd_arbiter #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MC_ADDR_WIDTH = 30,
// write command starve limit in read priority reg mode
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
parameter integer C_AXI_WR_STARVE_LIMIT = 256,
// log2 of C_AXI_WR_STARVE_LIMIT ceil (log2(C_AXI_WR_STARVE_LIMIT))
parameter integer C_AXI_STARVE_CNT_WIDTH = 8,
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG"
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
input wire awvalid ,
input wire [3:0] awqos ,
input wire wr_cmd_en ,
input wire wr_cmd_en_last ,
input wire [2:0] wr_cmd_instr ,
input wire [C_MC_ADDR_WIDTH-1:0] wr_cmd_byte_addr ,
output wire wr_cmd_full ,
input wire arvalid ,
input wire [3:0] arqos ,
input wire rd_cmd_en ,
input wire rd_cmd_en_last ,
input wire [2:0] rd_cmd_instr ,
input wire [C_MC_ADDR_WIDTH-1:0] rd_cmd_byte_addr ,
output wire rd_cmd_full ,
output wire mc_app_en ,
output wire [2:0] mc_app_cmd ,
output wire mc_app_size ,
output wire [C_MC_ADDR_WIDTH-1:0] mc_app_addr ,
output wire mc_app_hi_pri ,
input wire mc_app_rdy
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire rnw;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign mc_app_en = rnw ? rd_cmd_en : wr_cmd_en;
assign mc_app_cmd = rnw ? rd_cmd_instr : wr_cmd_instr;
assign mc_app_addr = rnw ? rd_cmd_byte_addr : wr_cmd_byte_addr;
assign mc_app_size = 1'b0;
assign wr_cmd_full = rnw ? 1'b1 : ~mc_app_rdy;
assign rd_cmd_full = ~rnw ? 1'b1 : ~mc_app_rdy;
assign mc_app_hi_pri = 1'b0;
generate
// TDM Arbitration scheme
if (C_RD_WR_ARB_ALGORITHM == "TDM") begin : TDM
reg rnw_i;
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b0;
end else begin
rnw_i <= ~rnw_i;
end
end
assign rnw = rnw_i;
end
else if (C_RD_WR_ARB_ALGORITHM == "ROUND_ROBIN") begin : ROUND_ROBIN
reg rnw_i;
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b0;
end else begin
rnw_i <= ~rnw;
end
end
assign rnw = (rnw_i & rd_cmd_en) | (~rnw_i & rd_cmd_en & ~wr_cmd_en);
end
else if (C_RD_WR_ARB_ALGORITHM == "RD_PRI_REG") begin : RD_PRI_REG
reg rnw_i;
reg rd_cmd_hold;
reg wr_cmd_hold;
reg [4:0] rd_wait_limit;
reg [4:0] wr_wait_limit;
reg [9:0] rd_starve_cnt;
reg [9:0] wr_starve_cnt;
always @(posedge clk) begin
if (~rnw | ~rd_cmd_hold) begin
rd_wait_limit <= 5'b0;
rd_starve_cnt <= (C_MC_BURST_LEN * 2);
end else if (mc_app_rdy) begin
if (~arvalid | rd_cmd_en)
rd_wait_limit <= 5'b0;
else
rd_wait_limit <= rd_wait_limit + C_MC_BURST_LEN;
if (rd_cmd_en & ~rd_starve_cnt[8])
rd_starve_cnt <= rd_starve_cnt + C_MC_BURST_LEN;
end
end
always @(posedge clk) begin
if (rnw | ~wr_cmd_hold) begin
wr_wait_limit <= 5'b0;
wr_starve_cnt <= (C_MC_BURST_LEN * 2);
end else if (mc_app_rdy) begin
if (~awvalid | wr_cmd_en)
wr_wait_limit <= 5'b0;
else
wr_wait_limit <= wr_wait_limit + C_MC_BURST_LEN;
if (wr_cmd_en & ~wr_starve_cnt[8])
wr_starve_cnt <= wr_starve_cnt + C_MC_BURST_LEN;
end
end
always @(posedge clk) begin
if (reset) begin
rd_cmd_hold <= 1'b0;
wr_cmd_hold <= 1'b0;
end else begin
rd_cmd_hold <= (rnw | rd_cmd_hold) & ~(rd_cmd_en_last & ((awvalid & (|awqos)) | rd_starve_cnt[8])) & ~rd_wait_limit[4];
wr_cmd_hold <= (~rnw | wr_cmd_hold) & ~(wr_cmd_en_last & ((arvalid & (|arqos)) | wr_starve_cnt[8])) & ~wr_wait_limit[4];
end
end
always @(posedge clk) begin
if (reset)
rnw_i <= 1'b1;
else
rnw_i <= rnw;
end
assign rnw = (rnw_i & ~(rd_cmd_hold & arvalid) & awvalid) ? 1'b0 : // RD -> WR
(~rnw_i & ~(wr_cmd_hold & awvalid) & arvalid) ? 1'b1 : // WR -> RD
rnw_i;
end // block: RD_PRI_REG
else if (C_RD_WR_ARB_ALGORITHM == "RD_PRI_REG_STARVE_LIMIT") begin : RD_PRI_REG_STARVE
reg rnw_i;
reg rd_cmd_en_d1;
reg wr_cmd_en_d1;
reg [C_AXI_STARVE_CNT_WIDTH-1:0] wr_starve_cnt;
reg wr_enable;
reg [8:0] rd_starve_cnt;
// write starve count logic.
// wr_enable to give priority to write commands will be set
// when the write commands have been starved till the starve
// limit. The wr_enable will be de-asserted when the pending write
// command is processed or if the rd has been starved for 256 clock
// cycles.
always @(posedge clk) begin
if(reset | ( ~(wr_cmd_en | wr_cmd_en_d1))
| rd_starve_cnt[8])begin
wr_starve_cnt <= 'b0;
wr_enable <= 'b0;
end else if(wr_cmd_en & (mc_app_rdy)) begin
if(wr_starve_cnt < (C_AXI_WR_STARVE_LIMIT-1))
wr_starve_cnt <= wr_starve_cnt + rnw_i;
else
wr_enable <= 1'b1;
end // if (wr_cmd_en & (mc_app_rdy)
end // always @ (posedge clk)
// The rd command should not be starved for ever in this mode.
// The maximum the read will starve is 256 clocks.
always @(posedge clk) begin
if(reset | rnw_i)begin
rd_starve_cnt <= 'b0;
end else if(rd_cmd_en & (mc_app_rdy)) begin
rd_starve_cnt <= rd_starve_cnt + 1;
end // if (wr_cmd_en & (mc_app_rdy)
end // always @ (posedge clk)
always @(posedge clk) begin
if (reset) begin
rd_cmd_en_d1 <= 1'b0;
wr_cmd_en_d1 <= 1'b0;
end else begin
if (mc_app_rdy) begin
rd_cmd_en_d1 <= rd_cmd_en & rnw;
wr_cmd_en_d1 <= wr_cmd_en & ~rnw;
end
end
end
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b1;
end else begin
// Only set RNW to 0 if there is a write pending and read is idle
// rnw_i <= ~((wr_cmd_en | wr_cmd_en_d1) & (~rd_cmd_en) & (~rd_cmd_en_d1));
rnw_i <= ~(((wr_cmd_en | wr_cmd_en_d1) & (~rd_cmd_en) & (~rd_cmd_en_d1)) | wr_enable);
end
end
assign rnw = rnw_i;
end
else if (C_RD_WR_ARB_ALGORITHM == "RD_PRI") begin : RD_PRI
assign rnw = ~(wr_cmd_en & ~rd_cmd_en);
end
else if (C_RD_WR_ARB_ALGORITHM == "WR_PR_REG") begin : WR_PR_REG
reg rnw_i;
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b0;
end else begin
// Only set RNW to 1 if there is a read pending and write is idle
// rnw_i <= (~wr_cmd_en & rd_cmd_en);
rnw_i <= (~awvalid & arvalid);
end
end
assign rnw = rnw_i;
end
else begin : WR_PR // if (C_RD_WR_ARB_ALGORITHM == "WR_PR") begin
// assign rnw = (~wr_cmd_en & rd_cmd_en);
assign rnw = (~awvalid & arvalid);
end
endgenerate
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_cmd_fsm.v
//
// Description:
// Simple state machine to handle sending commands from AXI to MC. The flow:
// 1. A transaction can only be initiaited when axvalid is true and data_rdy
// is true. For writes, data_rdy means that one completed BL8 or BL4 write
// data has been pushed into the MC write FIFOs. For read operations,
// data_rdy indicates that there is enough room to push the transaction into
// the read FIF & read transaction fifo in the shim. If the FIFO's in the
// read channel module is full, then the state machine waits for the
// FIFO's to drain out.
//
// 2. When CMD_EN is asserted, it remains high until we sample CMD_FULL in
// a low state. When CMD_EN == 1'b1, and CMD_FULL == 1'b0, then the command
// has been accepted. When the command is accepted, if the next_pending
// signal is high we will incremented to the next transaction and issue the
// cmd_en again when data_rdy is high. Otherwise we will go to the done
// state.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_mc_cmd_fsm #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// parameter to identify rd or wr instantation
// = 1 rd , = 0 wr
parameter integer C_MC_RD_INST = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output reg axready ,
input wire axvalid ,
output wire cmd_en ,
input wire cmd_full ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_rdy ,
// status signal for w_channel when command is written.
output wire cmd_en_last
);
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
assign cmd_en = (axvalid & data_rdy);
assign next = (~cmd_full & cmd_en);
assign cmd_en_last = next & ~next_pending;
always @(posedge clk) begin
if (reset)
axready <= 1'b0;
else
axready <= ~axvalid | cmd_en_last;
end
endmodule
`default_nettype wire

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// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_cmd_translator.v
//
// Description:
// INCR and WRAP burst modes are decoded in parallel and then the output is
// chosen based on the AxBURST value. FIXED burst mode is not supported and
// is mapped to the INCR command instead.
//
// Specifications:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_axi_mc_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MC_ADDR_WIDTH = 30,
// Width of AXI xDATA and MC xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// DRAM clock to AXI clock ratio
// supported values 2, 4
parameter integer C_MC_nCK_PER_CLK = 2,
// Static value of axsize
// Range: 2-5
parameter integer C_AXSIZE = 2,
// Instance for Read channel or write channel
parameter integer C_MC_RD_INST = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
input wire [1:0] axburst ,
input wire axvalid ,
input wire axready ,
output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr ,
output wire ignore_begin ,
output wire ignore_end ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_MC_BURST_MASK = {C_MC_ADDR_WIDTH{1'b1}} ^
{C_MC_BURST_LEN+(C_MC_nCK_PER_CLK/2){1'b1}};
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr_i;
wire [C_AXI_ADDR_WIDTH-1:0] axi_mc_incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] axi_mc_wrap_cmd_byte_addr;
wire wrap_next_pending;
wire incr_ignore_begin;
wire incr_ignore_end;
wire wrap_ignore_begin;
wire wrap_ignore_end;
wire axhandshake;
wire incr_axhandshake;
wire wrap_axhandshake;
wire incr_next;
wire wrap_next;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign axhandshake = axvalid & axready;
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign cmd_byte_addr = (C_MC_nCK_PER_CLK == 4) ?
(cmd_byte_addr_i >> C_AXSIZE-3) & P_MC_BURST_MASK :
(cmd_byte_addr_i >> C_AXSIZE-2) & P_MC_BURST_MASK;
assign cmd_byte_addr_i = (axburst[1]) ? axi_mc_wrap_cmd_byte_addr : axi_mc_incr_cmd_byte_addr;
assign ignore_begin = (axburst[1]) ? wrap_ignore_begin : incr_ignore_begin;
assign ignore_end = (axburst[1]) ? wrap_ignore_end : incr_ignore_end;
assign next_pending = (axburst[1]) ? wrap_next_pending : incr_next_pending;
assign incr_axhandshake = (axburst[1]) ? 1'b0 : axhandshake;
assign wrap_axhandshake = (axburst[1]) ? axhandshake : 1'b0;
assign incr_next = (axburst[1]) ? 1'b0 : next;
assign wrap_next = (axburst[1]) ? next : 1'b0;
mig_7series_v4_2_axi_mc_incr_cmd #
(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_MC_BURST_LEN (C_MC_BURST_LEN),
.C_AXSIZE (C_AXSIZE),
.C_MC_RD_INST (C_MC_RD_INST)
)
axi_mc_incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr ) ,
.axlen ( axlen ) ,
.axsize ( axsize ) ,
.axhandshake ( incr_axhandshake ) ,
.cmd_byte_addr ( axi_mc_incr_cmd_byte_addr ) ,
.ignore_begin ( incr_ignore_begin ) ,
.ignore_end ( incr_ignore_end ) ,
.next ( incr_next ) ,
.next_pending ( incr_next_pending )
);
mig_7series_v4_2_axi_mc_wrap_cmd #
(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH),
.C_MC_BURST_LEN (C_MC_BURST_LEN),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_AXSIZE (C_AXSIZE),
.C_MC_RD_INST (C_MC_RD_INST)
)
axi_mc_wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr ) ,
.axlen ( axlen ) ,
.axsize ( axsize ) ,
.axhandshake ( wrap_axhandshake ) ,
.ignore_begin ( wrap_ignore_begin ) ,
.ignore_end ( wrap_ignore_end ) ,
.cmd_byte_addr ( axi_mc_wrap_cmd_byte_addr ) ,
.next ( wrap_next ) ,
.next_pending ( wrap_next_pending )
);
endmodule
`default_nettype wire

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//-----------------------------------------------------------------------------
//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//Purpose:
// Synchronous, shallow FIFO that uses simple as a DP Memory.
// This requires about 1/2 the resources as a Distributed RAM DPRAM
// implementation.
//
// This FIFO will have the current data on the output when data is contained
// in the FIFO. When the FIFO is empty, the output data is invalid.
//
//Reference:
//Revision History:
//
//-----------------------------------------------
//
// MODULE: axi_mc_fifo
//
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
module mig_7series_v4_2_axi_mc_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = 0;
localparam [C_AWIDTH-1:0] C_FULL = C_DEPTH - 1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = C_DEPTH -2;
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH:0] cnt_read;
reg [C_AWIDTH:0] next_cnt_read;
wire [C_AWIDTH:0] cnt_read_plus1;
wire [C_AWIDTH:0] cnt_read_minus1;
wire [C_AWIDTH-1:0] read_addr;
///////////////////////////////////////
// Main FIFO Array
///////////////////////////////////////
assign read_addr = cnt_read;
assign dout = memory[read_addr];
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else cnt_read <= next_cnt_read;
end
assign cnt_read_plus1 = cnt_read + 1'b1;
assign cnt_read_minus1 = cnt_read - 1'b1;
always @(*) begin
next_cnt_read = cnt_read;
if ( wr_en & !rd_en) next_cnt_read = cnt_read_plus1;
else if (!wr_en & rd_en) next_cnt_read = cnt_read_minus1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = (cnt_read == C_FULL_PRE);
assign a_empty = (cnt_read == C_EMPTY_PRE);
endmodule // axi_mc_fifo
`default_nettype wire

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