858 lines
50 KiB
XML
858 lines
50 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="49" Path="C:/Users/Aleksa/Documents/EEVengers/Firmware/Artix7_PCIe/dso_top/dso_top.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Option Name="WTXSimExportSim" Val="80"/>
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<Option Name="WTActivehdlExportSim" Val="80"/>
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<Proxy FileSetName="design_1_axi_datamover_0_0"/>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci">
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<Proxy FileSetName="design_1_mig_7series_0_1"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
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<Proxy FileSetName="design_1_util_ds_buf_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
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<Proxy FileSetName="design_1_xdma_0_0"/>
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</CompFileExtendedInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../Spartan6_USB/dso_top/I2C_Transmit.v"/>
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../Spartan6_USB/dso_top/SPI_Transmit.v"/>
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/new/adc_to_datamover.v"/>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top_axixclk/dso_top_axixclk.srcs/sources_1/new/afifo.v"/>
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top_axixclk/dso_top_axixclk.srcs/sources_1/new/axixclk.v"/>
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<FileInfo>
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<FileInfo SFType="SVerilog">
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/new/combined_serdes.v"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="dso_top"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="ConstrsType" Val="XDC"/>
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<Filter Type="Srcs"/>
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<Config>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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<Config>
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<Option Name="TopModule" Val="design_1_axi_fifo_mm_s_0_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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<Config>
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<Option Name="TopModule" Val="design_1_axi_crossbar_0_1"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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<Option Name="TopModule" Val="design_1_axi_crossbar_0_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci"/>
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<Attr Name="ImportTime" Val="1614997392"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
|
|
<Option Name="TopModule" Val="clk_wiz_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
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|
</Config>
|
|
</FileSet>
|
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<FileSet Name="fifo_generator_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_generator_0">
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|
<File Path="$PSRCDIR/sources_1/ip/fifo_generator_0/fifo_generator_0.xci">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../../FPGA_Dev/dso_top_temp/PCIe_Test/PCIe_Test.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci"/>
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<Attr Name="ImportTime" Val="1615002098"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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|
<Option Name="TopModule" Val="fifo_generator_0"/>
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|
<Option Name="UseBlackboxStub" Val="1"/>
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|
</Config>
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</FileSet>
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|
<FileSet Name="design_1_xdma_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_xdma_0_0">
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|
<Config>
|
|
<Option Name="TopModule" Val="design_1_xdma_0_0"/>
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|
<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
|
|
<FileSet Name="design_1_mig_7series_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_mig_7series_0_1">
|
|
<Config>
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|
<Option Name="TopModule" Val="design_1_mig_7series_0_1"/>
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|
<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="design_1_util_ds_buf_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_util_ds_buf_0_1">
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|
<Config>
|
|
<Option Name="TopModule" Val="design_1_util_ds_buf_0_1"/>
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|
<Option Name="UseBlackboxStub" Val="1"/>
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|
</Config>
|
|
</FileSet>
|
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</FileSets>
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<Simulator Name="XSim">
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|
<Option Name="Description" Val="Vivado Simulator"/>
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|
<Option Name="CompiledLib" Val="0"/>
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</Simulator>
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<Simulator Name="ModelSim">
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|
<Option Name="Description" Val="ModelSim Simulator"/>
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|
</Simulator>
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|
<Simulator Name="Questa">
|
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
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|
</Simulator>
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|
<Simulator Name="Riviera">
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|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
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|
</Simulator>
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|
<Simulator Name="ActiveHDL">
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|
<Option Name="Description" Val="Active-HDL Simulator"/>
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|
</Simulator>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design">
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<Option Id="ControlSetOptThreshold">1</Option>
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<Option Id="Directive">1</Option>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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<Option Id="ControlSetOptThreshold">1</Option>
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<Option Id="Directive">1</Option>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<RQSFiles/>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design">
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<Option Id="ControlSetOptThreshold">1</Option>
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<Option Id="Directive">1</Option>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design">
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<Option Id="ControlSetOptThreshold">1</Option>
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<Option Id="Directive">1</Option>
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</Step>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design">
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<Option Id="ControlSetOptThreshold">1</Option>
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<Option Id="Directive">1</Option>
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</Step>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design">
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<Option Id="ControlSetOptThreshold">1</Option>
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<Option Id="Directive">1</Option>
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</Strategy>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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|
|
<Strategy Version="1" Minor="2">
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|
<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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|
<Step Id="synth_design">
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|
<Option Id="ControlSetOptThreshold">1</Option>
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|
<Option Id="Directive">1</Option>
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</Step>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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|
<Step Id="synth_design">
|
|
<Option Id="ControlSetOptThreshold">1</Option>
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|
<Option Id="Directive">1</Option>
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</Step>
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|
</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design">
|
|
<Option Id="ControlSetOptThreshold">1</Option>
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|
<Option Id="Directive">1</Option>
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</Step>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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|
<Step Id="synth_design">
|
|
<Option Id="ControlSetOptThreshold">1</Option>
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|
<Option Id="Directive">1</Option>
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</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
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|
<Step Id="synth_design">
|
|
<Option Id="ControlSetOptThreshold">1</Option>
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|
<Option Id="Directive">1</Option>
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|
</Step>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
|
|
<Step Id="synth_design">
|
|
<Option Id="ControlSetOptThreshold">1</Option>
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|
<Option Id="Directive">1</Option>
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|
</Step>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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|
<RQSFiles/>
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</Run>
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|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Flow_AreaOptimized_high" Flow="Vivado Synthesis 2020"/>
|
|
<Step Id="synth_design">
|
|
<Option Id="ControlSetOptThreshold">1</Option>
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|
<Option Id="Directive">1</Option>
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|
</Step>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_util_ds_buf_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_util_ds_buf_0_1" Part="xc7a35tcsg325-2" ConstrsSet="design_1_util_ds_buf_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_util_ds_buf_0_1_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="constrs_1" Description="Includes alternate algorithms for timing-driven optimization" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Performance_ExtraTimingOpt" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design">
|
|
<Option Id="Directive">8</Option>
|
|
</Step>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design">
|
|
<Option Id="Directive">8</Option>
|
|
</Step>
|
|
<Step Id="route_design">
|
|
<Option Id="Directive">1</Option>
|
|
</Step>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream">
|
|
<Option Id="BinFile">1</Option>
|
|
</Step>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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|
<RQSFiles/>
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</Run>
|
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<Run Id="design_1_axi_datamover_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_axi_datamover_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_datamover_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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|
<RQSFiles/>
|
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</Run>
|
|
<Run Id="design_1_axi_gpio_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_axi_gpio_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_gpio_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_util_ds_buf_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_util_ds_buf_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_util_ds_buf_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_axi_dwidth_converter_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_axi_dwidth_converter_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_dwidth_converter_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_axi_fifo_mm_s_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_axi_fifo_mm_s_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_fifo_mm_s_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_axi_crossbar_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_axi_crossbar_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_crossbar_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_axi_crossbar_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_axi_crossbar_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_crossbar_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_generator_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="fifo_generator_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_generator_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_xdma_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_xdma_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_xdma_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_mig_7series_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_mig_7series_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_mig_7series_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_1_util_ds_buf_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg325-2" ConstrsSet="design_1_util_ds_buf_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_util_ds_buf_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
</Runs>
|
|
<Board/>
|
|
<DashboardSummary Version="1" Minor="0">
|
|
<Dashboards>
|
|
<Dashboard Name="default_dashboard">
|
|
<Gadgets>
|
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
</Gadget>
|
|
</Gadgets>
|
|
</Dashboard>
|
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
</Dashboards>
|
|
</DashboardSummary>
|
|
</Project>
|