90 lines
3.5 KiB
Plaintext
90 lines
3.5 KiB
Plaintext
Protel Design System Design Rule Check
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PCB File : C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc
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Date : 2022-01-23
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Time : 1:13:44 PM
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Processing Rule : Clearance Constraint (Gap=0.127mm) (InNet('PG_1V0')),(All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.127mm) (All),(All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.127mm) (InComponent('U7')),(InComponent('U7'))
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.127mm) (isVia),(IsPad or IsVia)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.1mm) (isVia),(isPad and (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')or HasFootprint('GEN_R_0402')or HasFootprint('GEN_C_0402')or HasFootprint('MX_WSON8')))
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.1mm) (HasFootprint('GEN_C_0201') or HasFootprint('GEN_R_0201')),(All)
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Rule Violations :0
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Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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Rule Violations :0
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Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.127mm) (Max=0.213mm) (Preferred=0.127mm) ((InNetClass('DDR3 ADDR')) OR (InNetClass('DQ0')) OR (InNetClass('DQ1')) OR (InNetClass('DQ2')) OR (InNetClass('DQ3')))
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.254mm) (All)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.1mm) (Max=0.254mm) (Preferred=0.127mm) (InNet('PG_1V0'))
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Rule Violations :0
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Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
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Rule Violations :0
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Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=3.2mm) (All)
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Rule Violations :0
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Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Minimum Solder Mask Sliver (Gap=0.098mm) (All),(All)
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Rule Violations :0
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Processing Rule : Net Antennae (Tolerance=0mm) (All)
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('ADC LVDS'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS1') or InNetClass('DQ1'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('ADC LVDS'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS3') or InNetClass('DQ3'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS2') or InNetClass('DQ2'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (Disabled)(InNetClass('DDR3 ADDR'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=2ps) (InDifferentialPairClass('DDR3_CLK') or InDifferentialPairClass('DQS0') or InDifferentialPairClass('DQS1') or InDifferentialPairClass('DQS2') or InDifferentialPairClass('DQS3'))
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Rule Violations :0
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Processing Rule : Matched Lengths(Delay Tolerance=5ps) (InDifferentialPairClass('DQS0') or InNetClass('DQ0'))
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Rule Violations :0
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Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (All),(All)
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Rule Violations :0
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Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
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Rule Violations :0
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Violations Detected : 0
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Waived Violations : 0
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Time Elapsed : 00:00:02 |