9 lines
754 B
Plaintext
9 lines
754 B
Plaintext
Record=TopLevelDocument|FileName=Connectors.SchDoc|SheetNumber=1
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Record=NoMainPathDocument|SourceDocument=Connectors.SchDoc|FileName=DDR3L.SchDoc|SheetNumber=7
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Record=NoMainPathDocument|SourceDocument=Connectors.SchDoc|FileName=FPGA_Bank_IO.SchDoc|SheetNumber=2
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Record=NoMainPathDocument|SourceDocument=Connectors.SchDoc|FileName=FPGA_Banks_DDR3.SchDoc|SheetNumber=3
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Record=NoMainPathDocument|SourceDocument=Connectors.SchDoc|FileName=FPGA_CFG.SchDoc|SheetNumber=5
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Record=NoMainPathDocument|SourceDocument=Connectors.SchDoc|FileName=FPGA_MGT.SchDoc|SheetNumber=4
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Record=NoMainPathDocument|SourceDocument=Connectors.SchDoc|FileName=FPGA_PWR.SchDoc|SheetNumber=6
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Record=NoMainPathDocument|SourceDocument=Connectors.SchDoc|FileName=PWR.SchDoc|SheetNumber=8
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