222 lines
26 KiB
Plaintext
222 lines
26 KiB
Plaintext
[OutputJobFile]
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Version=1.0
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Caption=
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Description=
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VaultGUID=
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ItemGUID=
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ItemHRID=
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RevisionGUID=
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RevisionId=
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VaultHRID=
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AutoItemHRID=
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NextRevId=
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FolderGUID=
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LifeCycleDefinitionGUID=
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RevisionNamingSchemeGUID=
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[OutputGroup1]
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Name=Job1.OutJob
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Description=
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TargetOutputMedium=Folder Structure
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VariantName=[No Variations]
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VariantScope=1
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CurrentConfigurationName=
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TargetPrinter=Microsoft Print to PDF
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PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
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OutputMedium1=Print Job
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OutputMedium1_Type=Printer
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OutputMedium1_Printer=
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OutputMedium1_PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
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OutputMedium2=PDF
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OutputMedium2_Type=Publish
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OutputMedium3=Folder Structure
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OutputMedium3_Type=GeneratedFiles
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OutputMedium4=Video
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OutputMedium4_Type=Multimedia
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OutputType1=Gerber
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OutputName1=Gerber Files
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OutputCategory1=Fabrication
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OutputDocumentPath1=FPGA_Module_Panel.PcbDoc
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OutputVariantName1=
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OutputEnabled1=1
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OutputEnabled1_OutputMedium1=0
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OutputEnabled1_OutputMedium2=0
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OutputEnabled1_OutputMedium3=1
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OutputEnabled1_OutputMedium4=0
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OutputDefault1=0
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Configuration1_Name1=OutputConfigurationParameter1
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Configuration1_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|BoardID=NWUHWUCY|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=KeepLeadingAndTrailingZeroes|MaxApertureSize=2500000|MergePadAndRegion=False|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16973835~1,16973833~1,16973831~1,16908289~1,16908295~1,16777217~1,16777220~1,16777218~1,16777219~1,16777221~1,16842751~1|PlotBoardProfile=False|PlotBoardProfileFileName=FPGA_Module_Panel_Profile.gbr|PlotDrillDrawingLayerPair0_Backdrill=False|PlotDrillDrawingLayerPair0_Checked=True|PlotDrillDrawingLayerPair0_DrillType=Regular|PlotDrillDrawingLayerPair0_FileName=FPGA_Module_Panel_Drill_Drawing.gbr|PlotDrillDrawingLayerPair0_HighLayer=Bottom Layer|PlotDrillDrawingLayerPair0_LowLayer=Top Layer|PlotDrillGuideLayerPair0_Backdrill=False|PlotDrillGuideLayerPair0_Checked=True|PlotDrillGuideLayerPair0_DrillType=Regular|PlotDrillGuideLayerPair0_FileName=FPGA_Module_Panel_Drillguide.gbr|PlotDrillGuideLayerPair0_HighLayer=Bottom Layer|PlotDrillGuideLayerPair0_LowLayer=Top Layer|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|UserLayerName.Caption0=FPGA_Module_Panel_Keep-out.gbr|UserLayerName.Caption1=FPGA_Module_Panel_Paste_Top.gbr|UserLayerName.Caption10=FPGA_Module_Panel_Soldermask_Bot.gbr|UserLayerName.Caption11=FPGA_Module_Panel_Copper_Inner_3.gbr|UserLayerName.Caption12=FPGA_Module_Panel_Copper_Bottom.gbr|UserLayerName.Caption13=FPGA_Module_Panel_Bottom_3D_Body.gbr|UserLayerName.Caption14=FPGA_Module_Panel_Copper_Top.gbr|UserLayerName.Caption15=FPGA_Module_Panel_Legend_Bot.gbr|UserLayerName.Caption16=FPGA_Module_Panel_Pads_Top.gbr|UserLayerName.Caption17=FPGA_Module_Panel_Top_3D_Body.gbr|UserLayerName.Caption18=FPGA_Module_Panel_Top_Assembly.gbr|UserLayerName.Caption19=FPGA_Module_Panel_Top_Component_Center.gbr|UserLayerName.Caption2=FPGA_Module_Panel_Legend_Top.gbr|UserLayerName.Caption20=FPGA_Module_Panel_Copper_Inner_1.gbr|UserLayerName.Caption21=FPGA_Module_Panel_Board Outline.gbr|UserLayerName.Caption22=FPGA_Module_Panel_Copper_Inner_4.gbr|UserLayerName.Caption23=FPGA_Module_Panel_Bottom_Courtyard.gbr|UserLayerName.Caption24=FPGA_Module_Panel_Paste_Bot.gbr|UserLayerName.Caption3=FPGA_Module_Panel_Soldermask_Top.gbr|UserLayerName.Caption4=FPGA_Module_Panel_Bottom_Component_Center.gbr|UserLayerName.Caption5=FPGA_Module_Panel_Top_Courtyard.gbr|UserLayerName.Caption6=FPGA_Module_Panel_Pads_Bot.gbr|UserLayerName.Caption7=FPGA_Module_Panel_Copper_Inner_2.gbr|UserLayerName.Caption8=FPGA_Module_Panel_Bottom_Assembly.gbr|UserLayerName.Caption9=FPGA_Module_Panel_Fab_Notes.gbr|UserLayerName.Count=25|UserLayerName.Layer0=16973837|UserLayerName.Layer1=16973832|UserLayerName.Layer10=16973835|UserLayerName.Layer11=16777219|UserLayerName.Layer12=16842751|UserLayerName.Layer13=16908302|UserLayerName.Layer14=16777217|UserLayerName.Layer15=16973831|UserLayerName.Layer16=16973848|UserLayerName.Layer17=16908301|UserLayerName.Layer18=16908297|UserLayerName.Layer19=16908299|UserLayerName.Layer2=16973830|UserLayerName.Layer20=16777220|UserLayerName.Layer21=16908289|UserLayerName.Layer22=16777221|UserLayerName.Layer23=16908291|UserLayerName.Layer24=16973833|UserLayerName.Layer3=16973834|UserLayerName.Layer4=16908300|UserLayerName.Layer5=16908290|UserLayerName.Layer6=16973849|UserLayerName.Layer7=16777218|UserLayerName.Layer8=16908298|UserLayerName.Layer9=16908295|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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OutputType2=NC Drill
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OutputName2=NC Drill Files
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OutputCategory2=Fabrication
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OutputDocumentPath2=FPGA_Module_Panel.PcbDoc
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OutputVariantName2=
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OutputEnabled2=1
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OutputEnabled2_OutputMedium1=0
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OutputEnabled2_OutputMedium2=0
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OutputEnabled2_OutputMedium3=2
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OutputEnabled2_OutputMedium4=0
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OutputDefault2=0
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Configuration2_Name1=OutputConfigurationParameter1
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Configuration2_Item1=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|GenerateSeparateViaTypeFiles=False|NumberOfDecimals=4|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=KeepLeadingAndTrailingZeroes|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module.PcbDoc
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OutputType3=Assembly
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OutputName3=Assembly Drawings
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OutputCategory3=Assembly
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OutputDocumentPath3=FPGA_Module.PcbDoc
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OutputVariantName3=
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OutputEnabled3=0
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OutputEnabled3_OutputMedium1=0
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OutputEnabled3_OutputMedium2=1
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OutputEnabled3_OutputMedium3=0
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OutputEnabled3_OutputMedium4=0
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OutputDefault3=0
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PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=2.27|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
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Configuration3_Name1=OutputConfigurationParameter1
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Configuration3_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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Configuration3_Name2=OutputConfigurationParameter2
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Configuration3_Item2=IncludeBoardCutouts=False|IncludeBottomLayerComponents=False|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Top LayerAssembly Drawing|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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Configuration3_Name3=OutputConfigurationParameter3
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Configuration3_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical9|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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Configuration3_Name4=OutputConfigurationParameter4
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Configuration3_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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Configuration3_Name5=OutputConfigurationParameter5
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Configuration3_Item5=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=False|IncludeViewports=True|Index=1|Mirror=False|Name=Bottom LayerAssembly Drawing|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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Configuration3_Name6=OutputConfigurationParameter6
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Configuration3_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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Configuration3_Name7=OutputConfigurationParameter7
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Configuration3_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical10|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
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PcbPrintPreferences3=SubsititueFont_Default=True|SubsititueFont_Serif=True|SubsititueFont_SansSerif=True|PrintKeepOuts=False|NetColorOverride=True|PrintPositivePlaneLayers=False|V7_M0.Name=Mechanical Layer 1|V7_M0.Value=True|V7_M1.Name=Mechanical Layer 2|V7_M1.Value=True|V7_M2.Name=Mechanical Layer 3|V7_M2.Value=True|V7_M3.Name=Mechanical Layer 4|V7_M3.Value=True|V7_M4.Name=Mechanical Layer 5|V7_M4.Value=True|V7_M5.Name=Mechanical Layer 6|V7_M5.Value=True|V7_M6.Name=Mechanical Layer 7|V7_M6.Value=True|V7_M7.Name=Mechanical Layer 8|V7_M7.Value=True|V7_M8.Name=Mechanical Layer 9|V7_M8.Value=True|V7_M9.Name=Mechanical Layer 10|V7_M9.Value=True|V7_M10.Name=Mechanical Layer 11|V7_M10.Value=True|V7_M11.Name=Mechanical Layer 12|V7_M11.Value=True|V7_M12.Name=Mechanical Layer 13|V7_M12.Value=True|V7_M13.Name=Mechanical Layer 14|V7_M13.Value=True|V7_M14.Name=Mechanical Layer 15|V7_M14.Value=True|V7_M15.Name=Mechanical Layer 16|V7_M15.Value=True|V7_G0.Name=Top Layer|V7_G0.Value=30|V7_G1.Name=Mid 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For Mechanical15=90|Gray Level For Mechanical16=90|Gray Level For DrillDrawing=0|Gray Level For MultiLayer=0|Gray Level For ConnectLayer=0|Gray Level For BackGroundLayer=255|Gray Level For DRCErrorLayer=0|Gray Level For HighlightLayer=0|Gray Level For GridColor1=0|Gray Level For GridColor10=0|Gray Level For PadHoleLayer=210|Gray Level For ViaHoleLayer=210|Color For TopLayer=255|Color For MidLayer1=32768|Color For MidLayer2=65280|Color For MidLayer3=8388608|Color For MidLayer4=16776960|Color For MidLayer5=8388736|Color For MidLayer6=16711935|Color For MidLayer7=32896|Color For MidLayer8=65535|Color For MidLayer9=8421504|Color For MidLayer10=32768|Color For MidLayer11=8388736|Color For MidLayer12=8421376|Color For MidLayer13=12632256|Color For MidLayer14=128|Color For MidLayer15=32768|Color For MidLayer16=65280|Color For MidLayer17=8388608|Color For MidLayer18=16776960|Color For MidLayer19=8388736|Color For MidLayer20=16711935|Color For MidLayer21=32896|Color For MidLayer22=65535|Color For MidLayer23=8421504|Color For MidLayer24=32768|Color For MidLayer25=8388736|Color For MidLayer26=8421376|Color For MidLayer27=12632256|Color For MidLayer28=8421376|Color For MidLayer29=12632256|Color For MidLayer30=128|Color For BottomLayer=16711680|Color For TopOverlay=32768|Color For BottomOverlay=7585984|Color For TopPaste=8388736|Color For BottomPaste=128|Color For TopSolder=3162822|Color For BottomSolder=7307173|Color For InternalPlane1=32768|Color For InternalPlane2=128|Color For InternalPlane3=8388736|Color For InternalPlane4=8421376|Color For InternalPlane5=32768|Color For InternalPlane6=128|Color For InternalPlane7=8388736|Color For InternalPlane8=8421376|Color For InternalPlane9=32768|Color For InternalPlane10=128|Color For InternalPlane11=8388736|Color For InternalPlane12=8421376|Color For InternalPlane13=32768|Color For InternalPlane14=128|Color For InternalPlane15=8388736|Color For InternalPlane16=8421376|Color For DrillGuide=128|Color For KeepOutLayer=8388736|Color For Mechanical1=8388736|Color For Mechanical2=8421376|Color For Mechanical3=32768|Color For Mechanical4=0|Color For Mechanical5=8388736|Color For Mechanical6=8421376|Color For Mechanical7=32768|Color For Mechanical8=0|Color For Mechanical9=8388736|Color For Mechanical10=8421376|Color For Mechanical11=32768|Color For Mechanical12=0|Color For Mechanical13=8388736|Color For Mechanical14=8421376|Color For Mechanical15=32768|Color For Mechanical16=0|Color For DrillDrawing=3408013|Color For MultiLayer=8421504|Color For ConnectLayer=8421376|Color For BackGroundLayer=15269887|Color For DRCErrorLayer=65280|Color For HighlightLayer=65535|Color For GridColor1=12632256|Color For GridColor10=11913679|Color For PadHoleLayer=6899487|Color For ViaHoleLayer=9279142
|
|
OutputType4=Pick Place
|
|
OutputName4=Generates pick and place files
|
|
OutputCategory4=Assembly
|
|
OutputDocumentPath4=FPGA_Module.PcbDoc
|
|
OutputVariantName4=
|
|
OutputEnabled4=1
|
|
OutputEnabled4_OutputMedium1=0
|
|
OutputEnabled4_OutputMedium2=0
|
|
OutputEnabled4_OutputMedium3=3
|
|
OutputEnabled4_OutputMedium4=0
|
|
OutputDefault4=0
|
|
Configuration4_Name1=OutputConfigurationParameter1
|
|
Configuration4_Item1=Record=PickPlaceView|Units=Imperial|GenerateCSVFormat=False|GenerateTextFormat=True|ShowUnits=False|Separator= |ExcludeFilterParam=False|IncludeVariations=False|IncludeStandardNoBOM=True|Filter= |FilterActive=False|YFlip=False|Column#1=Name:Designator,Fixed:True,Metric:False,Visible:True,Sort:None,Position:0|Column#2=Name:Comment,Fixed:True,Metric:False,Visible:True,Sort:None,Position:1|Column#3=Name:Layer,Fixed:True,Metric:False,Visible:True,Sort:None,Position:2|Column#4=Name:Footprint,Fixed:True,Metric:False,Visible:True,Sort:None,Position:3|Column#5=Name:Footprint Description,Fixed:True,Metric:False,Visible:False,Sort:None,Position:4|Column#6=Name:Center-X,Fixed:True,Metric:True,Visible:True,Sort:None,Position:5|Column#7=Name:Center-Y,Fixed:True,Metric:True,Visible:True,Sort:None,Position:6|Column#8=Name:Rotation,Fixed:True,Metric:False,Visible:True,Sort:None,Position:7|Column#9=Name:Description,Fixed:True,Metric:False,Visible:True,Sort:None,Position:8|Column#10=Name:ComponentKind,Fixed:True,Metric:False,Visible:False,Sort:None,Position:9|Column#11=Name:Height,Fixed:True,Metric:True,Visible:False,Sort:None,Position:10|Column#12=Name:Ref-X,Fixed:True,Metric:True,Visible:False,Sort:None,Position:11|Column#13=Name:Ref-Y,Fixed:True,Metric:True,Visible:False,Sort:None,Position:12|Column#14=Name:Pad-X,Fixed:True,Metric:True,Visible:False,Sort:None,Position:13|Column#15=Name:Pad-Y,Fixed:True,Metric:True,Visible:False,Sort:None,Position:14|Column#16=Name:Variation,Fixed:True,Metric:False,Visible:False,Sort:None,Position:15|DocumentPath=C:\Users\Aleksa\Documents\Altium\FPGA_Module\FPGA_Module_Panel.PcbDoc
|
|
OutputType5=BOM_PartType
|
|
OutputName5=Bill of Materials
|
|
OutputCategory5=Report
|
|
OutputDocumentPath5=FPGA_Module.PcbDoc
|
|
OutputVariantName5=
|
|
OutputEnabled5=1
|
|
OutputEnabled5_OutputMedium1=0
|
|
OutputEnabled5_OutputMedium2=0
|
|
OutputEnabled5_OutputMedium3=4
|
|
OutputEnabled5_OutputMedium4=0
|
|
OutputDefault5=0
|
|
PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
|
Configuration5_Name1=ColumnNameFormat
|
|
Configuration5_Item1=CaptionAsName
|
|
Configuration5_Name2=General
|
|
Configuration5_Item2=OpenExported=False|AddToProject=False|ReportBOMViolationsInMessages=False|ForceFit=False|NotFitted=False|Database=False|DatabasePriority=False|IncludePcbData=False|IncludeVaultData=False|IncludeCloudData=False|IncludeDocumentData=True|IncludeAlternatives=False|ShowExportOptions=True|TemplateFilename=|TemplateVaultGuid=|TemplateItemGuid=|TemplateRevisionGuid=|BatchMode=5|FormWidth=1913|FormHeight=710|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=USD|SolutionsPerItem=1|SuppliersPerSolution=1|ViewType=0|UseDirectApi=False|BomSetName=
|
|
Configuration5_Name3=GroupOrder
|
|
Configuration5_Item3=Comment=True|Footprint=True
|
|
Configuration5_Name4=SortOrder
|
|
Configuration5_Item4=Designator=Up|Comment=Up|Footprint=Up
|
|
Configuration5_Name5=VisibleOrder
|
|
Configuration5_Item5=Comment=120|Designator=120|Footprint=120|LibRef=120|Quantity=120|Supplier Part Number 1=228
|
|
Configuration5_Name6=VisibleOrder_Flat
|
|
Configuration5_Item6=Comment=120|Designator=120|Footprint=120|LibRef=120|Quantity=120|Supplier Part Number 1=228
|
|
|
|
[PublishSettings]
|
|
OutputFilePath2=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Project Outputs for FPGA_Module\Job1.PDF
|
|
ReleaseManaged2=1
|
|
OutputBasePath2=Project Outputs for FPGA_Module
|
|
OutputPathMedia2=
|
|
OutputPathMediaValue2=
|
|
OutputPathOutputer2=[Output Type]
|
|
OutputPathOutputerPrefix2=
|
|
OutputPathOutputerValue2=
|
|
OutputFileName2=Assembly Drawing.PDF
|
|
OutputFileNameMulti2=
|
|
UseOutputNameForMulti2=0
|
|
OutputFileNameSpecial2=
|
|
OpenOutput2=1
|
|
PromptOverwrite2=1
|
|
PublishMethod2=0
|
|
ZoomLevel2=50
|
|
FitSCHPrintSizeToDoc2=1
|
|
FitPCBPrintSizeToDoc2=1
|
|
GenerateNetsInfo2=1
|
|
MarkPins2=1
|
|
MarkNetLabels2=1
|
|
MarkPortsId2=1
|
|
GenerateTOC2=1
|
|
ShowComponentParameters2=1
|
|
GlobalBookmarks2=0
|
|
PDFACompliance2=Disabled
|
|
PDFVersion2=Default
|
|
OutputFilePath3=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Project Outputs for FPGA_Module\
|
|
ReleaseManaged3=1
|
|
OutputBasePath3=Project Outputs for FPGA_Module
|
|
OutputPathMedia3=
|
|
OutputPathMediaValue3=
|
|
OutputPathOutputer3=[Output Type]
|
|
OutputPathOutputerPrefix3=
|
|
OutputPathOutputerValue3=
|
|
OutputFileName3=
|
|
OutputFileNameMulti3=
|
|
UseOutputNameForMulti3=1
|
|
OutputFileNameSpecial3=
|
|
OpenOutput3=1
|
|
OutputFilePath4=
|
|
ReleaseManaged4=1
|
|
OutputBasePath4=Project Outputs for FPGA_Module
|
|
OutputPathMedia4=
|
|
OutputPathMediaValue4=
|
|
OutputPathOutputer4=[Output Type]
|
|
OutputPathOutputerPrefix4=
|
|
OutputPathOutputerValue4=
|
|
OutputFileName4=
|
|
OutputFileNameMulti4=
|
|
UseOutputNameForMulti4=1
|
|
OutputFileNameSpecial4=
|
|
OpenOutput4=1
|
|
PromptOverwrite4=1
|
|
PublishMethod4=5
|
|
ZoomLevel4=50
|
|
FitSCHPrintSizeToDoc4=1
|
|
FitPCBPrintSizeToDoc4=1
|
|
GenerateNetsInfo4=1
|
|
MarkPins4=1
|
|
MarkNetLabels4=1
|
|
MarkPortsId4=1
|
|
MediaFormat4=Windows Media file (*.wmv,*.wma,*.asf)
|
|
FixedDimensions4=1
|
|
Width4=352
|
|
Height4=288
|
|
MultiFile4=0
|
|
FramesPerSecond4=25
|
|
FramesPerSecondDenom4=1
|
|
AviPixelFormat4=7
|
|
AviCompression4=MP42 MS-MPEG4 V2
|
|
AviQuality4=100
|
|
FFmpegVideoCodecId4=12
|
|
FFmpegPixelFormat4=0
|
|
FFmpegQuality4=80
|
|
WmvVideoCodecName4=Windows Media Video V7
|
|
WmvQuality4=80
|
|
|
|
[GeneratedFilesSettings]
|
|
RelativeOutputPath2=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Project Outputs for FPGA_Module\Job1.PDF
|
|
OpenOutputs2=1
|
|
RelativeOutputPath3=C:\Users\Aleksa\Documents\Altium\FPGA_Module\Project Outputs for FPGA_Module\
|
|
OpenOutputs3=1
|
|
AddToProject3=1
|
|
TimestampFolder3=0
|
|
UseOutputName3=0
|
|
OpenODBOutput3=0
|
|
OpenGerberOutput3=0
|
|
OpenNCDrillOutput3=0
|
|
OpenIPCOutput3=0
|
|
EnableReload3=0
|
|
RelativeOutputPath4=
|
|
OpenOutputs4=1
|
|
|