14 lines
3.2 KiB
Plaintext
14 lines
3.2 KiB
Plaintext
Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=ADC|SchDesignator=ADC|FileName=ADC.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=ADC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=FPGA Module|SchDesignator=FPGA Module|FileName=FPGA.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=Front End|SchDesignator=Front End|FileName=FE.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=FE.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=PCIe_X4|SchDesignator=PCIe_X4|FileName=CON_PCIe_X4.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=CON_PCIe_X4.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=LEDs|SchDesignator=LEDs|FileName=LEDs.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=LEDs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FE.SchDoc|Designator=CH1|SchDesignator=CH1|FileName=FE_Channel.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FE.SchDoc|Designator=CH2|SchDesignator=CH2|FileName=FE_Channel.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FE.SchDoc|Designator=CH3|SchDesignator=CH3|FileName=FE_Channel.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FE.SchDoc|Designator=CH4|SchDesignator=CH4|FileName=FE_Channel.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FE_Channel.SchDoc|Designator=Buffer|SchDesignator=Buffer|FileName=Buffer.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=Buffer.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FE_Channel.SchDoc|Designator=Input Coupling and Attenuation|SchDesignator=Input Coupling and Attenuation|FileName=Input.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=Input.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FE_Channel.SchDoc|Designator=PGA|SchDesignator=PGA|FileName=PGA.SchDoc|SheetNumber= |SymbolType=Normal|RawFileName=PGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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