206 lines
7.0 KiB
C
206 lines
7.0 KiB
C
/*
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* XDMA Register Map
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* =================
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*
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* Copyright 2018 Xilinx Inc.
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* Copyright 2010-2012 Sidebranch
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* Copyright 2010-2012 Leon Woestenberg <leon@sidebranch.com>
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*
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* Maintainer:
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* -----------
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* Alexander Hornburg <alexander.hornburg@xilinx.com>
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*
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* References:
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* -----------
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* [1] pg195-pcie-dma.pdf - DMA/Bridge Subsystem for PCI Express v4.0 - Product Guide
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*/
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#pragma once
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// ========================= include dependencies =================================================
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// ========================= declarations =================================================
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#define LIMIT_TO_64(x) (x & 0xFFFFFFFFFFFFFFFFULL)
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#define LIMIT_TO_32(x) (x & 0x00000000FFFFFFFFUL)
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#define LIMIT_TO_16(x) (x & 0x000000000000FFFFUL)
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#define CLR_MASK(x, mask) ((x) &= ~(mask));
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#define SET_MASK(x, mask) ((x) |= (mask));
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#define BIT_N(n) (1 << n)
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// block identification bits
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#define XDMA_ID_MASK (0xFFF00000UL)
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#define XDMA_ID (0x1FC00000UL)
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#define BLOCK_ID_MASK (0xFFFF0000UL)
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#define IRQ_BLOCK_ID (XDMA_ID | 0x20000UL)
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#define CONFIG_BLOCK_ID (XDMA_ID | 0x30000UL)
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#define XDMA_ID_ST_BIT (BIT_N(15))
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// Block module offsets
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#define BLOCK_OFFSET (0x1000UL)
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#define IRQ_BLOCK_OFFSET (2 * BLOCK_OFFSET)
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#define CONFIG_BLOCK_OFFSET (3 * BLOCK_OFFSET)
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#define SGDMA_BLOCK_OFFSET (4 * BLOCK_OFFSET)
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#define SGDMA_COMMON_BLOCK_OFFSET (6 * BLOCK_OFFSET)
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#define ENGINE_OFFSET (0x100UL)
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//bits of the SGDMA engine control register
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#define XDMA_CTRL_RUN_BIT (BIT_N(0))
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#define XDMA_CTRL_IE_DESC_STOPPED (BIT_N(1))
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#define XDMA_CTRL_IE_DESC_COMPLETED (BIT_N(2))
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#define XDMA_CTRL_IE_ALIGNMENT_MISMATCH (BIT_N(3))
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#define XDMA_CTRL_IE_MAGIC_STOPPED (BIT_N(4))
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#define XDMA_CTRL_IE_INVALID_LENGTH (BIT_N(5))
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#define XDMA_CTRL_IE_IDLE_STOPPED (BIT_N(6))
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#define XDMA_CTRL_IE_READ_ERROR (0x1f << 9)
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#define XDMA_CTRL_IE_WRITE_ERROR (0x1f << 14)
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#define XDMA_CTRL_IE_DESCRIPTOR_ERROR (0x1f << 19)
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#define XDMA_CTRL_NON_INCR_ADDR (BIT_N(25))
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#define XDMA_CTRL_POLL_MODE (BIT_N(26))
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#define XDMA_CTRL_RST (BIT_N(31))
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#define XDMA_CTRL_IE_ALL (XDMA_CTRL_IE_DESC_STOPPED | XDMA_CTRL_IE_DESC_COMPLETED \
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| XDMA_CTRL_IE_ALIGNMENT_MISMATCH | XDMA_CTRL_IE_MAGIC_STOPPED \
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| XDMA_CTRL_IE_INVALID_LENGTH | XDMA_CTRL_IE_READ_ERROR | XDMA_CTRL_IE_WRITE_ERROR\
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| XDMA_CTRL_IE_DESCRIPTOR_ERROR)
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// bits of the SGDMA engine status register
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#define XDMA_BUSY_BIT (BIT_N(0))
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#define XDMA_DESCRIPTOR_STOPPED_BIT (BIT_N(1))
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#define XDMA_DESCRIPTOR_COMPLETED_BIT (BIT_N(2))
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#define XDMA_ALIGN_MISMATCH_BIT (BIT_N(3))
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#define XDMA_MAGIC_STOPPED_BIT (BIT_N(4))
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#define XDMA_FETCH_STOPPED_BIT (BIT_N(5))
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#define XDMA_IDLE_STOPPED_BIT (BIT_N(6))
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#define XDMA_STAT_READ_ERROR (0x1fUL * BIT_N(9))
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#define XDMA_STAT_DESCRIPTOR_ERROR (0x1fUL * BIT_N(19))
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#define XDMA_ENGINE_STOPPED_OK (0UL)
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#define XDMA_STAT_EXPECTED_ZERO (XDMA_BUSY_BIT | XDMA_MAGIC_STOPPED_BIT | \
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XDMA_FETCH_STOPPED_BIT | XDMA_ALIGN_MISMATCH_BIT | \
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XDMA_STAT_READ_ERROR | XDMA_STAT_DESCRIPTOR_ERROR)
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// bits of the SGDMA descriptor control field
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#define XDMA_DESC_STOP_BIT (BIT_N(0))
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#define XDMA_DESC_COMPLETED_BIT (BIT_N(1))
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#define XDMA_DESC_EOP_BIT (BIT_N(4))
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#define XDMA_RESULT_EOP_BIT (BIT_N(0))
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// Engine performance control register bits
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#define XDMA_PERF_RUN BIT_N(0)
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#define XDMA_PERF_CLEAR BIT_N(1)
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#define XDMA_PERF_AUTO BIT_N(2)
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#pragma pack(1)
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/// H2C/C2H Channel Registers (H2C: 0x0, C2H: 0x1000)
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/// To avoid Read-Modify-Write errors in concurrent systems, some registers can be set via
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/// additional mirror registers.
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/// - W1S (write 1 to set) - only the bits set will be set in the underlying register. all other
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/// bits are ignored.
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/// - W1C (write 1 to clear)- only the bits set will be cleared in the underlying register. all other
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/// bits are ignored.
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typedef struct {
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UINT32 identifier;
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UINT32 control;
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UINT32 controlW1S; // write 1 to set
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UINT32 controlW1C; // write 1 to clear
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UINT32 reserved_1[12];
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UINT32 status; // status register { 6'h10, 2'b0 } is 0x40
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UINT32 statusRC;
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UINT32 completedDescCount; // number of completed descriptors
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UINT32 alignments;
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UINT32 reserved_2[14];
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UINT32 pollModeWbLo;
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UINT32 pollModeWbHi;
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UINT32 intEnableMask;
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UINT32 intEnableMaskW1S;
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UINT32 intEnableMaskW1C;
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UINT32 reserved_3[9];
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UINT32 perfCtrl;
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UINT32 perfCycLo;
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UINT32 perfCycHi;
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UINT32 perfDatLo;
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UINT32 perfDatHi;
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UINT32 perfPndLo;
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UINT32 perfPndHi;
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} XDMA_ENGINE_REGS;
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/// IRQ Block Registers (0x2000)
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typedef struct {
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UINT32 identifier;
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UINT32 userIntEnable;
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UINT32 userIntEnableW1S;
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UINT32 userIntEnableW1C;
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UINT32 channelIntEnable;
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UINT32 channelIntEnableW1S;
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UINT32 channelIntEnableW1C;
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UINT32 reserved_1[9];
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UINT32 userIntRequest;
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UINT32 channelIntRequest;
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UINT32 userIntPending;
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UINT32 channelIntPending;
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UINT32 reserved_2[12];
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UINT32 userVector[4];
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UINT32 reserved_3[4];
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UINT32 channelVector[2];
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} XDMA_IRQ_REGS;
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/// Config Block Registers (0x3000)
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typedef struct {
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UINT32 identifier;
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UINT32 busDev;
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UINT32 pcieMPS;
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UINT32 pcieMRRS;
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UINT32 systemId;
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UINT32 msiEnable;
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UINT32 pcieWidth;
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UINT32 pcieControl; // 0x1C
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UINT32 reserved_1[8];
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UINT32 userMPS; // 0x40
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UINT32 userMRRS;
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UINT32 reserved_2[6];
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UINT32 writeFlushTimeout; // 0x60
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} XDMA_CONFIG_REGS;
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/// H2C/C2H SGDMA Registers (H2C: 0x4000, C2H:0x5000)
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typedef struct {
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UINT32 identifier;
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UINT32 reserved_1[31];
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UINT32 firstDescLo;
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UINT32 firstDescHi;
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UINT32 firstDescAdj;
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UINT32 descCredits; //!< Writes to this register will add descriptor credits for the channel.
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} XDMA_SGDMA_REGS, *PXDMA_SGDMA_REGS;
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/// SGDMA Common Registers (0x6000)
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typedef struct {
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UINT32 identifier; // 0x00
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UINT32 reserved_1[3];
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UINT32 control; // 0x10
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UINT32 controlW1S; // 0x14
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UINT32 controlW1C; // 0x18
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UINT32 reserved_2;
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UINT32 creditModeEnable; // 0x20
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UINT32 creditModeEnableW1S; // 0x24
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UINT32 creditModeEnableW1C; // 0x28
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} XDMA_SGDMA_COMMON_REGS, *PXDMA_SGDMA_COMMON_REGS;
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#pragma pack()
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#define EXPECT(EXP) ASSERTMSG(#EXP, EXP)
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#define ENSURES(EXP) ASSERTMSG(#EXP, EXP) |