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https://github.com/sinara-hw/Kasli.git
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1ee0c9c9f6
Added DC blocking capacitors on SFP lines Added dust covers for SFP SMA clock input goes to the FPGA Added 2x DCXOs Switched ADCLK944 to ADCLK948 for clock mux Added 12V0->5V0 buck and 5V0->3V3 regulator for ADCLK948 and Si5324 (Si549 DCXO uses 2V5 LDO) Moved most of GPIO signals to I2C extender (interrupts go to the FPGA_ Added stacked 2x1 SFP cage Removed backplane connector and clock signal that went to it Added 4x EEM connectors Switched FTDI buck to LDO with higher input voltage range Switched the FPGA to -3 speed grade Changed some designators Schematic compiles without any errors
3 lines
109 B
Plaintext
Executable File
3 lines
109 B
Plaintext
Executable File
SFP=TX_FAULT,TX_DISABLE,SDA,SCL,MOD_PRESENT,RATE_SELECT,LOS,RATE_SELECT1,LED
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SFP_RX_TX=RD_P,RD_N,TD_P,TD_N
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