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Short-Term/designer/netrev_constraint_report.xml
2021-07-20 16:39:56 +08:00

35 lines
1.3 KiB
XML

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet type="text/xsl" href="file:///C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/pcb/consmgr/VDD/report/treeview.xsl"?>
<ConstraintDifferenceReport Path="file:///C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/pcb/consmgr/VDD/report/rc" Status="no-change" Type="Constraint Difference Report">
<RptSummary Col1="Layout" Col2="Schematic">
<Entry Name="Report time">Sat Jul 17 21:40:06 2021
</Entry>
<Entry Name="Software version">17.2 (P019)</Entry>
<Entry Name="Layout">C:\Users\Jimmy-X\Desktop\短学期\designer\pcb.brd</Entry>
<Entry Name="Schematic">C:\Users\Jimmy-X\Desktop\短学期\designer\worklib\52\packaged\pstcmdb.dat</Entry>
<Entry Name="Baseline File">C:\Users\Jimmy-X\AppData\Local\Temp\#Taaaaae25504.tmp</Entry>
<Entry Name="Destination design updated">Yes</Entry>
<Entry Name="Update Mode">Diff3</Entry>
<Entry Name="Constraint Information">Electrical, NetClasses, Properties</Entry>
</RptSummary>
<Tree>
<Item Filter="0x1" Name="Summary" Ref="main-summary"/>
</Tree>
<Summaries>
<MainSummary ID="main-summary"/>
</Summaries>
<Layers>
<Layer Name="TOP" Type="Conductor"/>
<Layer Name="BOTTOM" Type="Conductor"/>
</Layers>
<GenericLayers>
<Layer Name="Conductor"/>
</GenericLayers>
</ConstraintDifferenceReport>