mirror of
https://github.com/Jimmy-Bots/Short-Term.git
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114 lines
4.6 KiB
Plaintext
114 lines
4.6 KiB
Plaintext
(---------------------------------------------------------------------)
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( )
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( Allegro Netrev Import Logic )
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( )
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( Drawing : pcb.brd )
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( Software Version : 17.2P019 )
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( Date/Time : Sat Jul 17 19:10:50 2021 )
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( )
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(---------------------------------------------------------------------)
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------ Directives ------------
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Ripup etch: No
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Ripup delete first segment: No
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Ripup retain bondwire: No
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Ripup symbols: Always
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Missing symbol has error: No
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DRC update: Yes
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Schematic directory: 'C:\Users\Jimmy-X\Desktop\短学期\designer\worklib\52\packaged'
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Design Directory: '.'
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Old design name: 'C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/physical/pcb.brd'
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New design name: 'C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/physical/pcb.brd'
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CmdLine: netrev -proj C:\Users\Jimmy-X\Desktop\短学期\designer\52.cpm -y 1 -O C:\Users\Jimmy-X\Desktop\短学期\designer\worklib\52\physical\pcb.brd C:\Users\Jimmy-X\Desktop\短学期\designer\worklib\52\physical\pcb.brd -q C:\Users\Jimmy-X\Desktop\短学期\designer\temp\constraints_difference_report.xml -$
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------ Preparing to read pst files ------
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Starting to read C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/packaged/pstchip.dat
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Finished reading C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/packaged/pstchip.dat (00:00:00.28)
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Starting to read C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/packaged/pstxprt.dat
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Finished reading C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/packaged/pstxprt.dat (00:00:00.00)
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Starting to read C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/packaged/pstxnet.dat
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Finished reading C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/packaged/pstxnet.dat (00:00:00.00)
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------ Oversights/Warnings/Errors ------
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===========================================================
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Start Constraint Diff3 Import
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Constraint File: C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/packaged/pstcmdb.dat
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Allegro Baseline: C:/Users/Jimmy-X/AppData/Local/Temp/#Taaaaae27924.tmp
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Start time: Sat Jul 17 19:10:50 2021
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===========================================================
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The constraint difference report file can be viewed using the following command:
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C:\Cadence17\Cadence\Cadence_SPB_17.2-2016\tools\fet\projmgr\bin\firefox.exe -app C:\Cadence17\Cadence\Cadence_SPB_17.2-2016\share\pcb\consmgr\VDD\diff3rptViewer\diff3rptViewer.ini -file file:///C:/Users/Jimmy-X/Desktop/短学期/designer/temp/constraints_difference_report.xml
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NOTE: Constraint information is up-to-date. No processing was required.
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===========================================================
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Finished Constraint Update Time: Sat Jul 17 19:10:50 2021
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===========================================================
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------ Library Paths ------
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MODULEPATH = .
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C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/local/pcb/modules
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PSMPATH = .
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symbols
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..
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../symbols
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C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/local/pcb/symbols
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C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/pcb/pcb_lib/symbols
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C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/pcb/allegrolib/symbols
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C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/physical/
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PADPATH = .
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symbols
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..
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../symbols
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C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/local/pcb/padstacks
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C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/pcb/pcb_lib/symbols
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C:/Cadence17/Cadence/Cadence_SPB_17.2-2016/share/pcb/allegrolib/symbols
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C:/Users/Jimmy-X/Desktop/短学期/designer/worklib/52/physical/
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------ Summary Statistics ------
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netrev run on Jul 17 19:10:50 2021
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DESIGN NAME : '52'
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PACKAGING ON 17-Jul-2021 AT 19:10:47
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COMPILE 'logic'
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CHECK_PIN_NAMES OFF
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CROSS_REFERENCE OFF
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DIRECTORIES <none>
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FEEDBACK OFF
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INCREMENTAL OFF
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INTERFACE_TYPE PHYSICAL
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LIBRARIES '52_lib' 'standard'
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MASTER_LIBRARIES <none>
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MAX_ERRORS 500
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MERGE_MINIMUM 5
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NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
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NET_NAME_LENGTH 24
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OVERSIGHTS ON
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REPLACE_CHECK OFF
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SINGLE_NODE_NETS ON
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SPLIT_MINIMUM 0
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SUPPRESS 20
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WARNINGS ON
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No error detected
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No oversight detected
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No warning detected
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cpu time 0:01:58
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elapsed time 0:00:00
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