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2021-07-20 16:39:56 +08:00

17 lines
433 B
VHDL

-- generated by newgenasym Fri Jul 16 10:21:26 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity at24c02 is
port (
A0: INOUT STD_LOGIC;
A1: INOUT STD_LOGIC;
A2: INOUT STD_LOGIC;
GND: INOUT STD_LOGIC;
SCL: INOUT STD_LOGIC;
SDA: INOUT STD_LOGIC;
VCC: INOUT STD_LOGIC;
WP: INOUT STD_LOGIC);
end at24c02;