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15 lines
183 B
Verilog
15 lines
183 B
Verilog
// generated by newgenasym Fri Jul 16 11:57:50 2021
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module bjt_pnp (\1 , \2 , \3 );
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inout \1 ;
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inout \2 ;
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inout \3 ;
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initial
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begin
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end
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endmodule
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