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12 lines
263 B
VHDL
12 lines
263 B
VHDL
-- generated by newgenasym Fri Jul 16 11:57:50 2021
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity bjt_pnp is
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port (
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\1\: INOUT STD_LOGIC;
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\2\: INOUT STD_LOGIC;
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\3\: INOUT STD_LOGIC);
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end bjt_pnp;
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