0
mirror of https://github.com/Jimmy-Bots/Short-Term.git synced 2026-02-26 07:27:40 +00:00
2021-07-20 16:39:56 +08:00

12 lines
263 B
VHDL

-- generated by newgenasym Fri Jul 16 11:57:50 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity bjt_pnp is
port (
\1\: INOUT STD_LOGIC;
\2\: INOUT STD_LOGIC;
\3\: INOUT STD_LOGIC);
end bjt_pnp;