mirror of
https://github.com/Jimmy-Bots/Short-Term.git
synced 2026-03-24 02:43:46 +00:00
11 lines
237 B
VHDL
11 lines
237 B
VHDL
-- generated by newgenasym Thu Jul 15 18:07:05 2021
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity capacitance is
|
|
port (
|
|
\1\: INOUT STD_LOGIC;
|
|
\2\: INOUT STD_LOGIC);
|
|
end capacitance;
|