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Files
2021-07-20 16:39:56 +08:00

25 lines
705 B
VHDL

-- generated by newgenasym Fri Jul 16 11:24:38 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity lcd1602 is
port (
BLA: INOUT STD_LOGIC;
BLK: INOUT STD_LOGIC;
D0: INOUT STD_LOGIC;
D1: INOUT STD_LOGIC;
D2: INOUT STD_LOGIC;
D3: INOUT STD_LOGIC;
D4: INOUT STD_LOGIC;
D5: INOUT STD_LOGIC;
D6: INOUT STD_LOGIC;
D7: INOUT STD_LOGIC;
E: INOUT STD_LOGIC;
GND: INOUT STD_LOGIC;
\r/w\: INOUT STD_LOGIC;
RS: INOUT STD_LOGIC;
VCC: INOUT STD_LOGIC;
VL: INOUT STD_LOGIC);
end lcd1602;