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2021-07-20 16:39:56 +08:00

11 lines
221 B
VHDL

-- generated by newgenasym Wed Jul 14 13:49:46 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity led is
port (
\1\: INOUT STD_LOGIC;
\2\: INOUT STD_LOGIC);
end led;