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mirror of https://github.com/Jimmy-Bots/Short-Term.git synced 2026-03-20 10:35:38 +00:00
2021-07-20 16:39:56 +08:00

23 lines
633 B
VHDL

-- generated by newgenasym Wed Jul 14 19:38:27 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity lm339 is
port (
GND: INOUT STD_LOGIC;
\in+(1)\: INOUT STD_LOGIC;
\in+(2)\: INOUT STD_LOGIC;
\in+(3)\: INOUT STD_LOGIC;
\in+(4)\: INOUT STD_LOGIC;
\in-(1)\: INOUT STD_LOGIC;
\in-(2)\: INOUT STD_LOGIC;
\in-(3)\: INOUT STD_LOGIC;
\in-(4)\: INOUT STD_LOGIC;
OUT1: INOUT STD_LOGIC;
OUT2: INOUT STD_LOGIC;
OUT3: INOUT STD_LOGIC;
OUT4: INOUT STD_LOGIC;
VCC: INOUT STD_LOGIC);
end lm339;