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2021-07-20 16:39:56 +08:00

17 lines
429 B
VHDL

-- generated by newgenasym Wed Jul 14 19:38:27 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity lm358 is
port (
GND: INOUT STD_LOGIC;
\ina+\: INOUT STD_LOGIC;
\ina-\: INOUT STD_LOGIC;
\inb+\: INOUT STD_LOGIC;
\inb-\: INOUT STD_LOGIC;
OUTA: INOUT STD_LOGIC;
OUTB: INOUT STD_LOGIC;
VCC: INOUT STD_LOGIC);
end lm358;