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13 lines
299 B
VHDL
13 lines
299 B
VHDL
-- generated by newgenasym Thu Jul 15 19:13:43 2021
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mlx90614 is
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port (
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GND: OUT STD_LOGIC;
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SCL: OUT STD_LOGIC;
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SDA: OUT STD_LOGIC;
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VCC: OUT STD_LOGIC);
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end mlx90614;
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