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16 lines
393 B
VHDL
16 lines
393 B
VHDL
-- generated by newgenasym Fri Jul 16 11:27:52 2021
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity oled is
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port (
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CS: INOUT STD_LOGIC;
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DC: INOUT STD_LOGIC;
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GND: INOUT STD_LOGIC;
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RES: INOUT STD_LOGIC;
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SCL: INOUT STD_LOGIC;
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SDA: INOUT STD_LOGIC;
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VCC: INOUT STD_LOGIC);
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end oled;
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