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12 lines
275 B
VHDL
12 lines
275 B
VHDL
-- generated by newgenasym Wed Jul 14 19:38:27 2021
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity potentiometer is
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port (
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CCW: INOUT STD_LOGIC;
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CW: INOUT STD_LOGIC;
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WIPER: INOUT STD_LOGIC);
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end potentiometer;
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