mirror of
https://github.com/Jimmy-Bots/Short-Term.git
synced 2026-03-30 03:13:50 +00:00
14 lines
164 B
Verilog
14 lines
164 B
Verilog
// generated by newgenasym Thu Jul 15 17:56:55 2021
|
|
|
|
|
|
module resistor (\1 , \2 );
|
|
inout \1 ;
|
|
inout \2 ;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|